1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * meson-mx-sdio.c - Meson6, Meson8 and Meson8b SDIO/MMC Host Controller
4 *
5 * Copyright (C) 2015 Endless Mobile, Inc.
6 * Author: Carlo Caione <carlo@endlessm.com>
7 * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
8 */
9
10 #include <linux/bitfield.h>
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/ioport.h>
20 #include <linux/platform_device.h>
21 #include <linux/of_platform.h>
22 #include <linux/regmap.h>
23 #include <linux/timer.h>
24 #include <linux/types.h>
25
26 #include <linux/mmc/host.h>
27 #include <linux/mmc/mmc.h>
28 #include <linux/mmc/sdio.h>
29 #include <linux/mmc/slot-gpio.h>
30
31 #define MESON_MX_SDIO_ARGU 0x00
32
33 #define MESON_MX_SDIO_SEND 0x04
34 #define MESON_MX_SDIO_SEND_COMMAND_INDEX_MASK GENMASK(7, 0)
35 #define MESON_MX_SDIO_SEND_CMD_RESP_BITS_MASK GENMASK(15, 8)
36 #define MESON_MX_SDIO_SEND_RESP_WITHOUT_CRC7 BIT(16)
37 #define MESON_MX_SDIO_SEND_RESP_HAS_DATA BIT(17)
38 #define MESON_MX_SDIO_SEND_RESP_CRC7_FROM_8 BIT(18)
39 #define MESON_MX_SDIO_SEND_CHECK_DAT0_BUSY BIT(19)
40 #define MESON_MX_SDIO_SEND_DATA BIT(20)
41 #define MESON_MX_SDIO_SEND_USE_INT_WINDOW BIT(21)
42 #define MESON_MX_SDIO_SEND_REPEAT_PACKAGE_TIMES_MASK GENMASK(31, 24)
43
44 #define MESON_MX_SDIO_CONF 0x08
45 #define MESON_MX_SDIO_CONF_CMD_CLK_DIV_SHIFT 0
46 #define MESON_MX_SDIO_CONF_CMD_CLK_DIV_WIDTH 10
47 #define MESON_MX_SDIO_CONF_CMD_DISABLE_CRC BIT(10)
48 #define MESON_MX_SDIO_CONF_CMD_OUT_AT_POSITIVE_EDGE BIT(11)
49 #define MESON_MX_SDIO_CONF_CMD_ARGUMENT_BITS_MASK GENMASK(17, 12)
50 #define MESON_MX_SDIO_CONF_RESP_LATCH_AT_NEGATIVE_EDGE BIT(18)
51 #define MESON_MX_SDIO_CONF_DATA_LATCH_AT_NEGATIVE_EDGE BIT(19)
52 #define MESON_MX_SDIO_CONF_BUS_WIDTH BIT(20)
53 #define MESON_MX_SDIO_CONF_M_ENDIAN_MASK GENMASK(22, 21)
54 #define MESON_MX_SDIO_CONF_WRITE_NWR_MASK GENMASK(28, 23)
55 #define MESON_MX_SDIO_CONF_WRITE_CRC_OK_STATUS_MASK GENMASK(31, 29)
56
57 #define MESON_MX_SDIO_IRQS 0x0c
58 #define MESON_MX_SDIO_IRQS_STATUS_STATE_MACHINE_MASK GENMASK(3, 0)
59 #define MESON_MX_SDIO_IRQS_CMD_BUSY BIT(4)
60 #define MESON_MX_SDIO_IRQS_RESP_CRC7_OK BIT(5)
61 #define MESON_MX_SDIO_IRQS_DATA_READ_CRC16_OK BIT(6)
62 #define MESON_MX_SDIO_IRQS_DATA_WRITE_CRC16_OK BIT(7)
63 #define MESON_MX_SDIO_IRQS_IF_INT BIT(8)
64 #define MESON_MX_SDIO_IRQS_CMD_INT BIT(9)
65 #define MESON_MX_SDIO_IRQS_STATUS_INFO_MASK GENMASK(15, 12)
66 #define MESON_MX_SDIO_IRQS_TIMING_OUT_INT BIT(16)
67 #define MESON_MX_SDIO_IRQS_AMRISC_TIMING_OUT_INT_EN BIT(17)
68 #define MESON_MX_SDIO_IRQS_ARC_TIMING_OUT_INT_EN BIT(18)
69 #define MESON_MX_SDIO_IRQS_TIMING_OUT_COUNT_MASK GENMASK(31, 19)
70
71 #define MESON_MX_SDIO_IRQC 0x10
72 #define MESON_MX_SDIO_IRQC_ARC_IF_INT_EN BIT(3)
73 #define MESON_MX_SDIO_IRQC_ARC_CMD_INT_EN BIT(4)
74 #define MESON_MX_SDIO_IRQC_IF_CONFIG_MASK GENMASK(7, 6)
75 #define MESON_MX_SDIO_IRQC_FORCE_DATA_CLK BIT(8)
76 #define MESON_MX_SDIO_IRQC_FORCE_DATA_CMD BIT(9)
77 #define MESON_MX_SDIO_IRQC_FORCE_DATA_DAT_MASK GENMASK(13, 10)
78 #define MESON_MX_SDIO_IRQC_SOFT_RESET BIT(15)
79 #define MESON_MX_SDIO_IRQC_FORCE_HALT BIT(30)
80 #define MESON_MX_SDIO_IRQC_HALT_HOLE BIT(31)
81
82 #define MESON_MX_SDIO_MULT 0x14
83 #define MESON_MX_SDIO_MULT_PORT_SEL_MASK GENMASK(1, 0)
84 #define MESON_MX_SDIO_MULT_MEMORY_STICK_ENABLE BIT(2)
85 #define MESON_MX_SDIO_MULT_MEMORY_STICK_SCLK_ALWAYS BIT(3)
86 #define MESON_MX_SDIO_MULT_STREAM_ENABLE BIT(4)
87 #define MESON_MX_SDIO_MULT_STREAM_8BITS_MODE BIT(5)
88 #define MESON_MX_SDIO_MULT_WR_RD_OUT_INDEX BIT(8)
89 #define MESON_MX_SDIO_MULT_DAT0_DAT1_SWAPPED BIT(10)
90 #define MESON_MX_SDIO_MULT_DAT1_DAT0_SWAPPED BIT(11)
91 #define MESON_MX_SDIO_MULT_RESP_READ_INDEX_MASK GENMASK(15, 12)
92
93 #define MESON_MX_SDIO_ADDR 0x18
94
95 #define MESON_MX_SDIO_EXT 0x1c
96 #define MESON_MX_SDIO_EXT_DATA_RW_NUMBER_MASK GENMASK(29, 16)
97
98 #define MESON_MX_SDIO_BOUNCE_REQ_SIZE (128 * 1024)
99 #define MESON_MX_SDIO_RESPONSE_CRC16_BITS (16 - 1)
100 #define MESON_MX_SDIO_MAX_SLOTS 3
101
102 struct meson_mx_mmc_host_clkc {
103 struct clk_divider cfg_div;
104 struct clk_fixed_factor fixed_div2;
105 };
106
107 struct meson_mx_mmc_host {
108 struct device *controller_dev;
109
110 struct clk *cfg_div_clk;
111 struct regmap *regmap;
112 int irq;
113 spinlock_t irq_lock;
114
115 struct timer_list cmd_timeout;
116
117 unsigned int slot_id;
118 struct mmc_host *mmc;
119
120 struct mmc_request *mrq;
121 struct mmc_command *cmd;
122 int error;
123 };
124
meson_mx_mmc_soft_reset(struct meson_mx_mmc_host * host)125 static void meson_mx_mmc_soft_reset(struct meson_mx_mmc_host *host)
126 {
127 regmap_write(host->regmap, MESON_MX_SDIO_IRQC,
128 MESON_MX_SDIO_IRQC_SOFT_RESET);
129 udelay(2);
130 }
131
meson_mx_mmc_get_next_cmd(struct mmc_command * cmd)132 static struct mmc_command *meson_mx_mmc_get_next_cmd(struct mmc_command *cmd)
133 {
134 if (cmd->opcode == MMC_SET_BLOCK_COUNT && !cmd->error)
135 return cmd->mrq->cmd;
136 else if (mmc_op_multi(cmd->opcode) &&
137 (!cmd->mrq->sbc || cmd->error || cmd->data->error))
138 return cmd->mrq->stop;
139 else
140 return NULL;
141 }
142
meson_mx_mmc_start_cmd(struct mmc_host * mmc,struct mmc_command * cmd)143 static void meson_mx_mmc_start_cmd(struct mmc_host *mmc,
144 struct mmc_command *cmd)
145 {
146 struct meson_mx_mmc_host *host = mmc_priv(mmc);
147 unsigned int pack_size;
148 unsigned long irqflags, timeout;
149 u32 send = 0, ext = 0;
150
151 host->cmd = cmd;
152
153 if (cmd->busy_timeout)
154 timeout = msecs_to_jiffies(cmd->busy_timeout);
155 else
156 timeout = msecs_to_jiffies(1000);
157
158 switch (mmc_resp_type(cmd)) {
159 case MMC_RSP_R1:
160 case MMC_RSP_R1B:
161 case MMC_RSP_R3:
162 /* 7 (CMD) + 32 (response) + 7 (CRC) -1 */
163 send |= FIELD_PREP(MESON_MX_SDIO_SEND_CMD_RESP_BITS_MASK, 45);
164 break;
165 case MMC_RSP_R2:
166 /* 7 (CMD) + 120 (response) + 7 (CRC) -1 */
167 send |= FIELD_PREP(MESON_MX_SDIO_SEND_CMD_RESP_BITS_MASK, 133);
168 send |= MESON_MX_SDIO_SEND_RESP_CRC7_FROM_8;
169 break;
170 default:
171 break;
172 }
173
174 if (!(cmd->flags & MMC_RSP_CRC))
175 send |= MESON_MX_SDIO_SEND_RESP_WITHOUT_CRC7;
176
177 if (cmd->flags & MMC_RSP_BUSY)
178 send |= MESON_MX_SDIO_SEND_CHECK_DAT0_BUSY;
179
180 if (cmd->data) {
181 send |= FIELD_PREP(MESON_MX_SDIO_SEND_REPEAT_PACKAGE_TIMES_MASK,
182 (cmd->data->blocks - 1));
183
184 pack_size = cmd->data->blksz * BITS_PER_BYTE;
185 if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
186 pack_size += MESON_MX_SDIO_RESPONSE_CRC16_BITS * 4;
187 else
188 pack_size += MESON_MX_SDIO_RESPONSE_CRC16_BITS * 1;
189
190 ext |= FIELD_PREP(MESON_MX_SDIO_EXT_DATA_RW_NUMBER_MASK,
191 pack_size);
192
193 if (cmd->data->flags & MMC_DATA_WRITE)
194 send |= MESON_MX_SDIO_SEND_DATA;
195 else
196 send |= MESON_MX_SDIO_SEND_RESP_HAS_DATA;
197
198 cmd->data->bytes_xfered = 0;
199 }
200
201 send |= FIELD_PREP(MESON_MX_SDIO_SEND_COMMAND_INDEX_MASK,
202 (0x40 | cmd->opcode));
203
204 spin_lock_irqsave(&host->irq_lock, irqflags);
205
206 regmap_update_bits(host->regmap, MESON_MX_SDIO_MULT,
207 MESON_MX_SDIO_MULT_PORT_SEL_MASK | BIT(31),
208 FIELD_PREP(MESON_MX_SDIO_MULT_PORT_SEL_MASK,
209 host->slot_id) | BIT(31));
210
211 /* enable the CMD done interrupt */
212 regmap_set_bits(host->regmap, MESON_MX_SDIO_IRQC,
213 MESON_MX_SDIO_IRQC_ARC_CMD_INT_EN);
214
215 /* clear pending interrupts */
216 regmap_set_bits(host->regmap, MESON_MX_SDIO_IRQS,
217 MESON_MX_SDIO_IRQS_CMD_INT);
218
219 regmap_write(host->regmap, MESON_MX_SDIO_ARGU, cmd->arg);
220 regmap_write(host->regmap, MESON_MX_SDIO_EXT, ext);
221 regmap_write(host->regmap, MESON_MX_SDIO_SEND, send);
222
223 spin_unlock_irqrestore(&host->irq_lock, irqflags);
224
225 mod_timer(&host->cmd_timeout, jiffies + timeout);
226 }
227
meson_mx_mmc_request_done(struct meson_mx_mmc_host * host)228 static void meson_mx_mmc_request_done(struct meson_mx_mmc_host *host)
229 {
230 struct mmc_request *mrq;
231
232 mrq = host->mrq;
233
234 if (host->cmd->error)
235 meson_mx_mmc_soft_reset(host);
236
237 host->mrq = NULL;
238 host->cmd = NULL;
239
240 mmc_request_done(host->mmc, mrq);
241 }
242
meson_mx_mmc_set_ios(struct mmc_host * mmc,struct mmc_ios * ios)243 static void meson_mx_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
244 {
245 struct meson_mx_mmc_host *host = mmc_priv(mmc);
246 unsigned short vdd = ios->vdd;
247 unsigned long clk_rate = ios->clock;
248
249 switch (ios->bus_width) {
250 case MMC_BUS_WIDTH_1:
251 regmap_clear_bits(host->regmap, MESON_MX_SDIO_CONF,
252 MESON_MX_SDIO_CONF_BUS_WIDTH);
253 break;
254
255 case MMC_BUS_WIDTH_4:
256 regmap_set_bits(host->regmap, MESON_MX_SDIO_CONF,
257 MESON_MX_SDIO_CONF_BUS_WIDTH);
258 break;
259
260 case MMC_BUS_WIDTH_8:
261 default:
262 dev_err(mmc_dev(mmc), "unsupported bus width: %d\n",
263 ios->bus_width);
264 host->error = -EINVAL;
265 return;
266 }
267
268 host->error = clk_set_rate(host->cfg_div_clk, ios->clock);
269 if (host->error) {
270 dev_warn(mmc_dev(mmc),
271 "failed to set MMC clock to %lu: %d\n",
272 clk_rate, host->error);
273 return;
274 }
275
276 mmc->actual_clock = clk_get_rate(host->cfg_div_clk);
277
278 switch (ios->power_mode) {
279 case MMC_POWER_OFF:
280 vdd = 0;
281 fallthrough;
282 case MMC_POWER_UP:
283 if (!IS_ERR(mmc->supply.vmmc)) {
284 host->error = mmc_regulator_set_ocr(mmc,
285 mmc->supply.vmmc,
286 vdd);
287 if (host->error)
288 return;
289 }
290 break;
291 }
292 }
293
meson_mx_mmc_map_dma(struct mmc_host * mmc,struct mmc_request * mrq)294 static int meson_mx_mmc_map_dma(struct mmc_host *mmc, struct mmc_request *mrq)
295 {
296 struct mmc_data *data = mrq->data;
297 int dma_len;
298 struct scatterlist *sg;
299
300 if (!data)
301 return 0;
302
303 sg = data->sg;
304 if (sg->offset & 3 || sg->length & 3) {
305 dev_err(mmc_dev(mmc),
306 "unaligned scatterlist: offset %x length %d\n",
307 sg->offset, sg->length);
308 return -EINVAL;
309 }
310
311 dma_len = dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len,
312 mmc_get_dma_dir(data));
313 if (dma_len <= 0) {
314 dev_err(mmc_dev(mmc), "dma_map_sg failed\n");
315 return -ENOMEM;
316 }
317
318 return 0;
319 }
320
meson_mx_mmc_request(struct mmc_host * mmc,struct mmc_request * mrq)321 static void meson_mx_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
322 {
323 struct meson_mx_mmc_host *host = mmc_priv(mmc);
324 struct mmc_command *cmd = mrq->cmd;
325
326 if (!host->error)
327 host->error = meson_mx_mmc_map_dma(mmc, mrq);
328
329 if (host->error) {
330 cmd->error = host->error;
331 mmc_request_done(mmc, mrq);
332 return;
333 }
334
335 host->mrq = mrq;
336
337 if (mrq->data)
338 regmap_write(host->regmap, MESON_MX_SDIO_ADDR,
339 sg_dma_address(mrq->data->sg));
340
341 if (mrq->sbc)
342 meson_mx_mmc_start_cmd(mmc, mrq->sbc);
343 else
344 meson_mx_mmc_start_cmd(mmc, mrq->cmd);
345 }
346
meson_mx_mmc_read_response(struct mmc_host * mmc,struct mmc_command * cmd)347 static void meson_mx_mmc_read_response(struct mmc_host *mmc,
348 struct mmc_command *cmd)
349 {
350 struct meson_mx_mmc_host *host = mmc_priv(mmc);
351 unsigned int i, resp[4];
352
353 regmap_update_bits(host->regmap, MESON_MX_SDIO_MULT,
354 MESON_MX_SDIO_MULT_WR_RD_OUT_INDEX |
355 MESON_MX_SDIO_MULT_RESP_READ_INDEX_MASK,
356 MESON_MX_SDIO_MULT_WR_RD_OUT_INDEX |
357 FIELD_PREP(MESON_MX_SDIO_MULT_RESP_READ_INDEX_MASK,
358 0));
359
360 if (cmd->flags & MMC_RSP_136) {
361 for (i = 0; i <= 3; i++)
362 regmap_read(host->regmap, MESON_MX_SDIO_ARGU,
363 &resp[3 - i]);
364
365 cmd->resp[0] = (resp[0] << 8) | ((resp[1] >> 24) & 0xff);
366 cmd->resp[1] = (resp[1] << 8) | ((resp[2] >> 24) & 0xff);
367 cmd->resp[2] = (resp[2] << 8) | ((resp[3] >> 24) & 0xff);
368 cmd->resp[3] = (resp[3] << 8);
369 } else if (cmd->flags & MMC_RSP_PRESENT) {
370 regmap_read(host->regmap, MESON_MX_SDIO_ARGU, &cmd->resp[0]);
371 }
372 }
373
meson_mx_mmc_process_cmd_irq(struct meson_mx_mmc_host * host,u32 irqs,u32 send)374 static irqreturn_t meson_mx_mmc_process_cmd_irq(struct meson_mx_mmc_host *host,
375 u32 irqs, u32 send)
376 {
377 struct mmc_command *cmd = host->cmd;
378
379 /*
380 * NOTE: even though it shouldn't happen we sometimes get command
381 * interrupts twice (at least this is what it looks like). Ideally
382 * we find out why this happens and warn here as soon as it occurs.
383 */
384 if (!cmd)
385 return IRQ_HANDLED;
386
387 cmd->error = 0;
388 meson_mx_mmc_read_response(host->mmc, cmd);
389
390 if (cmd->data) {
391 if (!((irqs & MESON_MX_SDIO_IRQS_DATA_READ_CRC16_OK) ||
392 (irqs & MESON_MX_SDIO_IRQS_DATA_WRITE_CRC16_OK)))
393 cmd->error = -EILSEQ;
394 } else {
395 if (!((irqs & MESON_MX_SDIO_IRQS_RESP_CRC7_OK) ||
396 (send & MESON_MX_SDIO_SEND_RESP_WITHOUT_CRC7)))
397 cmd->error = -EILSEQ;
398 }
399
400 return IRQ_WAKE_THREAD;
401 }
402
meson_mx_mmc_irq(int irq,void * data)403 static irqreturn_t meson_mx_mmc_irq(int irq, void *data)
404 {
405 struct meson_mx_mmc_host *host = (void *) data;
406 u32 irqs, send;
407 irqreturn_t ret;
408
409 spin_lock(&host->irq_lock);
410
411 regmap_read(host->regmap, MESON_MX_SDIO_IRQS, &irqs);
412 regmap_read(host->regmap, MESON_MX_SDIO_SEND, &send);
413
414 if (irqs & MESON_MX_SDIO_IRQS_CMD_INT)
415 ret = meson_mx_mmc_process_cmd_irq(host, irqs, send);
416 else
417 ret = IRQ_HANDLED;
418
419 /* finally ACK all pending interrupts */
420 regmap_write(host->regmap, MESON_MX_SDIO_IRQS, irqs);
421
422 spin_unlock(&host->irq_lock);
423
424 return ret;
425 }
426
meson_mx_mmc_irq_thread(int irq,void * irq_data)427 static irqreturn_t meson_mx_mmc_irq_thread(int irq, void *irq_data)
428 {
429 struct meson_mx_mmc_host *host = (void *) irq_data;
430 struct mmc_command *cmd = host->cmd, *next_cmd;
431
432 if (WARN_ON(!cmd))
433 return IRQ_HANDLED;
434
435 timer_delete_sync(&host->cmd_timeout);
436
437 if (cmd->data) {
438 dma_unmap_sg(mmc_dev(host->mmc), cmd->data->sg,
439 cmd->data->sg_len, mmc_get_dma_dir(cmd->data));
440
441 cmd->data->bytes_xfered = cmd->data->blksz * cmd->data->blocks;
442 }
443
444 next_cmd = meson_mx_mmc_get_next_cmd(cmd);
445 if (next_cmd)
446 meson_mx_mmc_start_cmd(host->mmc, next_cmd);
447 else
448 meson_mx_mmc_request_done(host);
449
450 return IRQ_HANDLED;
451 }
452
meson_mx_mmc_timeout(struct timer_list * t)453 static void meson_mx_mmc_timeout(struct timer_list *t)
454 {
455 struct meson_mx_mmc_host *host = timer_container_of(host, t,
456 cmd_timeout);
457 unsigned long irqflags;
458 u32 irqs, argu;
459
460 spin_lock_irqsave(&host->irq_lock, irqflags);
461
462 /* disable the CMD interrupt */
463 regmap_clear_bits(host->regmap, MESON_MX_SDIO_IRQC,
464 MESON_MX_SDIO_IRQC_ARC_CMD_INT_EN);
465
466 spin_unlock_irqrestore(&host->irq_lock, irqflags);
467
468 /*
469 * skip the timeout handling if the interrupt handler already processed
470 * the command.
471 */
472 if (!host->cmd)
473 return;
474
475 regmap_read(host->regmap, MESON_MX_SDIO_IRQS, &irqs);
476 regmap_read(host->regmap, MESON_MX_SDIO_ARGU, &argu);
477
478 dev_dbg(mmc_dev(host->mmc),
479 "Timeout on CMD%u (IRQS = 0x%08x, ARGU = 0x%08x)\n",
480 host->cmd->opcode, irqs, argu);
481
482 host->cmd->error = -ETIMEDOUT;
483
484 meson_mx_mmc_request_done(host);
485 }
486
487 static struct mmc_host_ops meson_mx_mmc_ops = {
488 .request = meson_mx_mmc_request,
489 .set_ios = meson_mx_mmc_set_ios,
490 .get_cd = mmc_gpio_get_cd,
491 .get_ro = mmc_gpio_get_ro,
492 };
493
meson_mx_mmc_slot_pdev(struct device * parent)494 static struct platform_device *meson_mx_mmc_slot_pdev(struct device *parent)
495 {
496 struct platform_device *pdev = NULL;
497
498 for_each_available_child_of_node_scoped(parent->of_node, slot_node) {
499 if (!of_device_is_compatible(slot_node, "mmc-slot"))
500 continue;
501
502 /*
503 * TODO: the MMC core framework currently does not support
504 * controllers with multiple slots properly. So we only
505 * register the first slot for now.
506 */
507 if (pdev) {
508 dev_warn(parent,
509 "more than one 'mmc-slot' compatible child found - using the first one and ignoring all subsequent ones\n");
510 break;
511 }
512
513 pdev = of_platform_device_create(slot_node, NULL, parent);
514 if (!pdev)
515 dev_err(parent,
516 "Failed to create platform device for mmc-slot node '%pOF'\n",
517 slot_node);
518 }
519
520 return pdev;
521 }
522
meson_mx_mmc_add_host(struct meson_mx_mmc_host * host)523 static int meson_mx_mmc_add_host(struct meson_mx_mmc_host *host)
524 {
525 struct mmc_host *mmc = host->mmc;
526 struct device *slot_dev = mmc_dev(mmc);
527 int ret;
528
529 if (of_property_read_u32(slot_dev->of_node, "reg", &host->slot_id))
530 return dev_err_probe(slot_dev, -EINVAL,
531 "missing 'reg' property\n");
532
533 if (host->slot_id >= MESON_MX_SDIO_MAX_SLOTS)
534 return dev_err_probe(slot_dev, -EINVAL,
535 "invalid 'reg' property value %d\n",
536 host->slot_id);
537
538 /* Get regulators and the supported OCR mask */
539 ret = mmc_regulator_get_supply(mmc);
540 if (ret)
541 return ret;
542
543 mmc->max_req_size = MESON_MX_SDIO_BOUNCE_REQ_SIZE;
544 mmc->max_seg_size = mmc->max_req_size;
545 mmc->max_blk_count =
546 FIELD_GET(MESON_MX_SDIO_SEND_REPEAT_PACKAGE_TIMES_MASK,
547 0xffffffff);
548 mmc->max_blk_size = FIELD_GET(MESON_MX_SDIO_EXT_DATA_RW_NUMBER_MASK,
549 0xffffffff);
550 mmc->max_blk_size -= (4 * MESON_MX_SDIO_RESPONSE_CRC16_BITS);
551 mmc->max_blk_size /= BITS_PER_BYTE;
552
553 /* Get the min and max supported clock rates */
554 mmc->f_min = clk_round_rate(host->cfg_div_clk, 1);
555 mmc->f_max = clk_round_rate(host->cfg_div_clk, ULONG_MAX);
556
557 mmc->caps |= MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY;
558 mmc->ops = &meson_mx_mmc_ops;
559
560 ret = mmc_of_parse(mmc);
561 if (ret)
562 return ret;
563
564 ret = mmc_add_host(mmc);
565 if (ret)
566 return ret;
567
568 return 0;
569 }
570
meson_mx_mmc_register_clk(struct device * dev,void __iomem * base)571 static struct clk *meson_mx_mmc_register_clk(struct device *dev,
572 void __iomem *base)
573 {
574 const char *fixed_div2_name, *cfg_div_name;
575 struct meson_mx_mmc_host_clkc *host_clkc;
576 struct clk *clk;
577 int ret;
578
579 /* use a dedicated memory allocation for the clock controller to
580 * prevent use-after-free as meson_mx_mmc_host is free'd before
581 * dev (controller dev, not mmc_host->dev) is free'd.
582 */
583 host_clkc = devm_kzalloc(dev, sizeof(*host_clkc), GFP_KERNEL);
584 if (!host_clkc)
585 return ERR_PTR(-ENOMEM);
586
587 fixed_div2_name = devm_kasprintf(dev, GFP_KERNEL, "%s#fixed_div2",
588 dev_name(dev));
589 if (!fixed_div2_name)
590 return ERR_PTR(-ENOMEM);
591
592 host_clkc->fixed_div2.div = 2;
593 host_clkc->fixed_div2.mult = 1;
594 host_clkc->fixed_div2.hw.init = CLK_HW_INIT_FW_NAME(fixed_div2_name,
595 "clkin",
596 &clk_fixed_factor_ops,
597 0);
598 ret = devm_clk_hw_register(dev, &host_clkc->fixed_div2.hw);
599 if (ret)
600 return dev_err_ptr_probe(dev, ret,
601 "Failed to register %s clock\n",
602 fixed_div2_name);
603
604 cfg_div_name = devm_kasprintf(dev, GFP_KERNEL, "%s#div", dev_name(dev));
605 if (!cfg_div_name)
606 return ERR_PTR(-ENOMEM);
607
608 host_clkc->cfg_div.reg = base + MESON_MX_SDIO_CONF;
609 host_clkc->cfg_div.shift = MESON_MX_SDIO_CONF_CMD_CLK_DIV_SHIFT;
610 host_clkc->cfg_div.width = MESON_MX_SDIO_CONF_CMD_CLK_DIV_WIDTH;
611 host_clkc->cfg_div.hw.init = CLK_HW_INIT_HW(cfg_div_name,
612 &host_clkc->fixed_div2.hw,
613 &clk_divider_ops,
614 CLK_DIVIDER_ALLOW_ZERO);
615 ret = devm_clk_hw_register(dev, &host_clkc->cfg_div.hw);
616 if (ret)
617 return dev_err_ptr_probe(dev, ret,
618 "Failed to register %s clock\n",
619 cfg_div_name);
620
621 clk = devm_clk_hw_get_clk(dev, &host_clkc->cfg_div.hw, "cfg_div_clk");
622 if (IS_ERR(clk))
623 return dev_err_ptr_probe(dev, PTR_ERR(clk),
624 "Failed to get the cfg_div clock\n");
625
626 return clk;
627 }
628
meson_mx_mmc_probe(struct platform_device * pdev)629 static int meson_mx_mmc_probe(struct platform_device *pdev)
630 {
631 const struct regmap_config meson_mx_sdio_regmap_config = {
632 .reg_bits = 8,
633 .val_bits = 32,
634 .reg_stride = 4,
635 .max_register = MESON_MX_SDIO_EXT,
636 };
637 struct platform_device *slot_pdev;
638 struct mmc_host *mmc;
639 struct meson_mx_mmc_host *host;
640 struct clk *core_clk;
641 void __iomem *base;
642 int ret, irq;
643 u32 conf;
644
645 base = devm_platform_ioremap_resource(pdev, 0);
646 if (IS_ERR(base))
647 return PTR_ERR(base);
648
649 slot_pdev = meson_mx_mmc_slot_pdev(&pdev->dev);
650 if (!slot_pdev)
651 return -ENODEV;
652
653 mmc = devm_mmc_alloc_host(&slot_pdev->dev, sizeof(*host));
654 if (!mmc) {
655 ret = -ENOMEM;
656 goto error_unregister_slot_pdev;
657 }
658
659 host = mmc_priv(mmc);
660 host->mmc = mmc;
661 host->controller_dev = &pdev->dev;
662
663 spin_lock_init(&host->irq_lock);
664 timer_setup(&host->cmd_timeout, meson_mx_mmc_timeout, 0);
665
666 platform_set_drvdata(pdev, host);
667
668 host->regmap = devm_regmap_init_mmio(&pdev->dev, base,
669 &meson_mx_sdio_regmap_config);
670 if (IS_ERR(host->regmap)) {
671 ret = dev_err_probe(host->controller_dev, PTR_ERR(host->regmap),
672 "Failed to initialize regmap\n");
673 goto error_unregister_slot_pdev;
674 }
675
676 irq = platform_get_irq(pdev, 0);
677 if (irq < 0) {
678 ret = irq;
679 goto error_unregister_slot_pdev;
680 }
681
682 ret = devm_request_threaded_irq(host->controller_dev, irq,
683 meson_mx_mmc_irq,
684 meson_mx_mmc_irq_thread, IRQF_ONESHOT,
685 NULL, host);
686 if (ret) {
687 dev_err_probe(host->controller_dev, ret,
688 "Failed to request IRQ\n");
689 goto error_unregister_slot_pdev;
690 }
691
692 core_clk = devm_clk_get_enabled(host->controller_dev, "core");
693 if (IS_ERR(core_clk)) {
694 ret = dev_err_probe(host->controller_dev, PTR_ERR(core_clk),
695 "Failed to get and enable 'core' clock\n");
696 goto error_unregister_slot_pdev;
697 }
698
699 host->cfg_div_clk = meson_mx_mmc_register_clk(&pdev->dev, base);
700 if (IS_ERR(host->cfg_div_clk)) {
701 ret = PTR_ERR(host->cfg_div_clk);
702 goto error_unregister_slot_pdev;
703 }
704
705 ret = clk_prepare_enable(host->cfg_div_clk);
706 if (ret) {
707 dev_err_probe(host->controller_dev, ret,
708 "Failed to enable MMC (cfg div) clock\n");
709 goto error_unregister_slot_pdev;
710 }
711
712 conf = 0;
713 conf |= FIELD_PREP(MESON_MX_SDIO_CONF_CMD_ARGUMENT_BITS_MASK, 39);
714 conf |= FIELD_PREP(MESON_MX_SDIO_CONF_M_ENDIAN_MASK, 0x3);
715 conf |= FIELD_PREP(MESON_MX_SDIO_CONF_WRITE_NWR_MASK, 0x2);
716 conf |= FIELD_PREP(MESON_MX_SDIO_CONF_WRITE_CRC_OK_STATUS_MASK, 0x2);
717 regmap_write(host->regmap, MESON_MX_SDIO_CONF, conf);
718
719 meson_mx_mmc_soft_reset(host);
720
721 ret = meson_mx_mmc_add_host(host);
722 if (ret)
723 goto error_disable_div_clk;
724
725 return 0;
726
727 error_disable_div_clk:
728 clk_disable_unprepare(host->cfg_div_clk);
729 error_unregister_slot_pdev:
730 of_platform_device_destroy(&slot_pdev->dev, NULL);
731 return ret;
732 }
733
meson_mx_mmc_remove(struct platform_device * pdev)734 static void meson_mx_mmc_remove(struct platform_device *pdev)
735 {
736 struct meson_mx_mmc_host *host = platform_get_drvdata(pdev);
737 struct device *slot_dev = mmc_dev(host->mmc);
738
739 timer_delete_sync(&host->cmd_timeout);
740
741 mmc_remove_host(host->mmc);
742
743 of_platform_device_destroy(slot_dev, NULL);
744
745 clk_disable_unprepare(host->cfg_div_clk);
746 }
747
748 static const struct of_device_id meson_mx_mmc_of_match[] = {
749 { .compatible = "amlogic,meson8-sdio", },
750 { .compatible = "amlogic,meson8b-sdio", },
751 { /* sentinel */ }
752 };
753 MODULE_DEVICE_TABLE(of, meson_mx_mmc_of_match);
754
755 static struct platform_driver meson_mx_mmc_driver = {
756 .probe = meson_mx_mmc_probe,
757 .remove = meson_mx_mmc_remove,
758 .driver = {
759 .name = "meson-mx-sdio",
760 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
761 .of_match_table = of_match_ptr(meson_mx_mmc_of_match),
762 },
763 };
764
765 module_platform_driver(meson_mx_mmc_driver);
766
767 MODULE_DESCRIPTION("Meson6, Meson8 and Meson8b SDIO/MMC Host Driver");
768 MODULE_AUTHOR("Carlo Caione <carlo@endlessm.com>");
769 MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
770 MODULE_LICENSE("GPL v2");
771