1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2021 Alibaba Group Holding Limited. 4 * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> 5 */ 6 7#include <dt-bindings/interrupt-controller/irq.h> 8#include <dt-bindings/clock/thead,th1520-clk-ap.h> 9#include <dt-bindings/power/thead,th1520-power.h> 10#include <dt-bindings/reset/thead,th1520-reset.h> 11 12/ { 13 compatible = "thead,th1520"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 cpus: cpus { 18 #address-cells = <1>; 19 #size-cells = <0>; 20 timebase-frequency = <3000000>; 21 22 c910_0: cpu@0 { 23 compatible = "thead,c910", "riscv"; 24 device_type = "cpu"; 25 riscv,isa = "rv64imafdc"; 26 riscv,isa-base = "rv64i"; 27 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", 28 "zifencei", "zihpm"; 29 reg = <0>; 30 i-cache-block-size = <64>; 31 i-cache-size = <65536>; 32 i-cache-sets = <512>; 33 d-cache-block-size = <64>; 34 d-cache-size = <65536>; 35 d-cache-sets = <512>; 36 next-level-cache = <&l2_cache>; 37 mmu-type = "riscv,sv39"; 38 39 cpu0_intc: interrupt-controller { 40 compatible = "riscv,cpu-intc"; 41 interrupt-controller; 42 #interrupt-cells = <1>; 43 }; 44 }; 45 46 c910_1: cpu@1 { 47 compatible = "thead,c910", "riscv"; 48 device_type = "cpu"; 49 riscv,isa = "rv64imafdc"; 50 riscv,isa-base = "rv64i"; 51 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", 52 "zifencei", "zihpm"; 53 reg = <1>; 54 i-cache-block-size = <64>; 55 i-cache-size = <65536>; 56 i-cache-sets = <512>; 57 d-cache-block-size = <64>; 58 d-cache-size = <65536>; 59 d-cache-sets = <512>; 60 next-level-cache = <&l2_cache>; 61 mmu-type = "riscv,sv39"; 62 63 cpu1_intc: interrupt-controller { 64 compatible = "riscv,cpu-intc"; 65 interrupt-controller; 66 #interrupt-cells = <1>; 67 }; 68 }; 69 70 c910_2: cpu@2 { 71 compatible = "thead,c910", "riscv"; 72 device_type = "cpu"; 73 riscv,isa = "rv64imafdc"; 74 riscv,isa-base = "rv64i"; 75 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", 76 "zifencei", "zihpm"; 77 reg = <2>; 78 i-cache-block-size = <64>; 79 i-cache-size = <65536>; 80 i-cache-sets = <512>; 81 d-cache-block-size = <64>; 82 d-cache-size = <65536>; 83 d-cache-sets = <512>; 84 next-level-cache = <&l2_cache>; 85 mmu-type = "riscv,sv39"; 86 87 cpu2_intc: interrupt-controller { 88 compatible = "riscv,cpu-intc"; 89 interrupt-controller; 90 #interrupt-cells = <1>; 91 }; 92 }; 93 94 c910_3: cpu@3 { 95 compatible = "thead,c910", "riscv"; 96 device_type = "cpu"; 97 riscv,isa = "rv64imafdc"; 98 riscv,isa-base = "rv64i"; 99 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", 100 "zifencei", "zihpm"; 101 reg = <3>; 102 i-cache-block-size = <64>; 103 i-cache-size = <65536>; 104 i-cache-sets = <512>; 105 d-cache-block-size = <64>; 106 d-cache-size = <65536>; 107 d-cache-sets = <512>; 108 next-level-cache = <&l2_cache>; 109 mmu-type = "riscv,sv39"; 110 111 cpu3_intc: interrupt-controller { 112 compatible = "riscv,cpu-intc"; 113 interrupt-controller; 114 #interrupt-cells = <1>; 115 }; 116 }; 117 118 l2_cache: l2-cache { 119 compatible = "cache"; 120 cache-block-size = <64>; 121 cache-level = <2>; 122 cache-size = <1048576>; 123 cache-sets = <1024>; 124 cache-unified; 125 }; 126 }; 127 128 pmu { 129 compatible = "riscv,pmu"; 130 riscv,event-to-mhpmcounters = 131 <0x00003 0x00003 0x0007fff8>, 132 <0x00004 0x00004 0x0007fff8>, 133 <0x00005 0x00005 0x0007fff8>, 134 <0x00006 0x00006 0x0007fff8>, 135 <0x00007 0x00007 0x0007fff8>, 136 <0x00008 0x00008 0x0007fff8>, 137 <0x00009 0x00009 0x0007fff8>, 138 <0x0000a 0x0000a 0x0007fff8>, 139 <0x10000 0x10000 0x0007fff8>, 140 <0x10001 0x10001 0x0007fff8>, 141 <0x10002 0x10002 0x0007fff8>, 142 <0x10003 0x10003 0x0007fff8>, 143 <0x10010 0x10010 0x0007fff8>, 144 <0x10011 0x10011 0x0007fff8>, 145 <0x10012 0x10012 0x0007fff8>, 146 <0x10013 0x10013 0x0007fff8>; 147 riscv,event-to-mhpmevent = 148 <0x00003 0x00000000 0x00000001>, 149 <0x00004 0x00000000 0x00000002>, 150 <0x00006 0x00000000 0x00000006>, 151 <0x00005 0x00000000 0x00000007>, 152 <0x00007 0x00000000 0x00000008>, 153 <0x00008 0x00000000 0x00000009>, 154 <0x00009 0x00000000 0x0000000a>, 155 <0x0000a 0x00000000 0x0000000b>, 156 <0x10000 0x00000000 0x0000000c>, 157 <0x10001 0x00000000 0x0000000d>, 158 <0x10002 0x00000000 0x0000000e>, 159 <0x10003 0x00000000 0x0000000f>, 160 <0x10010 0x00000000 0x00000010>, 161 <0x10011 0x00000000 0x00000011>, 162 <0x10012 0x00000000 0x00000012>, 163 <0x10013 0x00000000 0x00000013>; 164 riscv,raw-event-to-mhpmcounters = 165 <0x00000000 0x00000001 0xffffffff 0xffffffff 0x0007fff8>, 166 <0x00000000 0x00000002 0xffffffff 0xffffffff 0x0007fff8>, 167 <0x00000000 0x00000003 0xffffffff 0xffffffff 0x0007fff8>, 168 <0x00000000 0x00000004 0xffffffff 0xffffffff 0x0007fff8>, 169 <0x00000000 0x00000005 0xffffffff 0xffffffff 0x0007fff8>, 170 <0x00000000 0x00000006 0xffffffff 0xffffffff 0x0007fff8>, 171 <0x00000000 0x00000007 0xffffffff 0xffffffff 0x0007fff8>, 172 <0x00000000 0x00000008 0xffffffff 0xffffffff 0x0007fff8>, 173 <0x00000000 0x00000009 0xffffffff 0xffffffff 0x0007fff8>, 174 <0x00000000 0x0000000a 0xffffffff 0xffffffff 0x0007fff8>, 175 <0x00000000 0x0000000b 0xffffffff 0xffffffff 0x0007fff8>, 176 <0x00000000 0x0000000c 0xffffffff 0xffffffff 0x0007fff8>, 177 <0x00000000 0x0000000d 0xffffffff 0xffffffff 0x0007fff8>, 178 <0x00000000 0x0000000e 0xffffffff 0xffffffff 0x0007fff8>, 179 <0x00000000 0x0000000f 0xffffffff 0xffffffff 0x0007fff8>, 180 <0x00000000 0x00000010 0xffffffff 0xffffffff 0x0007fff8>, 181 <0x00000000 0x00000011 0xffffffff 0xffffffff 0x0007fff8>, 182 <0x00000000 0x00000012 0xffffffff 0xffffffff 0x0007fff8>, 183 <0x00000000 0x00000013 0xffffffff 0xffffffff 0x0007fff8>, 184 <0x00000000 0x00000014 0xffffffff 0xffffffff 0x0007fff8>, 185 <0x00000000 0x00000015 0xffffffff 0xffffffff 0x0007fff8>, 186 <0x00000000 0x00000016 0xffffffff 0xffffffff 0x0007fff8>, 187 <0x00000000 0x00000017 0xffffffff 0xffffffff 0x0007fff8>, 188 <0x00000000 0x00000018 0xffffffff 0xffffffff 0x0007fff8>, 189 <0x00000000 0x00000019 0xffffffff 0xffffffff 0x0007fff8>, 190 <0x00000000 0x0000001a 0xffffffff 0xffffffff 0x0007fff8>, 191 <0x00000000 0x0000001b 0xffffffff 0xffffffff 0x0007fff8>, 192 <0x00000000 0x0000001c 0xffffffff 0xffffffff 0x0007fff8>, 193 <0x00000000 0x0000001d 0xffffffff 0xffffffff 0x0007fff8>, 194 <0x00000000 0x0000001e 0xffffffff 0xffffffff 0x0007fff8>, 195 <0x00000000 0x0000001f 0xffffffff 0xffffffff 0x0007fff8>, 196 <0x00000000 0x00000020 0xffffffff 0xffffffff 0x0007fff8>, 197 <0x00000000 0x00000021 0xffffffff 0xffffffff 0x0007fff8>, 198 <0x00000000 0x00000022 0xffffffff 0xffffffff 0x0007fff8>, 199 <0x00000000 0x00000023 0xffffffff 0xffffffff 0x0007fff8>, 200 <0x00000000 0x00000024 0xffffffff 0xffffffff 0x0007fff8>, 201 <0x00000000 0x00000025 0xffffffff 0xffffffff 0x0007fff8>, 202 <0x00000000 0x00000026 0xffffffff 0xffffffff 0x0007fff8>, 203 <0x00000000 0x00000027 0xffffffff 0xffffffff 0x0007fff8>, 204 <0x00000000 0x00000028 0xffffffff 0xffffffff 0x0007fff8>, 205 <0x00000000 0x00000029 0xffffffff 0xffffffff 0x0007fff8>, 206 <0x00000000 0x0000002a 0xffffffff 0xffffffff 0x0007fff8>; 207 }; 208 209 osc: oscillator { 210 compatible = "fixed-clock"; 211 clock-output-names = "osc_24m"; 212 #clock-cells = <0>; 213 }; 214 215 osc_32k: 32k-oscillator { 216 compatible = "fixed-clock"; 217 clock-output-names = "osc_32k"; 218 #clock-cells = <0>; 219 }; 220 221 aonsys_clk: clock-73728000 { 222 compatible = "fixed-clock"; 223 clock-frequency = <73728000>; 224 clock-output-names = "aonsys_clk"; 225 #clock-cells = <0>; 226 }; 227 228 stmmac_axi_config: stmmac-axi-config { 229 snps,wr_osr_lmt = <15>; 230 snps,rd_osr_lmt = <15>; 231 snps,blen = <0 0 64 32 0 0 0>; 232 }; 233 234 aon: aon { 235 compatible = "thead,th1520-aon"; 236 mboxes = <&mbox_910t 1>; 237 mbox-names = "aon"; 238 resets = <&rst TH1520_RESET_ID_GPU_CLKGEN>; 239 reset-names = "gpu-clkgen"; 240 #power-domain-cells = <1>; 241 }; 242 243 soc { 244 compatible = "simple-bus"; 245 interrupt-parent = <&plic>; 246 #address-cells = <2>; 247 #size-cells = <2>; 248 dma-noncoherent; 249 ranges; 250 251 plic: interrupt-controller@ffd8000000 { 252 compatible = "thead,th1520-plic", "thead,c900-plic"; 253 reg = <0xff 0xd8000000 0x0 0x01000000>; 254 interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, 255 <&cpu1_intc 11>, <&cpu1_intc 9>, 256 <&cpu2_intc 11>, <&cpu2_intc 9>, 257 <&cpu3_intc 11>, <&cpu3_intc 9>; 258 interrupt-controller; 259 #address-cells = <0>; 260 #interrupt-cells = <2>; 261 riscv,ndev = <240>; 262 }; 263 264 clint: timer@ffdc000000 { 265 compatible = "thead,th1520-clint", "thead,c900-clint"; 266 reg = <0xff 0xdc000000 0x0 0x00010000>; 267 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, 268 <&cpu1_intc 3>, <&cpu1_intc 7>, 269 <&cpu2_intc 3>, <&cpu2_intc 7>, 270 <&cpu3_intc 3>, <&cpu3_intc 7>; 271 }; 272 273 spi0: spi@ffe700c000 { 274 compatible = "thead,th1520-spi", "snps,dw-apb-ssi"; 275 reg = <0xff 0xe700c000 0x0 0x1000>; 276 interrupts = <54 IRQ_TYPE_LEVEL_HIGH>; 277 clocks = <&clk CLK_SPI>; 278 #address-cells = <1>; 279 #size-cells = <0>; 280 status = "disabled"; 281 }; 282 283 uart0: serial@ffe7014000 { 284 compatible = "snps,dw-apb-uart"; 285 reg = <0xff 0xe7014000 0x0 0x100>; 286 interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; 287 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART0_PCLK>; 288 clock-names = "baudclk", "apb_pclk"; 289 reg-shift = <2>; 290 reg-io-width = <4>; 291 status = "disabled"; 292 }; 293 294 gmac1: ethernet@ffe7060000 { 295 compatible = "thead,th1520-gmac", "snps,dwmac-3.70a"; 296 reg = <0xff 0xe7060000 0x0 0x2000>, <0xff 0xec004000 0x0 0x1000>; 297 reg-names = "dwmac", "apb"; 298 interrupts = <67 IRQ_TYPE_LEVEL_HIGH>; 299 interrupt-names = "macirq"; 300 clocks = <&clk CLK_GMAC_AXI>, <&clk CLK_GMAC1>, 301 <&clk CLK_PERISYS_APB4_HCLK>; 302 clock-names = "stmmaceth", "pclk", "apb"; 303 snps,pbl = <32>; 304 snps,fixed-burst; 305 snps,multicast-filter-bins = <64>; 306 snps,perfect-filter-entries = <32>; 307 snps,axi-config = <&stmmac_axi_config>; 308 status = "disabled"; 309 310 mdio1: mdio { 311 compatible = "snps,dwmac-mdio"; 312 #address-cells = <1>; 313 #size-cells = <0>; 314 }; 315 }; 316 317 gmac0: ethernet@ffe7070000 { 318 compatible = "thead,th1520-gmac", "snps,dwmac-3.70a"; 319 reg = <0xff 0xe7070000 0x0 0x2000>, <0xff 0xec003000 0x0 0x1000>; 320 reg-names = "dwmac", "apb"; 321 interrupts = <66 IRQ_TYPE_LEVEL_HIGH>; 322 interrupt-names = "macirq"; 323 clocks = <&clk CLK_GMAC_AXI>, <&clk CLK_GMAC0>, 324 <&clk CLK_PERISYS_APB4_HCLK>; 325 clock-names = "stmmaceth", "pclk", "apb"; 326 snps,pbl = <32>; 327 snps,fixed-burst; 328 snps,multicast-filter-bins = <64>; 329 snps,perfect-filter-entries = <32>; 330 snps,axi-config = <&stmmac_axi_config>; 331 status = "disabled"; 332 333 mdio0: mdio { 334 compatible = "snps,dwmac-mdio"; 335 #address-cells = <1>; 336 #size-cells = <0>; 337 }; 338 }; 339 340 emmc: mmc@ffe7080000 { 341 compatible = "thead,th1520-dwcmshc"; 342 reg = <0xff 0xe7080000 0x0 0x10000>; 343 interrupts = <62 IRQ_TYPE_LEVEL_HIGH>; 344 clocks = <&clk CLK_EMMC_SDIO>; 345 clock-names = "core"; 346 status = "disabled"; 347 }; 348 349 sdio0: mmc@ffe7090000 { 350 compatible = "thead,th1520-dwcmshc"; 351 reg = <0xff 0xe7090000 0x0 0x10000>; 352 interrupts = <64 IRQ_TYPE_LEVEL_HIGH>; 353 clocks = <&clk CLK_EMMC_SDIO>; 354 clock-names = "core"; 355 status = "disabled"; 356 }; 357 358 sdio1: mmc@ffe70a0000 { 359 compatible = "thead,th1520-dwcmshc"; 360 reg = <0xff 0xe70a0000 0x0 0x10000>; 361 interrupts = <71 IRQ_TYPE_LEVEL_HIGH>; 362 clocks = <&clk CLK_EMMC_SDIO>; 363 clock-names = "core"; 364 status = "disabled"; 365 }; 366 367 uart1: serial@ffe7f00000 { 368 compatible = "snps,dw-apb-uart"; 369 reg = <0xff 0xe7f00000 0x0 0x100>; 370 interrupts = <37 IRQ_TYPE_LEVEL_HIGH>; 371 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART1_PCLK>; 372 clock-names = "baudclk", "apb_pclk"; 373 reg-shift = <2>; 374 reg-io-width = <4>; 375 status = "disabled"; 376 }; 377 378 uart3: serial@ffe7f04000 { 379 compatible = "snps,dw-apb-uart"; 380 reg = <0xff 0xe7f04000 0x0 0x100>; 381 interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; 382 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART3_PCLK>; 383 clock-names = "baudclk", "apb_pclk"; 384 reg-shift = <2>; 385 reg-io-width = <4>; 386 status = "disabled"; 387 }; 388 389 gpio@ffe7f34000 { 390 compatible = "snps,dw-apb-gpio"; 391 reg = <0xff 0xe7f34000 0x0 0x1000>; 392 #address-cells = <1>; 393 #size-cells = <0>; 394 clocks = <&clk CLK_GPIO2>; 395 clock-names = "bus"; 396 397 gpio2: gpio-controller@0 { 398 compatible = "snps,dw-apb-gpio-port"; 399 gpio-controller; 400 #gpio-cells = <2>; 401 ngpios = <32>; 402 gpio-ranges = <&padctrl0_apsys 0 0 32>; 403 reg = <0>; 404 interrupt-controller; 405 #interrupt-cells = <2>; 406 interrupts = <58 IRQ_TYPE_LEVEL_HIGH>; 407 }; 408 }; 409 410 gpio@ffe7f38000 { 411 compatible = "snps,dw-apb-gpio"; 412 reg = <0xff 0xe7f38000 0x0 0x1000>; 413 #address-cells = <1>; 414 #size-cells = <0>; 415 clocks = <&clk CLK_GPIO3>; 416 clock-names = "bus"; 417 418 gpio3: gpio-controller@0 { 419 compatible = "snps,dw-apb-gpio-port"; 420 gpio-controller; 421 #gpio-cells = <2>; 422 ngpios = <23>; 423 gpio-ranges = <&padctrl0_apsys 0 32 23>; 424 reg = <0>; 425 interrupt-controller; 426 #interrupt-cells = <2>; 427 interrupts = <59 IRQ_TYPE_LEVEL_HIGH>; 428 }; 429 }; 430 431 padctrl1_apsys: pinctrl@ffe7f3c000 { 432 compatible = "thead,th1520-pinctrl"; 433 reg = <0xff 0xe7f3c000 0x0 0x1000>; 434 clocks = <&clk CLK_PADCTRL1>; 435 thead,pad-group = <2>; 436 }; 437 438 gpio@ffec005000 { 439 compatible = "snps,dw-apb-gpio"; 440 reg = <0xff 0xec005000 0x0 0x1000>; 441 #address-cells = <1>; 442 #size-cells = <0>; 443 clocks = <&clk CLK_GPIO0>; 444 clock-names = "bus"; 445 446 gpio0: gpio-controller@0 { 447 compatible = "snps,dw-apb-gpio-port"; 448 gpio-controller; 449 #gpio-cells = <2>; 450 ngpios = <32>; 451 gpio-ranges = <&padctrl1_apsys 0 0 32>; 452 reg = <0>; 453 interrupt-controller; 454 #interrupt-cells = <2>; 455 interrupts = <56 IRQ_TYPE_LEVEL_HIGH>; 456 }; 457 }; 458 459 gpio@ffec006000 { 460 compatible = "snps,dw-apb-gpio"; 461 reg = <0xff 0xec006000 0x0 0x1000>; 462 #address-cells = <1>; 463 #size-cells = <0>; 464 clocks = <&clk CLK_GPIO1>; 465 clock-names = "bus"; 466 467 gpio1: gpio-controller@0 { 468 compatible = "snps,dw-apb-gpio-port"; 469 gpio-controller; 470 #gpio-cells = <2>; 471 ngpios = <31>; 472 gpio-ranges = <&padctrl1_apsys 0 32 31>; 473 reg = <0>; 474 interrupt-controller; 475 #interrupt-cells = <2>; 476 interrupts = <57 IRQ_TYPE_LEVEL_HIGH>; 477 }; 478 }; 479 480 padctrl0_apsys: pinctrl@ffec007000 { 481 compatible = "thead,th1520-pinctrl"; 482 reg = <0xff 0xec007000 0x0 0x1000>; 483 clocks = <&clk CLK_PADCTRL0>; 484 thead,pad-group = <3>; 485 }; 486 487 uart2: serial@ffec010000 { 488 compatible = "snps,dw-apb-uart"; 489 reg = <0xff 0xec010000 0x0 0x4000>; 490 interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; 491 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART2_PCLK>; 492 clock-names = "baudclk", "apb_pclk"; 493 reg-shift = <2>; 494 reg-io-width = <4>; 495 status = "disabled"; 496 }; 497 498 clk: clock-controller@ffef010000 { 499 compatible = "thead,th1520-clk-ap"; 500 reg = <0xff 0xef010000 0x0 0x1000>; 501 clocks = <&osc>; 502 #clock-cells = <1>; 503 }; 504 505 rst: reset-controller@ffef528000 { 506 compatible = "thead,th1520-reset"; 507 reg = <0xff 0xef528000 0x0 0x4f>; 508 #reset-cells = <1>; 509 }; 510 511 clk_vo: clock-controller@ffef528050 { 512 compatible = "thead,th1520-clk-vo"; 513 reg = <0xff 0xef528050 0x0 0xfb0>; 514 clocks = <&clk CLK_VIDEO_PLL>; 515 #clock-cells = <1>; 516 }; 517 518 dmac0: dma-controller@ffefc00000 { 519 compatible = "snps,axi-dma-1.01a"; 520 reg = <0xff 0xefc00000 0x0 0x1000>; 521 interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; 522 clocks = <&clk CLK_PERI_APB_PCLK>, <&clk CLK_PERI_APB_PCLK>; 523 clock-names = "core-clk", "cfgr-clk"; 524 #dma-cells = <1>; 525 dma-channels = <4>; 526 snps,block-size = <65536 65536 65536 65536>; 527 snps,priority = <0 1 2 3>; 528 snps,dma-masters = <1>; 529 snps,data-width = <4>; 530 snps,axi-max-burst-len = <16>; 531 status = "disabled"; 532 }; 533 534 timer0: timer@ffefc32000 { 535 compatible = "snps,dw-apb-timer"; 536 reg = <0xff 0xefc32000 0x0 0x14>; 537 clocks = <&clk CLK_PERI_APB_PCLK>; 538 clock-names = "timer"; 539 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; 540 status = "disabled"; 541 }; 542 543 timer1: timer@ffefc32014 { 544 compatible = "snps,dw-apb-timer"; 545 reg = <0xff 0xefc32014 0x0 0x14>; 546 clocks = <&clk CLK_PERI_APB_PCLK>; 547 clock-names = "timer"; 548 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; 549 status = "disabled"; 550 }; 551 552 timer2: timer@ffefc32028 { 553 compatible = "snps,dw-apb-timer"; 554 reg = <0xff 0xefc32028 0x0 0x14>; 555 clocks = <&clk CLK_PERI_APB_PCLK>; 556 clock-names = "timer"; 557 interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; 558 status = "disabled"; 559 }; 560 561 timer3: timer@ffefc3203c { 562 compatible = "snps,dw-apb-timer"; 563 reg = <0xff 0xefc3203c 0x0 0x14>; 564 clocks = <&clk CLK_PERI_APB_PCLK>; 565 clock-names = "timer"; 566 interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; 567 status = "disabled"; 568 }; 569 570 uart4: serial@fff7f08000 { 571 compatible = "snps,dw-apb-uart"; 572 reg = <0xff 0xf7f08000 0x0 0x4000>; 573 interrupts = <40 IRQ_TYPE_LEVEL_HIGH>; 574 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART4_PCLK>; 575 clock-names = "baudclk", "apb_pclk"; 576 reg-shift = <2>; 577 reg-io-width = <4>; 578 status = "disabled"; 579 }; 580 581 uart5: serial@fff7f0c000 { 582 compatible = "snps,dw-apb-uart"; 583 reg = <0xff 0xf7f0c000 0x0 0x4000>; 584 interrupts = <41 IRQ_TYPE_LEVEL_HIGH>; 585 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART5_PCLK>; 586 clock-names = "baudclk", "apb_pclk"; 587 reg-shift = <2>; 588 reg-io-width = <4>; 589 status = "disabled"; 590 }; 591 592 timer4: timer@ffffc33000 { 593 compatible = "snps,dw-apb-timer"; 594 reg = <0xff 0xffc33000 0x0 0x14>; 595 clocks = <&clk CLK_PERI_APB_PCLK>; 596 clock-names = "timer"; 597 interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; 598 status = "disabled"; 599 }; 600 601 timer5: timer@ffffc33014 { 602 compatible = "snps,dw-apb-timer"; 603 reg = <0xff 0xffc33014 0x0 0x14>; 604 clocks = <&clk CLK_PERI_APB_PCLK>; 605 clock-names = "timer"; 606 interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; 607 status = "disabled"; 608 }; 609 610 timer6: timer@ffffc33028 { 611 compatible = "snps,dw-apb-timer"; 612 reg = <0xff 0xffc33028 0x0 0x14>; 613 clocks = <&clk CLK_PERI_APB_PCLK>; 614 clock-names = "timer"; 615 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; 616 status = "disabled"; 617 }; 618 619 timer7: timer@ffffc3303c { 620 compatible = "snps,dw-apb-timer"; 621 reg = <0xff 0xffc3303c 0x0 0x14>; 622 clocks = <&clk CLK_PERI_APB_PCLK>; 623 clock-names = "timer"; 624 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; 625 status = "disabled"; 626 }; 627 628 mbox_910t: mailbox@ffffc38000 { 629 compatible = "thead,th1520-mbox"; 630 reg = <0xff 0xffc38000 0x0 0x6000>, 631 <0xff 0xffc40000 0x0 0x6000>, 632 <0xff 0xffc4c000 0x0 0x2000>, 633 <0xff 0xffc54000 0x0 0x2000>; 634 reg-names = "local", "remote-icu0", "remote-icu1", "remote-icu2"; 635 clocks = <&clk CLK_MBOX0>, <&clk CLK_MBOX1>, <&clk CLK_MBOX2>, 636 <&clk CLK_MBOX3>; 637 clock-names = "clk-local", "clk-remote-icu0", "clk-remote-icu1", 638 "clk-remote-icu2"; 639 interrupt-parent = <&plic>; 640 interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; 641 #mbox-cells = <1>; 642 }; 643 644 gpio@fffff41000 { 645 compatible = "snps,dw-apb-gpio"; 646 reg = <0xff 0xfff41000 0x0 0x1000>; 647 #address-cells = <1>; 648 #size-cells = <0>; 649 650 aogpio: gpio-controller@0 { 651 compatible = "snps,dw-apb-gpio-port"; 652 gpio-controller; 653 #gpio-cells = <2>; 654 ngpios = <16>; 655 gpio-ranges = <&padctrl_aosys 0 9 16>; 656 reg = <0>; 657 interrupt-controller; 658 #interrupt-cells = <2>; 659 interrupts = <76 IRQ_TYPE_LEVEL_HIGH>; 660 }; 661 }; 662 663 padctrl_aosys: pinctrl@fffff4a000 { 664 compatible = "thead,th1520-pinctrl"; 665 reg = <0xff 0xfff4a000 0x0 0x2000>; 666 clocks = <&aonsys_clk>; 667 thead,pad-group = <1>; 668 }; 669 670 pvt: pvt@fffff4e000 { 671 compatible = "moortec,mr75203"; 672 reg = <0xff 0xfff4e000 0x0 0x80>, 673 <0xff 0xfff4e080 0x0 0x100>, 674 <0xff 0xfff4e180 0x0 0x680>, 675 <0xff 0xfff4e800 0x0 0x600>; 676 reg-names = "common", "ts", "pd", "vm"; 677 clocks = <&aonsys_clk>; 678 #thermal-sensor-cells = <1>; 679 }; 680 681 gpio@fffff52000 { 682 compatible = "snps,dw-apb-gpio"; 683 reg = <0xff 0xfff52000 0x0 0x1000>; 684 #address-cells = <1>; 685 #size-cells = <0>; 686 687 gpio4: gpio-controller@0 { 688 compatible = "snps,dw-apb-gpio-port"; 689 gpio-controller; 690 #gpio-cells = <2>; 691 ngpios = <23>; 692 gpio-ranges = <&padctrl_aosys 0 25 22>, <&padctrl_aosys 22 7 1>; 693 reg = <0>; 694 interrupt-controller; 695 #interrupt-cells = <2>; 696 interrupts = <55 IRQ_TYPE_LEVEL_HIGH>; 697 }; 698 }; 699 }; 700}; 701