1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree Source for J784S4 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_main { 9 watchdog4: watchdog@2240000 { 10 compatible = "ti,j7-rti-wdt"; 11 reg = <0x00 0x2240000 0x00 0x100>; 12 clocks = <&k3_clks 352 0>; 13 power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>; 14 assigned-clocks = <&k3_clks 352 0>; 15 assigned-clock-parents = <&k3_clks 352 4>; 16 }; 17 18 watchdog5: watchdog@2250000 { 19 compatible = "ti,j7-rti-wdt"; 20 reg = <0x00 0x2250000 0x00 0x100>; 21 clocks = <&k3_clks 353 0>; 22 power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>; 23 assigned-clocks = <&k3_clks 353 0>; 24 assigned-clock-parents = <&k3_clks 353 4>; 25 }; 26 27 watchdog6: watchdog@2260000 { 28 compatible = "ti,j7-rti-wdt"; 29 reg = <0x00 0x2260000 0x00 0x100>; 30 clocks = <&k3_clks 354 0>; 31 power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>; 32 assigned-clocks = <&k3_clks 354 0>; 33 assigned-clock-parents = <&k3_clks 354 4>; 34 }; 35 36 watchdog7: watchdog@2270000 { 37 compatible = "ti,j7-rti-wdt"; 38 reg = <0x00 0x2270000 0x00 0x100>; 39 clocks = <&k3_clks 355 0>; 40 power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>; 41 assigned-clocks = <&k3_clks 355 0>; 42 assigned-clock-parents = <&k3_clks 355 4>; 43 }; 44 45 pcie2_rc: pcie@2920000 { 46 compatible = "ti,j784s4-pcie-host"; 47 reg = <0x00 0x02920000 0x00 0x1000>, 48 <0x00 0x02927000 0x00 0x400>, 49 <0x00 0x0e000000 0x00 0x00800000>, 50 <0x44 0x00000000 0x00 0x00001000>; 51 ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>, 52 <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>; 53 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 54 interrupt-names = "link_state"; 55 interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>; 56 device_type = "pci"; 57 max-link-speed = <3>; 58 num-lanes = <2>; 59 power-domains = <&k3_pds 334 TI_SCI_PD_EXCLUSIVE>; 60 clocks = <&k3_clks 334 0>; 61 clock-names = "fck"; 62 #address-cells = <3>; 63 #size-cells = <2>; 64 bus-range = <0x0 0xff>; 65 vendor-id = <0x104c>; 66 device-id = <0xb012>; 67 msi-map = <0x0 &gic_its 0x20000 0x10000>; 68 dma-coherent; 69 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 70 ti,syscon-pcie-ctrl = <&pcie2_ctrl 0x0>; 71 status = "disabled"; 72 }; 73 74 pcie3_rc: pcie@2930000 { 75 compatible = "ti,j784s4-pcie-host"; 76 reg = <0x00 0x02930000 0x00 0x1000>, 77 <0x00 0x02937000 0x00 0x400>, 78 <0x00 0x0e800000 0x00 0x00800000>, 79 <0x44 0x10000000 0x00 0x00001000>; 80 ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>, 81 <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>; 82 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 83 interrupt-names = "link_state"; 84 interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>; 85 device_type = "pci"; 86 max-link-speed = <3>; 87 num-lanes = <2>; 88 power-domains = <&k3_pds 335 TI_SCI_PD_EXCLUSIVE>; 89 clocks = <&k3_clks 335 0>; 90 clock-names = "fck"; 91 #address-cells = <3>; 92 #size-cells = <2>; 93 bus-range = <0x0 0xff>; 94 vendor-id = <0x104c>; 95 device-id = <0xb012>; 96 msi-map = <0x0 &gic_its 0x30000 0x10000>; 97 dma-coherent; 98 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 99 ti,syscon-pcie-ctrl = <&pcie3_ctrl 0x0>; 100 status = "disabled"; 101 }; 102 103 serdes_wiz2: wiz@5020000 { 104 compatible = "ti,j784s4-wiz-10g"; 105 ranges = <0x05020000 0x00 0x05020000 0x10000>; 106 #address-cells = <1>; 107 #size-cells = <1>; 108 power-domains = <&k3_pds 406 TI_SCI_PD_EXCLUSIVE>; 109 clocks = <&k3_clks 406 2>, <&k3_clks 406 6>, <&serdes_refclk>, <&k3_clks 406 5>; 110 clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk"; 111 assigned-clocks = <&k3_clks 406 6>; 112 assigned-clock-parents = <&k3_clks 406 10>; 113 num-lanes = <4>; 114 #reset-cells = <1>; 115 #clock-cells = <1>; 116 status = "disabled"; 117 118 serdes2: serdes@5020000 { 119 compatible = "ti,j721e-serdes-10g"; 120 reg = <0x05020000 0x010000>; 121 reg-names = "torrent_phy"; 122 resets = <&serdes_wiz2 0>; 123 reset-names = "torrent_reset"; 124 clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>, 125 <&serdes_wiz2 TI_WIZ_PHY_EN_REFCLK>; 126 clock-names = "refclk", "phy_en_refclk"; 127 assigned-clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>, 128 <&serdes_wiz2 TI_WIZ_PLL1_REFCLK>, 129 <&serdes_wiz2 TI_WIZ_REFCLK_DIG>; 130 assigned-clock-parents = <&k3_clks 406 6>, 131 <&k3_clks 406 6>, 132 <&k3_clks 406 6>; 133 #address-cells = <1>; 134 #size-cells = <0>; 135 #clock-cells = <1>; 136 status = "disabled"; 137 }; 138 }; 139 140 c71_3: dsp@67800000 { 141 compatible = "ti,j721s2-c71-dsp"; 142 reg = <0x00 0x67800000 0x00 0x00080000>, 143 <0x00 0x67e00000 0x00 0x0000c000>; 144 reg-names = "l2sram", "l1dram"; 145 resets = <&k3_reset 40 1>; 146 firmware-name = "j784s4-c71_3-fw"; 147 ti,sci = <&sms>; 148 ti,sci-dev-id = <40>; 149 ti,sci-proc-ids = <0x33 0xff>; 150 status = "disabled"; 151 }; 152}; 153 154&scm_conf { 155 pcie2_ctrl: pcie2-ctrl@4078 { 156 compatible = "ti,j784s4-pcie-ctrl", "syscon"; 157 reg = <0x4078 0x4>; 158 }; 159 160 pcie3_ctrl: pcie3-ctrl@407c { 161 compatible = "ti,j784s4-pcie-ctrl", "syscon"; 162 reg = <0x407c 0x4>; 163 }; 164}; 165