1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 5#include <dt-bindings/clock/qcom,gcc-msm8974.h> 6#include <dt-bindings/clock/qcom,mmcc-msm8974.h> 7#include <dt-bindings/clock/qcom,rpmcc.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interconnect/qcom,msm8974.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/power/qcom-rpmpd.h> 12#include <dt-bindings/reset/qcom,gcc-msm8974.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 interrupt-parent = <&intc>; 18 19 chosen { }; 20 21 clocks { 22 xo_board: xo_board { 23 compatible = "fixed-clock"; 24 #clock-cells = <0>; 25 clock-frequency = <19200000>; 26 }; 27 28 sleep_clk: sleep_clk { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <32768>; 32 }; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 39 40 cpu0: cpu@0 { 41 compatible = "qcom,krait"; 42 enable-method = "qcom,kpss-acc-v2"; 43 device_type = "cpu"; 44 reg = <0>; 45 next-level-cache = <&l2>; 46 qcom,acc = <&acc0>; 47 qcom,saw = <&saw0>; 48 cpu-idle-states = <&cpu_spc>; 49 }; 50 51 cpu1: cpu@1 { 52 compatible = "qcom,krait"; 53 enable-method = "qcom,kpss-acc-v2"; 54 device_type = "cpu"; 55 reg = <1>; 56 next-level-cache = <&l2>; 57 qcom,acc = <&acc1>; 58 qcom,saw = <&saw1>; 59 cpu-idle-states = <&cpu_spc>; 60 }; 61 62 cpu2: cpu@2 { 63 compatible = "qcom,krait"; 64 enable-method = "qcom,kpss-acc-v2"; 65 device_type = "cpu"; 66 reg = <2>; 67 next-level-cache = <&l2>; 68 qcom,acc = <&acc2>; 69 qcom,saw = <&saw2>; 70 cpu-idle-states = <&cpu_spc>; 71 }; 72 73 cpu3: cpu@3 { 74 compatible = "qcom,krait"; 75 enable-method = "qcom,kpss-acc-v2"; 76 device_type = "cpu"; 77 reg = <3>; 78 next-level-cache = <&l2>; 79 qcom,acc = <&acc3>; 80 qcom,saw = <&saw3>; 81 cpu-idle-states = <&cpu_spc>; 82 }; 83 84 l2: l2-cache { 85 compatible = "cache"; 86 cache-level = <2>; 87 cache-unified; 88 qcom,saw = <&saw_l2>; 89 }; 90 91 idle-states { 92 cpu_spc: cpu-spc { 93 compatible = "qcom,idle-state-spc", 94 "arm,idle-state"; 95 entry-latency-us = <150>; 96 exit-latency-us = <200>; 97 min-residency-us = <2000>; 98 }; 99 }; 100 }; 101 102 firmware { 103 scm { 104 compatible = "qcom,scm-msm8974", "qcom,scm"; 105 clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>; 106 clock-names = "core", "bus", "iface"; 107 }; 108 }; 109 110 memory@0 { 111 device_type = "memory"; 112 reg = <0x0 0x0>; 113 }; 114 115 pmu { 116 compatible = "qcom,krait-pmu"; 117 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 118 }; 119 120 rpm: remoteproc { 121 compatible = "qcom,msm8974-rpm-proc", "qcom,rpm-proc"; 122 123 master-stats { 124 compatible = "qcom,rpm-master-stats"; 125 qcom,rpm-msg-ram = <&apss_master_stats>, 126 <&mpss_master_stats>, 127 <&lpss_master_stats>, 128 <&pronto_master_stats>; 129 qcom,master-names = "APSS", 130 "MPSS", 131 "LPSS", 132 "PRONTO"; 133 }; 134 135 smd-edge { 136 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 137 mboxes = <&apcs 0>; 138 qcom,smd-edge = <15>; 139 140 rpm_requests: rpm-requests { 141 compatible = "qcom,rpm-msm8974", "qcom,smd-rpm"; 142 qcom,smd-channels = "rpm_requests"; 143 144 rpmcc: clock-controller { 145 compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc"; 146 #clock-cells = <1>; 147 clocks = <&xo_board>; 148 clock-names = "xo"; 149 }; 150 151 rpmpd: power-controller { 152 compatible = "qcom,msm8974-rpmpd"; 153 #power-domain-cells = <1>; 154 operating-points-v2 = <&rpmpd_opp_table>; 155 156 rpmpd_opp_table: opp-table { 157 compatible = "operating-points-v2"; 158 159 rpmpd_opp_ret: opp1 { 160 opp-level = <1>; 161 }; 162 163 rpmpd_opp_svs_krait: opp2 { 164 opp-level = <2>; 165 }; 166 167 rpmpd_opp_svs_soc: opp3 { 168 opp-level = <3>; 169 }; 170 171 rpmpd_opp_nom: opp4 { 172 opp-level = <4>; 173 }; 174 175 rpmpd_opp_turbo: opp5 { 176 opp-level = <5>; 177 }; 178 179 rpmpd_opp_super_turbo: opp6 { 180 opp-level = <6>; 181 }; 182 }; 183 }; 184 }; 185 }; 186 }; 187 188 reserved_memory: reserved-memory { 189 #address-cells = <1>; 190 #size-cells = <1>; 191 ranges; 192 193 mpss_region: mpss@8000000 { 194 reg = <0x08000000 0x5100000>; 195 no-map; 196 }; 197 198 mba_region: mba@d100000 { 199 reg = <0x0d100000 0x100000>; 200 no-map; 201 }; 202 203 wcnss_region: wcnss@d200000 { 204 reg = <0x0d200000 0xa00000>; 205 no-map; 206 }; 207 208 adsp_region: adsp@dc00000 { 209 reg = <0x0dc00000 0x1900000>; 210 no-map; 211 }; 212 213 venus_region: memory@f500000 { 214 reg = <0x0f500000 0x500000>; 215 no-map; 216 }; 217 218 smem_region: smem@fa00000 { 219 reg = <0xfa00000 0x200000>; 220 no-map; 221 }; 222 223 tz_region: memory@fc00000 { 224 reg = <0x0fc00000 0x160000>; 225 no-map; 226 }; 227 228 rfsa_mem: memory@fd60000 { 229 reg = <0x0fd60000 0x20000>; 230 no-map; 231 }; 232 233 rmtfs@fd80000 { 234 compatible = "qcom,rmtfs-mem"; 235 reg = <0x0fd80000 0x180000>; 236 no-map; 237 238 qcom,client-id = <1>; 239 }; 240 }; 241 242 smem { 243 compatible = "qcom,smem"; 244 245 memory-region = <&smem_region>; 246 qcom,rpm-msg-ram = <&rpm_msg_ram>; 247 248 hwlocks = <&tcsr_mutex 3>; 249 }; 250 251 smp2p-adsp { 252 compatible = "qcom,smp2p"; 253 qcom,smem = <443>, <429>; 254 255 interrupt-parent = <&intc>; 256 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 257 258 mboxes = <&apcs 10>; 259 260 qcom,local-pid = <0>; 261 qcom,remote-pid = <2>; 262 263 adsp_smp2p_out: master-kernel { 264 qcom,entry-name = "master-kernel"; 265 #qcom,smem-state-cells = <1>; 266 }; 267 268 adsp_smp2p_in: slave-kernel { 269 qcom,entry-name = "slave-kernel"; 270 271 interrupt-controller; 272 #interrupt-cells = <2>; 273 }; 274 }; 275 276 smp2p-modem { 277 compatible = "qcom,smp2p"; 278 qcom,smem = <435>, <428>; 279 280 interrupt-parent = <&intc>; 281 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; 282 283 mboxes = <&apcs 14>; 284 285 qcom,local-pid = <0>; 286 qcom,remote-pid = <1>; 287 288 modem_smp2p_out: master-kernel { 289 qcom,entry-name = "master-kernel"; 290 #qcom,smem-state-cells = <1>; 291 }; 292 293 modem_smp2p_in: slave-kernel { 294 qcom,entry-name = "slave-kernel"; 295 296 interrupt-controller; 297 #interrupt-cells = <2>; 298 }; 299 }; 300 301 smp2p-wcnss { 302 compatible = "qcom,smp2p"; 303 qcom,smem = <451>, <431>; 304 305 interrupt-parent = <&intc>; 306 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; 307 308 mboxes = <&apcs 18>; 309 310 qcom,local-pid = <0>; 311 qcom,remote-pid = <4>; 312 313 wcnss_smp2p_out: master-kernel { 314 qcom,entry-name = "master-kernel"; 315 316 #qcom,smem-state-cells = <1>; 317 }; 318 319 wcnss_smp2p_in: slave-kernel { 320 qcom,entry-name = "slave-kernel"; 321 322 interrupt-controller; 323 #interrupt-cells = <2>; 324 }; 325 }; 326 327 smsm { 328 compatible = "qcom,smsm"; 329 330 #address-cells = <1>; 331 #size-cells = <0>; 332 333 mboxes = <0>, <&apcs 13>, <&apcs 9>, <&apcs 19>; 334 335 apps_smsm: apps@0 { 336 reg = <0>; 337 338 #qcom,smem-state-cells = <1>; 339 }; 340 341 modem_smsm: modem@1 { 342 reg = <1>; 343 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 344 345 interrupt-controller; 346 #interrupt-cells = <2>; 347 }; 348 349 adsp_smsm: adsp@2 { 350 reg = <2>; 351 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; 352 353 interrupt-controller; 354 #interrupt-cells = <2>; 355 }; 356 357 wcnss_smsm: wcnss@7 { 358 reg = <7>; 359 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; 360 361 interrupt-controller; 362 #interrupt-cells = <2>; 363 }; 364 }; 365 366 soc: soc { 367 #address-cells = <1>; 368 #size-cells = <1>; 369 ranges; 370 compatible = "simple-bus"; 371 372 intc: interrupt-controller@f9000000 { 373 compatible = "qcom,msm-qgic2"; 374 interrupt-controller; 375 #interrupt-cells = <3>; 376 reg = <0xf9000000 0x1000>, 377 <0xf9002000 0x1000>; 378 }; 379 380 apcs: mailbox@f9011000 { 381 compatible = "qcom,msm8974-apcs-kpss-global", 382 "qcom,msm8994-apcs-kpss-global", "syscon"; 383 reg = <0xf9011000 0x1000>; 384 #mbox-cells = <1>; 385 }; 386 387 saw_l2: power-manager@f9012000 { 388 compatible = "qcom,msm8974-saw2-v2.1-l2", "qcom,saw2"; 389 reg = <0xf9012000 0x1000>; 390 }; 391 392 watchdog@f9017000 { 393 compatible = "qcom,apss-wdt-msm8974", "qcom,kpss-wdt"; 394 reg = <0xf9017000 0x1000>; 395 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>, 396 <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>; 397 clocks = <&sleep_clk>; 398 }; 399 400 timer@f9020000 { 401 #address-cells = <1>; 402 #size-cells = <1>; 403 ranges; 404 compatible = "arm,armv7-timer-mem"; 405 reg = <0xf9020000 0x1000>; 406 clock-frequency = <19200000>; 407 408 frame@f9021000 { 409 frame-number = <0>; 410 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 411 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 412 reg = <0xf9021000 0x1000>, 413 <0xf9022000 0x1000>; 414 }; 415 416 frame@f9023000 { 417 frame-number = <1>; 418 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 419 reg = <0xf9023000 0x1000>; 420 status = "disabled"; 421 }; 422 423 frame@f9024000 { 424 frame-number = <2>; 425 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 426 reg = <0xf9024000 0x1000>; 427 status = "disabled"; 428 }; 429 430 frame@f9025000 { 431 frame-number = <3>; 432 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 433 reg = <0xf9025000 0x1000>; 434 status = "disabled"; 435 }; 436 437 frame@f9026000 { 438 frame-number = <4>; 439 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 440 reg = <0xf9026000 0x1000>; 441 status = "disabled"; 442 }; 443 444 frame@f9027000 { 445 frame-number = <5>; 446 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 447 reg = <0xf9027000 0x1000>; 448 status = "disabled"; 449 }; 450 451 frame@f9028000 { 452 frame-number = <6>; 453 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 454 reg = <0xf9028000 0x1000>; 455 status = "disabled"; 456 }; 457 }; 458 459 acc0: power-manager@f9088000 { 460 compatible = "qcom,kpss-acc-v2"; 461 reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>; 462 }; 463 464 saw0: power-manager@f9089000 { 465 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; 466 reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; 467 }; 468 469 acc1: power-manager@f9098000 { 470 compatible = "qcom,kpss-acc-v2"; 471 reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>; 472 }; 473 474 saw1: power-manager@f9099000 { 475 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; 476 reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>; 477 }; 478 479 acc2: power-manager@f90a8000 { 480 compatible = "qcom,kpss-acc-v2"; 481 reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>; 482 }; 483 484 saw2: power-manager@f90a9000 { 485 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; 486 reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>; 487 }; 488 489 acc3: power-manager@f90b8000 { 490 compatible = "qcom,kpss-acc-v2"; 491 reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>; 492 }; 493 494 saw3: power-manager@f90b9000 { 495 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; 496 reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>; 497 }; 498 499 sdhc_1: mmc@f9824900 { 500 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; 501 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; 502 reg-names = "hc", "core"; 503 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 505 interrupt-names = "hc_irq", "pwr_irq"; 506 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 507 <&gcc GCC_SDCC1_APPS_CLK>, 508 <&xo_board>; 509 clock-names = "iface", "core", "xo"; 510 bus-width = <8>; 511 non-removable; 512 513 status = "disabled"; 514 }; 515 516 sdhc_3: mmc@f9864900 { 517 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; 518 reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; 519 reg-names = "hc", "core"; 520 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 522 interrupt-names = "hc_irq", "pwr_irq"; 523 clocks = <&gcc GCC_SDCC3_AHB_CLK>, 524 <&gcc GCC_SDCC3_APPS_CLK>, 525 <&xo_board>; 526 clock-names = "iface", "core", "xo"; 527 bus-width = <4>; 528 529 #address-cells = <1>; 530 #size-cells = <0>; 531 532 status = "disabled"; 533 }; 534 535 sdhc_2: mmc@f98a4900 { 536 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; 537 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; 538 reg-names = "hc", "core"; 539 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 540 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 541 interrupt-names = "hc_irq", "pwr_irq"; 542 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 543 <&gcc GCC_SDCC2_APPS_CLK>, 544 <&xo_board>; 545 clock-names = "iface", "core", "xo"; 546 bus-width = <4>; 547 548 #address-cells = <1>; 549 #size-cells = <0>; 550 551 status = "disabled"; 552 }; 553 554 blsp1_uart1: serial@f991d000 { 555 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 556 reg = <0xf991d000 0x1000>; 557 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 558 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 559 clock-names = "core", "iface"; 560 status = "disabled"; 561 }; 562 563 blsp1_uart2: serial@f991e000 { 564 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 565 reg = <0xf991e000 0x1000>; 566 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 567 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 568 clock-names = "core", "iface"; 569 pinctrl-names = "default"; 570 pinctrl-0 = <&blsp1_uart2_default>; 571 status = "disabled"; 572 }; 573 574 blsp1_i2c1: i2c@f9923000 { 575 status = "disabled"; 576 compatible = "qcom,i2c-qup-v2.1.1"; 577 reg = <0xf9923000 0x1000>; 578 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 579 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 580 clock-names = "core", "iface"; 581 pinctrl-names = "default", "sleep"; 582 pinctrl-0 = <&blsp1_i2c1_default>; 583 pinctrl-1 = <&blsp1_i2c1_sleep>; 584 #address-cells = <1>; 585 #size-cells = <0>; 586 }; 587 588 blsp1_i2c2: i2c@f9924000 { 589 status = "disabled"; 590 compatible = "qcom,i2c-qup-v2.1.1"; 591 reg = <0xf9924000 0x1000>; 592 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 593 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 594 clock-names = "core", "iface"; 595 pinctrl-names = "default", "sleep"; 596 pinctrl-0 = <&blsp1_i2c2_default>; 597 pinctrl-1 = <&blsp1_i2c2_sleep>; 598 #address-cells = <1>; 599 #size-cells = <0>; 600 }; 601 602 blsp1_i2c3: i2c@f9925000 { 603 status = "disabled"; 604 compatible = "qcom,i2c-qup-v2.1.1"; 605 reg = <0xf9925000 0x1000>; 606 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 607 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 608 clock-names = "core", "iface"; 609 pinctrl-names = "default", "sleep"; 610 pinctrl-0 = <&blsp1_i2c3_default>; 611 pinctrl-1 = <&blsp1_i2c3_sleep>; 612 #address-cells = <1>; 613 #size-cells = <0>; 614 }; 615 616 blsp1_i2c6: i2c@f9928000 { 617 status = "disabled"; 618 compatible = "qcom,i2c-qup-v2.1.1"; 619 reg = <0xf9928000 0x1000>; 620 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 621 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 622 clock-names = "core", "iface"; 623 pinctrl-names = "default", "sleep"; 624 pinctrl-0 = <&blsp1_i2c6_default>; 625 pinctrl-1 = <&blsp1_i2c6_sleep>; 626 #address-cells = <1>; 627 #size-cells = <0>; 628 }; 629 630 blsp2_dma: dma-controller@f9944000 { 631 compatible = "qcom,bam-v1.4.0"; 632 reg = <0xf9944000 0x19000>; 633 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 634 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 635 clock-names = "bam_clk"; 636 #dma-cells = <1>; 637 qcom,ee = <0>; 638 }; 639 640 blsp2_uart1: serial@f995d000 { 641 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 642 reg = <0xf995d000 0x1000>; 643 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 644 clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 645 clock-names = "core", "iface"; 646 pinctrl-names = "default", "sleep"; 647 pinctrl-0 = <&blsp2_uart1_default>; 648 pinctrl-1 = <&blsp2_uart1_sleep>; 649 status = "disabled"; 650 }; 651 652 blsp2_uart2: serial@f995e000 { 653 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 654 reg = <0xf995e000 0x1000>; 655 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 656 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 657 clock-names = "core", "iface"; 658 status = "disabled"; 659 }; 660 661 blsp2_uart4: serial@f9960000 { 662 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 663 reg = <0xf9960000 0x1000>; 664 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 665 clocks = <&gcc GCC_BLSP2_UART4_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 666 clock-names = "core", "iface"; 667 pinctrl-names = "default"; 668 pinctrl-0 = <&blsp2_uart4_default>; 669 status = "disabled"; 670 }; 671 672 blsp2_i2c2: i2c@f9964000 { 673 status = "disabled"; 674 compatible = "qcom,i2c-qup-v2.1.1"; 675 reg = <0xf9964000 0x1000>; 676 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 677 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 678 clock-names = "core", "iface"; 679 pinctrl-names = "default", "sleep"; 680 pinctrl-0 = <&blsp2_i2c2_default>; 681 pinctrl-1 = <&blsp2_i2c2_sleep>; 682 #address-cells = <1>; 683 #size-cells = <0>; 684 }; 685 686 blsp2_i2c5: i2c@f9967000 { 687 status = "disabled"; 688 compatible = "qcom,i2c-qup-v2.1.1"; 689 reg = <0xf9967000 0x1000>; 690 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 691 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 692 clock-names = "core", "iface"; 693 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; 694 dma-names = "tx", "rx"; 695 pinctrl-names = "default", "sleep"; 696 pinctrl-0 = <&blsp2_i2c5_default>; 697 pinctrl-1 = <&blsp2_i2c5_sleep>; 698 #address-cells = <1>; 699 #size-cells = <0>; 700 }; 701 702 blsp2_i2c6: i2c@f9968000 { 703 status = "disabled"; 704 compatible = "qcom,i2c-qup-v2.1.1"; 705 reg = <0xf9968000 0x1000>; 706 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 707 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 708 clock-names = "core", "iface"; 709 pinctrl-names = "default", "sleep"; 710 pinctrl-0 = <&blsp2_i2c6_default>; 711 pinctrl-1 = <&blsp2_i2c6_sleep>; 712 #address-cells = <1>; 713 #size-cells = <0>; 714 }; 715 716 usb: usb@f9a55000 { 717 compatible = "qcom,ci-hdrc"; 718 reg = <0xf9a55000 0x200>, 719 <0xf9a55200 0x200>; 720 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 721 clocks = <&gcc GCC_USB_HS_AHB_CLK>, 722 <&gcc GCC_USB_HS_SYSTEM_CLK>; 723 clock-names = "iface", "core"; 724 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; 725 assigned-clock-rates = <75000000>; 726 resets = <&gcc GCC_USB_HS_BCR>; 727 reset-names = "core"; 728 phy_type = "ulpi"; 729 dr_mode = "otg"; 730 ahb-burst-config = <0>; 731 phy-names = "usb-phy"; 732 status = "disabled"; 733 #reset-cells = <1>; 734 735 ulpi { 736 usb_hs1_phy: phy-0 { 737 compatible = "qcom,usb-hs-phy-msm8974", 738 "qcom,usb-hs-phy"; 739 #phy-cells = <0>; 740 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 741 clock-names = "ref", "sleep"; 742 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>; 743 reset-names = "phy", "por"; 744 status = "disabled"; 745 }; 746 747 usb_hs2_phy: phy-1 { 748 compatible = "qcom,usb-hs-phy-msm8974", 749 "qcom,usb-hs-phy"; 750 #phy-cells = <0>; 751 clocks = <&xo_board>, <&gcc GCC_USB2B_PHY_SLEEP_CLK>; 752 clock-names = "ref", "sleep"; 753 resets = <&gcc GCC_USB2B_PHY_BCR>, <&usb 1>; 754 reset-names = "phy", "por"; 755 status = "disabled"; 756 }; 757 }; 758 }; 759 760 rng@f9bff000 { 761 compatible = "qcom,prng"; 762 reg = <0xf9bff000 0x200>; 763 clocks = <&gcc GCC_PRNG_AHB_CLK>; 764 clock-names = "core"; 765 }; 766 767 pronto: remoteproc@fb204000 { 768 compatible = "qcom,pronto-v2-pil", "qcom,pronto"; 769 reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>; 770 reg-names = "ccu", "dxe", "pmu"; 771 772 memory-region = <&wcnss_region>; 773 774 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, 775 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 776 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 777 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 778 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 779 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 780 781 power-domains = <&rpmpd MSM8974_VDDCX>; 782 power-domain-names = "cx"; 783 784 qcom,smem-states = <&wcnss_smp2p_out 0>; 785 qcom,smem-state-names = "stop"; 786 787 status = "disabled"; 788 789 iris { 790 compatible = "qcom,wcn3680"; 791 792 clocks = <&rpmcc RPM_SMD_CXO_A2>; 793 clock-names = "xo"; 794 }; 795 796 smd-edge { 797 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>; 798 799 mboxes = <&apcs 17>; 800 qcom,smd-edge = <6>; 801 802 wcnss { 803 compatible = "qcom,wcnss"; 804 qcom,smd-channels = "WCNSS_CTRL"; 805 status = "disabled"; 806 807 qcom,mmio = <&pronto>; 808 809 bluetooth { 810 compatible = "qcom,wcnss-bt"; 811 }; 812 813 wifi { 814 compatible = "qcom,wcnss-wlan"; 815 816 interrupts = <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>, 817 <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>; 818 interrupt-names = "tx", "rx"; 819 820 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; 821 qcom,smem-state-names = "tx-enable", 822 "tx-rings-empty"; 823 }; 824 }; 825 }; 826 }; 827 828 sram@fc190000 { 829 compatible = "qcom,msm8974-rpm-stats"; 830 reg = <0xfc190000 0x10000>; 831 }; 832 833 etf@fc307000 { 834 compatible = "arm,coresight-tmc", "arm,primecell"; 835 reg = <0xfc307000 0x1000>; 836 837 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 838 clock-names = "apb_pclk", "atclk"; 839 840 out-ports { 841 port { 842 etf_out: endpoint { 843 remote-endpoint = <&replicator_in>; 844 }; 845 }; 846 }; 847 848 in-ports { 849 port { 850 etf_in: endpoint { 851 remote-endpoint = <&merger_out>; 852 }; 853 }; 854 }; 855 }; 856 857 tpiu@fc318000 { 858 compatible = "arm,coresight-tpiu", "arm,primecell"; 859 reg = <0xfc318000 0x1000>; 860 861 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 862 clock-names = "apb_pclk", "atclk"; 863 864 in-ports { 865 port { 866 tpiu_in: endpoint { 867 remote-endpoint = <&replicator_out1>; 868 }; 869 }; 870 }; 871 }; 872 873 funnel@fc31a000 { 874 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 875 reg = <0xfc31a000 0x1000>; 876 877 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 878 clock-names = "apb_pclk", "atclk"; 879 880 in-ports { 881 #address-cells = <1>; 882 #size-cells = <0>; 883 884 /* 885 * Not described input ports: 886 * 0 - not-connected 887 * 1 - connected trought funnel to Multimedia CPU 888 * 2 - connected to Wireless CPU 889 * 3 - not-connected 890 * 4 - not-connected 891 * 6 - not-connected 892 * 7 - connected to STM 893 */ 894 port@5 { 895 reg = <5>; 896 funnel1_in5: endpoint { 897 remote-endpoint = <&kpss_out>; 898 }; 899 }; 900 }; 901 902 out-ports { 903 port { 904 funnel1_out: endpoint { 905 remote-endpoint = <&merger_in1>; 906 }; 907 }; 908 }; 909 }; 910 911 funnel@fc31b000 { 912 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 913 reg = <0xfc31b000 0x1000>; 914 915 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 916 clock-names = "apb_pclk", "atclk"; 917 918 in-ports { 919 #address-cells = <1>; 920 #size-cells = <0>; 921 922 /* 923 * Not described input ports: 924 * 0 - connected trought funnel to Audio, Modem and 925 * Resource and Power Manager CPU's 926 * 2...7 - not-connected 927 */ 928 port@1 { 929 reg = <1>; 930 merger_in1: endpoint { 931 remote-endpoint = <&funnel1_out>; 932 }; 933 }; 934 }; 935 936 out-ports { 937 port { 938 merger_out: endpoint { 939 remote-endpoint = <&etf_in>; 940 }; 941 }; 942 }; 943 }; 944 945 replicator@fc31c000 { 946 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 947 reg = <0xfc31c000 0x1000>; 948 949 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 950 clock-names = "apb_pclk", "atclk"; 951 952 out-ports { 953 #address-cells = <1>; 954 #size-cells = <0>; 955 956 port@0 { 957 reg = <0>; 958 replicator_out0: endpoint { 959 remote-endpoint = <&etr_in>; 960 }; 961 }; 962 port@1 { 963 reg = <1>; 964 replicator_out1: endpoint { 965 remote-endpoint = <&tpiu_in>; 966 }; 967 }; 968 }; 969 970 in-ports { 971 port { 972 replicator_in: endpoint { 973 remote-endpoint = <&etf_out>; 974 }; 975 }; 976 }; 977 }; 978 979 etr@fc322000 { 980 compatible = "arm,coresight-tmc", "arm,primecell"; 981 reg = <0xfc322000 0x1000>; 982 983 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 984 clock-names = "apb_pclk", "atclk"; 985 986 in-ports { 987 port { 988 etr_in: endpoint { 989 remote-endpoint = <&replicator_out0>; 990 }; 991 }; 992 }; 993 }; 994 995 etm@fc33c000 { 996 compatible = "arm,coresight-etm4x", "arm,primecell"; 997 reg = <0xfc33c000 0x1000>; 998 999 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1000 clock-names = "apb_pclk", "atclk"; 1001 1002 cpu = <&cpu0>; 1003 1004 out-ports { 1005 port { 1006 etm0_out: endpoint { 1007 remote-endpoint = <&kpss_in0>; 1008 }; 1009 }; 1010 }; 1011 }; 1012 1013 etm@fc33d000 { 1014 compatible = "arm,coresight-etm4x", "arm,primecell"; 1015 reg = <0xfc33d000 0x1000>; 1016 1017 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1018 clock-names = "apb_pclk", "atclk"; 1019 1020 cpu = <&cpu1>; 1021 1022 out-ports { 1023 port { 1024 etm1_out: endpoint { 1025 remote-endpoint = <&kpss_in1>; 1026 }; 1027 }; 1028 }; 1029 }; 1030 1031 etm@fc33e000 { 1032 compatible = "arm,coresight-etm4x", "arm,primecell"; 1033 reg = <0xfc33e000 0x1000>; 1034 1035 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1036 clock-names = "apb_pclk", "atclk"; 1037 1038 cpu = <&cpu2>; 1039 1040 out-ports { 1041 port { 1042 etm2_out: endpoint { 1043 remote-endpoint = <&kpss_in2>; 1044 }; 1045 }; 1046 }; 1047 }; 1048 1049 etm@fc33f000 { 1050 compatible = "arm,coresight-etm4x", "arm,primecell"; 1051 reg = <0xfc33f000 0x1000>; 1052 1053 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1054 clock-names = "apb_pclk", "atclk"; 1055 1056 cpu = <&cpu3>; 1057 1058 out-ports { 1059 port { 1060 etm3_out: endpoint { 1061 remote-endpoint = <&kpss_in3>; 1062 }; 1063 }; 1064 }; 1065 }; 1066 1067 /* KPSS funnel, only 4 inputs are used */ 1068 funnel@fc345000 { 1069 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1070 reg = <0xfc345000 0x1000>; 1071 1072 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1073 clock-names = "apb_pclk", "atclk"; 1074 1075 in-ports { 1076 #address-cells = <1>; 1077 #size-cells = <0>; 1078 1079 port@0 { 1080 reg = <0>; 1081 kpss_in0: endpoint { 1082 remote-endpoint = <&etm0_out>; 1083 }; 1084 }; 1085 port@1 { 1086 reg = <1>; 1087 kpss_in1: endpoint { 1088 remote-endpoint = <&etm1_out>; 1089 }; 1090 }; 1091 port@2 { 1092 reg = <2>; 1093 kpss_in2: endpoint { 1094 remote-endpoint = <&etm2_out>; 1095 }; 1096 }; 1097 port@3 { 1098 reg = <3>; 1099 kpss_in3: endpoint { 1100 remote-endpoint = <&etm3_out>; 1101 }; 1102 }; 1103 }; 1104 1105 out-ports { 1106 port { 1107 kpss_out: endpoint { 1108 remote-endpoint = <&funnel1_in5>; 1109 }; 1110 }; 1111 }; 1112 }; 1113 1114 bimc: interconnect@fc380000 { 1115 reg = <0xfc380000 0x6a000>; 1116 compatible = "qcom,msm8974-bimc"; 1117 #interconnect-cells = <1>; 1118 clock-names = "bus", "bus_a"; 1119 clocks = <&rpmcc RPM_SMD_BIMC_CLK>, 1120 <&rpmcc RPM_SMD_BIMC_A_CLK>; 1121 }; 1122 1123 gcc: clock-controller@fc400000 { 1124 compatible = "qcom,gcc-msm8974"; 1125 #clock-cells = <1>; 1126 #reset-cells = <1>; 1127 #power-domain-cells = <1>; 1128 reg = <0xfc400000 0x4000>; 1129 1130 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1131 <&sleep_clk>; 1132 clock-names = "xo", 1133 "sleep_clk"; 1134 }; 1135 1136 rpm_msg_ram: sram@fc428000 { 1137 compatible = "qcom,rpm-msg-ram"; 1138 reg = <0xfc428000 0x4000>; 1139 1140 #address-cells = <1>; 1141 #size-cells = <1>; 1142 ranges = <0 0xfc428000 0x4000>; 1143 1144 apss_master_stats: sram@150 { 1145 reg = <0x150 0x14>; 1146 }; 1147 1148 mpss_master_stats: sram@b50 { 1149 reg = <0xb50 0x14>; 1150 }; 1151 1152 lpss_master_stats: sram@1550 { 1153 reg = <0x1550 0x14>; 1154 }; 1155 1156 pronto_master_stats: sram@1f50 { 1157 reg = <0x1f50 0x14>; 1158 }; 1159 }; 1160 1161 snoc: interconnect@fc460000 { 1162 reg = <0xfc460000 0x4000>; 1163 compatible = "qcom,msm8974-snoc"; 1164 #interconnect-cells = <1>; 1165 clock-names = "bus", "bus_a"; 1166 clocks = <&rpmcc RPM_SMD_SNOC_CLK>, 1167 <&rpmcc RPM_SMD_SNOC_A_CLK>; 1168 }; 1169 1170 pnoc: interconnect@fc468000 { 1171 reg = <0xfc468000 0x4000>; 1172 compatible = "qcom,msm8974-pnoc"; 1173 #interconnect-cells = <1>; 1174 clock-names = "bus", "bus_a"; 1175 clocks = <&rpmcc RPM_SMD_PNOC_CLK>, 1176 <&rpmcc RPM_SMD_PNOC_A_CLK>; 1177 }; 1178 1179 ocmemnoc: interconnect@fc470000 { 1180 reg = <0xfc470000 0x4000>; 1181 compatible = "qcom,msm8974-ocmemnoc"; 1182 #interconnect-cells = <1>; 1183 clock-names = "bus", "bus_a"; 1184 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, 1185 <&rpmcc RPM_SMD_OCMEMGX_A_CLK>; 1186 }; 1187 1188 mmssnoc: interconnect@fc478000 { 1189 reg = <0xfc478000 0x4000>; 1190 compatible = "qcom,msm8974-mmssnoc"; 1191 #interconnect-cells = <1>; 1192 clock-names = "bus", "bus_a"; 1193 clocks = <&mmcc MMSS_S0_AXI_CLK>, 1194 <&mmcc MMSS_S0_AXI_CLK>; 1195 }; 1196 1197 cnoc: interconnect@fc480000 { 1198 reg = <0xfc480000 0x4000>; 1199 compatible = "qcom,msm8974-cnoc"; 1200 #interconnect-cells = <1>; 1201 clock-names = "bus", "bus_a"; 1202 clocks = <&rpmcc RPM_SMD_CNOC_CLK>, 1203 <&rpmcc RPM_SMD_CNOC_A_CLK>; 1204 }; 1205 1206 tsens: thermal-sensor@fc4a9000 { 1207 compatible = "qcom,msm8974-tsens", "qcom,tsens-v0_1"; 1208 reg = <0xfc4a9000 0x1000>, /* TM */ 1209 <0xfc4a8000 0x1000>; /* SROT */ 1210 nvmem-cells = <&tsens_mode>, 1211 <&tsens_base1>, <&tsens_base2>, 1212 <&tsens_use_backup>, 1213 <&tsens_mode_backup>, 1214 <&tsens_base1_backup>, <&tsens_base2_backup>, 1215 <&tsens_s0_p1>, <&tsens_s0_p2>, 1216 <&tsens_s1_p1>, <&tsens_s1_p2>, 1217 <&tsens_s2_p1>, <&tsens_s2_p2>, 1218 <&tsens_s3_p1>, <&tsens_s3_p2>, 1219 <&tsens_s4_p1>, <&tsens_s4_p2>, 1220 <&tsens_s5_p1>, <&tsens_s5_p2>, 1221 <&tsens_s6_p1>, <&tsens_s6_p2>, 1222 <&tsens_s7_p1>, <&tsens_s7_p2>, 1223 <&tsens_s8_p1>, <&tsens_s8_p2>, 1224 <&tsens_s9_p1>, <&tsens_s9_p2>, 1225 <&tsens_s10_p1>, <&tsens_s10_p2>, 1226 <&tsens_s0_p1_backup>, <&tsens_s0_p2_backup>, 1227 <&tsens_s1_p1_backup>, <&tsens_s1_p2_backup>, 1228 <&tsens_s2_p1_backup>, <&tsens_s2_p2_backup>, 1229 <&tsens_s3_p1_backup>, <&tsens_s3_p2_backup>, 1230 <&tsens_s4_p1_backup>, <&tsens_s4_p2_backup>, 1231 <&tsens_s5_p1_backup>, <&tsens_s5_p2_backup>, 1232 <&tsens_s6_p1_backup>, <&tsens_s6_p2_backup>, 1233 <&tsens_s7_p1_backup>, <&tsens_s7_p2_backup>, 1234 <&tsens_s8_p1_backup>, <&tsens_s8_p2_backup>, 1235 <&tsens_s9_p1_backup>, <&tsens_s9_p2_backup>, 1236 <&tsens_s10_p1_backup>, <&tsens_s10_p2_backup>; 1237 nvmem-cell-names = "mode", 1238 "base1", "base2", 1239 "use_backup", 1240 "mode_backup", 1241 "base1_backup", "base2_backup", 1242 "s0_p1", "s0_p2", 1243 "s1_p1", "s1_p2", 1244 "s2_p1", "s2_p2", 1245 "s3_p1", "s3_p2", 1246 "s4_p1", "s4_p2", 1247 "s5_p1", "s5_p2", 1248 "s6_p1", "s6_p2", 1249 "s7_p1", "s7_p2", 1250 "s8_p1", "s8_p2", 1251 "s9_p1", "s9_p2", 1252 "s10_p1", "s10_p2", 1253 "s0_p1_backup", "s0_p2_backup", 1254 "s1_p1_backup", "s1_p2_backup", 1255 "s2_p1_backup", "s2_p2_backup", 1256 "s3_p1_backup", "s3_p2_backup", 1257 "s4_p1_backup", "s4_p2_backup", 1258 "s5_p1_backup", "s5_p2_backup", 1259 "s6_p1_backup", "s6_p2_backup", 1260 "s7_p1_backup", "s7_p2_backup", 1261 "s8_p1_backup", "s8_p2_backup", 1262 "s9_p1_backup", "s9_p2_backup", 1263 "s10_p1_backup", "s10_p2_backup"; 1264 #qcom,sensors = <11>; 1265 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 1266 interrupt-names = "uplow"; 1267 #thermal-sensor-cells = <1>; 1268 }; 1269 1270 restart@fc4ab000 { 1271 compatible = "qcom,pshold"; 1272 reg = <0xfc4ab000 0x4>; 1273 }; 1274 1275 qfprom: efuse@fc4bc000 { 1276 compatible = "qcom,msm8974-qfprom", "qcom,qfprom"; 1277 reg = <0xfc4bc000 0x2100>; 1278 #address-cells = <1>; 1279 #size-cells = <1>; 1280 1281 tsens_base1: base1@d0 { 1282 reg = <0xd0 0x1>; 1283 bits = <0 8>; 1284 }; 1285 1286 tsens_s0_p1: s0-p1@d1 { 1287 reg = <0xd1 0x1>; 1288 bits = <0 6>; 1289 }; 1290 1291 tsens_s1_p1: s1-p1@d2 { 1292 reg = <0xd1 0x2>; 1293 bits = <6 6>; 1294 }; 1295 1296 tsens_s2_p1: s2-p1@d2 { 1297 reg = <0xd2 0x2>; 1298 bits = <4 6>; 1299 }; 1300 1301 tsens_s3_p1: s3-p1@d3 { 1302 reg = <0xd3 0x1>; 1303 bits = <2 6>; 1304 }; 1305 1306 tsens_s4_p1: s4-p1@d4 { 1307 reg = <0xd4 0x1>; 1308 bits = <0 6>; 1309 }; 1310 1311 tsens_s5_p1: s5-p1@d4 { 1312 reg = <0xd4 0x2>; 1313 bits = <6 6>; 1314 }; 1315 1316 tsens_s6_p1: s6-p1@d5 { 1317 reg = <0xd5 0x2>; 1318 bits = <4 6>; 1319 }; 1320 1321 tsens_s7_p1: s7-p1@d6 { 1322 reg = <0xd6 0x1>; 1323 bits = <2 6>; 1324 }; 1325 1326 tsens_s8_p1: s8-p1@d7 { 1327 reg = <0xd7 0x1>; 1328 bits = <0 6>; 1329 }; 1330 1331 tsens_mode: mode@d7 { 1332 reg = <0xd7 0x1>; 1333 bits = <6 2>; 1334 }; 1335 1336 tsens_s9_p1: s9-p1@d8 { 1337 reg = <0xd8 0x1>; 1338 bits = <0 6>; 1339 }; 1340 1341 tsens_s10_p1: s10-p1@d8 { 1342 reg = <0xd8 0x2>; 1343 bits = <6 6>; 1344 }; 1345 1346 tsens_base2: base2@d9 { 1347 reg = <0xd9 0x2>; 1348 bits = <4 8>; 1349 }; 1350 1351 tsens_s0_p2: s0-p2@da { 1352 reg = <0xda 0x2>; 1353 bits = <4 6>; 1354 }; 1355 1356 tsens_s1_p2: s1-p2@db { 1357 reg = <0xdb 0x1>; 1358 bits = <2 6>; 1359 }; 1360 1361 tsens_s2_p2: s2-p2@dc { 1362 reg = <0xdc 0x1>; 1363 bits = <0 6>; 1364 }; 1365 1366 tsens_s3_p2: s3-p2@dc { 1367 reg = <0xdc 0x2>; 1368 bits = <6 6>; 1369 }; 1370 1371 tsens_s4_p2: s4-p2@dd { 1372 reg = <0xdd 0x2>; 1373 bits = <4 6>; 1374 }; 1375 1376 tsens_s5_p2: s5-p2@de { 1377 reg = <0xde 0x2>; 1378 bits = <2 6>; 1379 }; 1380 1381 tsens_s6_p2: s6-p2@df { 1382 reg = <0xdf 0x1>; 1383 bits = <0 6>; 1384 }; 1385 1386 tsens_s7_p2: s7-p2@e0 { 1387 reg = <0xe0 0x1>; 1388 bits = <0 6>; 1389 }; 1390 1391 tsens_s8_p2: s8-p2@e0 { 1392 reg = <0xe0 0x2>; 1393 bits = <6 6>; 1394 }; 1395 1396 tsens_s9_p2: s9-p2@e1 { 1397 reg = <0xe1 0x2>; 1398 bits = <4 6>; 1399 }; 1400 1401 tsens_s10_p2: s10-p2@e2 { 1402 reg = <0xe2 0x2>; 1403 bits = <2 6>; 1404 }; 1405 1406 tsens_s5_p2_backup: s5-p2-backup@e3 { 1407 reg = <0xe3 0x2>; 1408 bits = <0 6>; 1409 }; 1410 1411 tsens_mode_backup: mode-backup@e3 { 1412 reg = <0xe3 0x1>; 1413 bits = <6 2>; 1414 }; 1415 1416 tsens_s6_p2_backup: s6-p2-backup@e4 { 1417 reg = <0xe4 0x1>; 1418 bits = <0 6>; 1419 }; 1420 1421 tsens_s7_p2_backup: s7-p2-backup@e4 { 1422 reg = <0xe4 0x2>; 1423 bits = <6 6>; 1424 }; 1425 1426 tsens_s8_p2_backup: s8-p2-backup@e5 { 1427 reg = <0xe5 0x2>; 1428 bits = <4 6>; 1429 }; 1430 1431 tsens_s9_p2_backup: s9-p2-backup@e6 { 1432 reg = <0xe6 0x2>; 1433 bits = <2 6>; 1434 }; 1435 1436 tsens_s10_p2_backup: s10-p2-backup@e7 { 1437 reg = <0xe7 0x1>; 1438 bits = <0 6>; 1439 }; 1440 1441 tsens_base1_backup: base1-backup@440 { 1442 reg = <0x440 0x1>; 1443 bits = <0 8>; 1444 }; 1445 1446 tsens_s0_p1_backup: s0-p1-backup@441 { 1447 reg = <0x441 0x1>; 1448 bits = <0 6>; 1449 }; 1450 1451 tsens_s1_p1_backup: s1-p1-backup@442 { 1452 reg = <0x441 0x2>; 1453 bits = <6 6>; 1454 }; 1455 1456 tsens_s2_p1_backup: s2-p1-backup@442 { 1457 reg = <0x442 0x2>; 1458 bits = <4 6>; 1459 }; 1460 1461 tsens_s3_p1_backup: s3-p1-backup@443 { 1462 reg = <0x443 0x1>; 1463 bits = <2 6>; 1464 }; 1465 1466 tsens_s4_p1_backup: s4-p1-backup@444 { 1467 reg = <0x444 0x1>; 1468 bits = <0 6>; 1469 }; 1470 1471 tsens_s5_p1_backup: s5-p1-backup@444 { 1472 reg = <0x444 0x2>; 1473 bits = <6 6>; 1474 }; 1475 1476 tsens_s6_p1_backup: s6-p1-backup@445 { 1477 reg = <0x445 0x2>; 1478 bits = <4 6>; 1479 }; 1480 1481 tsens_s7_p1_backup: s7-p1-backup@446 { 1482 reg = <0x446 0x1>; 1483 bits = <2 6>; 1484 }; 1485 1486 tsens_use_backup: use-backup@447 { 1487 reg = <0x447 0x1>; 1488 bits = <5 3>; 1489 }; 1490 1491 tsens_s8_p1_backup: s8-p1-backup@448 { 1492 reg = <0x448 0x1>; 1493 bits = <0 6>; 1494 }; 1495 1496 tsens_s9_p1_backup: s9-p1-backup@448 { 1497 reg = <0x448 0x2>; 1498 bits = <6 6>; 1499 }; 1500 1501 tsens_s10_p1_backup: s10-p1-backup@449 { 1502 reg = <0x449 0x2>; 1503 bits = <4 6>; 1504 }; 1505 1506 tsens_base2_backup: base2-backup@44a { 1507 reg = <0x44a 0x2>; 1508 bits = <2 8>; 1509 }; 1510 1511 tsens_s0_p2_backup: s0-p2-backup@44b { 1512 reg = <0x44b 0x3>; 1513 bits = <2 6>; 1514 }; 1515 1516 tsens_s1_p2_backup: s1-p2-backup@44c { 1517 reg = <0x44c 0x1>; 1518 bits = <0 6>; 1519 }; 1520 1521 tsens_s2_p2_backup: s2-p2-backup@44c { 1522 reg = <0x44c 0x2>; 1523 bits = <6 6>; 1524 }; 1525 1526 tsens_s3_p2_backup: s3-p2-backup@44d { 1527 reg = <0x44d 0x2>; 1528 bits = <4 6>; 1529 }; 1530 1531 tsens_s4_p2_backup: s4-p2-backup@44e { 1532 reg = <0x44e 0x1>; 1533 bits = <2 6>; 1534 }; 1535 }; 1536 1537 spmi_bus: spmi@fc4cf000 { 1538 compatible = "qcom,spmi-pmic-arb"; 1539 reg-names = "core", "intr", "cnfg"; 1540 reg = <0xfc4cf000 0x1000>, 1541 <0xfc4cb000 0x1000>, 1542 <0xfc4ca000 0x1000>; 1543 interrupt-names = "periph_irq"; 1544 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1545 qcom,ee = <0>; 1546 qcom,channel = <0>; 1547 #address-cells = <2>; 1548 #size-cells = <0>; 1549 interrupt-controller; 1550 #interrupt-cells = <4>; 1551 }; 1552 1553 bam_dmux_dma: dma-controller@fc834000 { 1554 compatible = "qcom,bam-v1.4.0"; 1555 reg = <0xfc834000 0x7000>; 1556 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1557 #dma-cells = <1>; 1558 qcom,ee = <0>; 1559 1560 num-channels = <6>; 1561 qcom,num-ees = <1>; 1562 qcom,powered-remotely; 1563 }; 1564 1565 remoteproc_mss: remoteproc@fc880000 { 1566 compatible = "qcom,msm8974-mss-pil"; 1567 reg = <0xfc880000 0x100>, <0xfc820000 0x020>; 1568 reg-names = "qdsp6", "rmb"; 1569 1570 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, 1571 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1572 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1573 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1574 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1575 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 1576 1577 clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, 1578 <&gcc GCC_MSS_CFG_AHB_CLK>, 1579 <&gcc GCC_BOOT_ROM_AHB_CLK>, 1580 <&xo_board>; 1581 clock-names = "iface", "bus", "mem", "xo"; 1582 1583 resets = <&gcc GCC_MSS_RESTART>; 1584 reset-names = "mss_restart"; 1585 1586 power-domains = <&rpmpd MSM8974_VDDCX>; 1587 power-domain-names = "cx"; 1588 1589 qcom,halt-regs = <&tcsr_mutex 0x1180 0x1200 0x1280>; 1590 1591 qcom,smem-states = <&modem_smp2p_out 0>; 1592 qcom,smem-state-names = "stop"; 1593 1594 status = "disabled"; 1595 1596 mba { 1597 memory-region = <&mba_region>; 1598 }; 1599 1600 mpss { 1601 memory-region = <&mpss_region>; 1602 }; 1603 1604 bam_dmux: bam-dmux { 1605 compatible = "qcom,bam-dmux"; 1606 1607 interrupt-parent = <&modem_smsm>; 1608 interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>; 1609 interrupt-names = "pc", "pc-ack"; 1610 1611 qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>; 1612 qcom,smem-state-names = "pc", "pc-ack"; 1613 1614 dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>; 1615 dma-names = "tx", "rx"; 1616 }; 1617 1618 smd-edge { 1619 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; 1620 1621 mboxes = <&apcs 12>; 1622 qcom,smd-edge = <0>; 1623 1624 label = "modem"; 1625 }; 1626 }; 1627 1628 tcsr_mutex: hwlock@fd484000 { 1629 compatible = "qcom,msm8974-tcsr-mutex", "qcom,tcsr-mutex", "syscon"; 1630 reg = <0xfd484000 0x2000>; 1631 #hwlock-cells = <1>; 1632 }; 1633 1634 tcsr: syscon@fd4a0000 { 1635 compatible = "qcom,tcsr-msm8974", "syscon"; 1636 reg = <0xfd4a0000 0x10000>; 1637 }; 1638 1639 tlmm: pinctrl@fd510000 { 1640 compatible = "qcom,msm8974-pinctrl"; 1641 reg = <0xfd510000 0x4000>; 1642 gpio-controller; 1643 gpio-ranges = <&tlmm 0 0 146>; 1644 #gpio-cells = <2>; 1645 interrupt-controller; 1646 #interrupt-cells = <2>; 1647 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1648 1649 sdc1_off: sdc1-off-state { 1650 clk-pins { 1651 pins = "sdc1_clk"; 1652 bias-disable; 1653 drive-strength = <2>; 1654 }; 1655 1656 cmd-pins { 1657 pins = "sdc1_cmd"; 1658 bias-pull-up; 1659 drive-strength = <2>; 1660 }; 1661 1662 data-pins { 1663 pins = "sdc1_data"; 1664 bias-pull-up; 1665 drive-strength = <2>; 1666 }; 1667 }; 1668 1669 sdc2_off: sdc2-off-state { 1670 clk-pins { 1671 pins = "sdc2_clk"; 1672 bias-disable; 1673 drive-strength = <2>; 1674 }; 1675 1676 cmd-pins { 1677 pins = "sdc2_cmd"; 1678 bias-pull-up; 1679 drive-strength = <2>; 1680 }; 1681 1682 data-pins { 1683 pins = "sdc2_data"; 1684 bias-pull-up; 1685 drive-strength = <2>; 1686 }; 1687 }; 1688 1689 blsp1_uart2_default: blsp1-uart2-default-state { 1690 rx-pins { 1691 pins = "gpio5"; 1692 function = "blsp_uart2"; 1693 drive-strength = <2>; 1694 bias-pull-up; 1695 }; 1696 1697 tx-pins { 1698 pins = "gpio4"; 1699 function = "blsp_uart2"; 1700 drive-strength = <4>; 1701 bias-disable; 1702 }; 1703 }; 1704 1705 blsp2_uart1_default: blsp2-uart1-default-state { 1706 tx-rts-pins { 1707 pins = "gpio41", "gpio44"; 1708 function = "blsp_uart7"; 1709 drive-strength = <2>; 1710 bias-disable; 1711 }; 1712 1713 rx-cts-pins { 1714 pins = "gpio42", "gpio43"; 1715 function = "blsp_uart7"; 1716 drive-strength = <2>; 1717 bias-pull-up; 1718 }; 1719 }; 1720 1721 blsp2_uart1_sleep: blsp2-uart1-sleep-state { 1722 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 1723 function = "gpio"; 1724 drive-strength = <2>; 1725 bias-pull-down; 1726 }; 1727 1728 blsp2_uart4_default: blsp2-uart4-default-state { 1729 tx-rts-pins { 1730 pins = "gpio53", "gpio56"; 1731 function = "blsp_uart10"; 1732 drive-strength = <2>; 1733 bias-disable; 1734 }; 1735 1736 rx-cts-pins { 1737 pins = "gpio54", "gpio55"; 1738 function = "blsp_uart10"; 1739 drive-strength = <2>; 1740 bias-pull-up; 1741 }; 1742 }; 1743 1744 blsp1_i2c1_default: blsp1-i2c1-default-state { 1745 pins = "gpio2", "gpio3"; 1746 function = "blsp_i2c1"; 1747 drive-strength = <2>; 1748 bias-disable; 1749 }; 1750 1751 blsp1_i2c1_sleep: blsp1-i2c1-sleep-state { 1752 pins = "gpio2", "gpio3"; 1753 function = "blsp_i2c1"; 1754 drive-strength = <2>; 1755 bias-pull-up; 1756 }; 1757 1758 blsp1_i2c2_default: blsp1-i2c2-default-state { 1759 pins = "gpio6", "gpio7"; 1760 function = "blsp_i2c2"; 1761 drive-strength = <2>; 1762 bias-disable; 1763 }; 1764 1765 blsp1_i2c2_sleep: blsp1-i2c2-sleep-state { 1766 pins = "gpio6", "gpio7"; 1767 function = "blsp_i2c2"; 1768 drive-strength = <2>; 1769 bias-pull-up; 1770 }; 1771 1772 blsp1_i2c3_default: blsp1-i2c3-default-state { 1773 pins = "gpio10", "gpio11"; 1774 function = "blsp_i2c3"; 1775 drive-strength = <2>; 1776 bias-disable; 1777 }; 1778 1779 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state { 1780 pins = "gpio10", "gpio11"; 1781 function = "blsp_i2c3"; 1782 drive-strength = <2>; 1783 bias-pull-up; 1784 }; 1785 1786 /* BLSP1_I2C4 info is missing */ 1787 1788 /* BLSP1_I2C5 info is missing */ 1789 1790 blsp1_i2c6_default: blsp1-i2c6-default-state { 1791 pins = "gpio29", "gpio30"; 1792 function = "blsp_i2c6"; 1793 drive-strength = <2>; 1794 bias-disable; 1795 }; 1796 1797 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state { 1798 pins = "gpio29", "gpio30"; 1799 function = "blsp_i2c6"; 1800 drive-strength = <2>; 1801 bias-pull-up; 1802 }; 1803 /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */ 1804 1805 /* BLSP2_I2C1 info is missing */ 1806 1807 blsp2_i2c2_default: blsp2-i2c2-default-state { 1808 pins = "gpio47", "gpio48"; 1809 function = "blsp_i2c8"; 1810 drive-strength = <2>; 1811 bias-disable; 1812 }; 1813 1814 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state { 1815 pins = "gpio47", "gpio48"; 1816 function = "blsp_i2c8"; 1817 drive-strength = <2>; 1818 bias-pull-up; 1819 }; 1820 1821 /* BLSP2_I2C3 info is missing */ 1822 1823 /* BLSP2_I2C4 info is missing */ 1824 1825 blsp2_i2c5_default: blsp2-i2c5-default-state { 1826 pins = "gpio83", "gpio84"; 1827 function = "blsp_i2c11"; 1828 drive-strength = <2>; 1829 bias-disable; 1830 }; 1831 1832 blsp2_i2c5_sleep: blsp2-i2c5-sleep-state { 1833 pins = "gpio83", "gpio84"; 1834 function = "blsp_i2c11"; 1835 drive-strength = <2>; 1836 bias-pull-up; 1837 }; 1838 1839 blsp2_i2c6_default: blsp2-i2c6-default-state { 1840 pins = "gpio87", "gpio88"; 1841 function = "blsp_i2c12"; 1842 drive-strength = <2>; 1843 bias-disable; 1844 }; 1845 1846 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state { 1847 pins = "gpio87", "gpio88"; 1848 function = "blsp_i2c12"; 1849 drive-strength = <2>; 1850 bias-pull-up; 1851 }; 1852 1853 cci_default: cci-default-state { 1854 cci_i2c0_default: cci-i2c0-default-pins { 1855 pins = "gpio19", "gpio20"; 1856 function = "cci_i2c0"; 1857 drive-strength = <2>; 1858 bias-disable; 1859 }; 1860 1861 cci_i2c1_default: cci-i2c1-default-pins { 1862 pins = "gpio21", "gpio22"; 1863 function = "cci_i2c1"; 1864 drive-strength = <2>; 1865 bias-disable; 1866 }; 1867 }; 1868 1869 cci_sleep: cci-sleep-state { 1870 cci_i2c0_sleep: cci-i2c0-sleep-pins { 1871 pins = "gpio19", "gpio20"; 1872 function = "gpio"; 1873 drive-strength = <2>; 1874 bias-disable; 1875 }; 1876 1877 cci_i2c1_sleep: cci-i2c1-sleep-pins { 1878 pins = "gpio21", "gpio22"; 1879 function = "gpio"; 1880 drive-strength = <2>; 1881 bias-disable; 1882 }; 1883 }; 1884 1885 spi8_default: spi8_default-state { 1886 mosi-pins { 1887 pins = "gpio45"; 1888 function = "blsp_spi8"; 1889 }; 1890 miso-pins { 1891 pins = "gpio46"; 1892 function = "blsp_spi8"; 1893 }; 1894 cs-pins { 1895 pins = "gpio47"; 1896 function = "blsp_spi8"; 1897 }; 1898 clk-pins { 1899 pins = "gpio48"; 1900 function = "blsp_spi8"; 1901 }; 1902 }; 1903 }; 1904 1905 mmcc: clock-controller@fd8c0000 { 1906 compatible = "qcom,mmcc-msm8974"; 1907 #clock-cells = <1>; 1908 #reset-cells = <1>; 1909 #power-domain-cells = <1>; 1910 reg = <0xfd8c0000 0x6000>; 1911 clocks = <&xo_board>, 1912 <&gcc GCC_MMSS_GPLL0_CLK_SRC>, 1913 <&gcc GPLL0_VOTE>, 1914 <&gcc GPLL1_VOTE>, 1915 <&rpmcc RPM_SMD_GFX3D_CLK_SRC>, 1916 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 1917 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 1918 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, 1919 <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 1920 <0>, 1921 <0>, 1922 <0>; 1923 clock-names = "xo", 1924 "mmss_gpll0_vote", 1925 "gpll0_vote", 1926 "gpll1_vote", 1927 "gfx3d_clk_src", 1928 "dsi0pll", 1929 "dsi0pllbyte", 1930 "dsi1pll", 1931 "dsi1pllbyte", 1932 "hdmipll", 1933 "edp_link_clk", 1934 "edp_vco_div"; 1935 }; 1936 1937 mdss: display-subsystem@fd900000 { 1938 compatible = "qcom,mdss"; 1939 reg = <0xfd900000 0x100>, <0xfd924000 0x1000>; 1940 reg-names = "mdss_phys", "vbif_phys"; 1941 1942 power-domains = <&mmcc MDSS_GDSC>; 1943 1944 clocks = <&mmcc MDSS_AHB_CLK>, 1945 <&mmcc MDSS_AXI_CLK>, 1946 <&mmcc MDSS_VSYNC_CLK>; 1947 clock-names = "iface", "bus", "vsync"; 1948 1949 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1950 1951 interrupt-controller; 1952 #interrupt-cells = <1>; 1953 1954 status = "disabled"; 1955 1956 #address-cells = <1>; 1957 #size-cells = <1>; 1958 ranges; 1959 1960 mdp: display-controller@fd900000 { 1961 compatible = "qcom,msm8974-mdp5", "qcom,mdp5"; 1962 reg = <0xfd900100 0x22000>; 1963 reg-names = "mdp_phys"; 1964 1965 interrupt-parent = <&mdss>; 1966 interrupts = <0>; 1967 1968 clocks = <&mmcc MDSS_AHB_CLK>, 1969 <&mmcc MDSS_AXI_CLK>, 1970 <&mmcc MDSS_MDP_CLK>, 1971 <&mmcc MDSS_VSYNC_CLK>; 1972 clock-names = "iface", "bus", "core", "vsync"; 1973 1974 interconnects = <&mmssnoc MNOC_MAS_MDP_PORT0 &bimc BIMC_SLV_EBI_CH0>; 1975 interconnect-names = "mdp0-mem"; 1976 1977 ports { 1978 #address-cells = <1>; 1979 #size-cells = <0>; 1980 1981 port@0 { 1982 reg = <0>; 1983 mdp5_intf1_out: endpoint { 1984 remote-endpoint = <&mdss_dsi0_in>; 1985 }; 1986 }; 1987 1988 port@1 { 1989 reg = <1>; 1990 mdp5_intf2_out: endpoint { 1991 remote-endpoint = <&mdss_dsi1_in>; 1992 }; 1993 }; 1994 }; 1995 }; 1996 1997 mdss_dsi0: dsi@fd922800 { 1998 compatible = "qcom,msm8974-dsi-ctrl", 1999 "qcom,mdss-dsi-ctrl"; 2000 reg = <0xfd922800 0x1f8>; 2001 reg-names = "dsi_ctrl"; 2002 2003 interrupt-parent = <&mdss>; 2004 interrupts = <4>; 2005 2006 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, 2007 <&mmcc PCLK0_CLK_SRC>; 2008 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 2009 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 2010 2011 clocks = <&mmcc MDSS_MDP_CLK>, 2012 <&mmcc MDSS_AHB_CLK>, 2013 <&mmcc MDSS_AXI_CLK>, 2014 <&mmcc MDSS_BYTE0_CLK>, 2015 <&mmcc MDSS_PCLK0_CLK>, 2016 <&mmcc MDSS_ESC0_CLK>, 2017 <&mmcc MMSS_MISC_AHB_CLK>; 2018 clock-names = "mdp_core", 2019 "iface", 2020 "bus", 2021 "byte", 2022 "pixel", 2023 "core", 2024 "core_mmss"; 2025 2026 phys = <&mdss_dsi0_phy>; 2027 2028 status = "disabled"; 2029 2030 #address-cells = <1>; 2031 #size-cells = <0>; 2032 2033 ports { 2034 #address-cells = <1>; 2035 #size-cells = <0>; 2036 2037 port@0 { 2038 reg = <0>; 2039 mdss_dsi0_in: endpoint { 2040 remote-endpoint = <&mdp5_intf1_out>; 2041 }; 2042 }; 2043 2044 port@1 { 2045 reg = <1>; 2046 mdss_dsi0_out: endpoint { 2047 }; 2048 }; 2049 }; 2050 }; 2051 2052 mdss_dsi0_phy: phy@fd922a00 { 2053 compatible = "qcom,dsi-phy-28nm-hpm"; 2054 reg = <0xfd922a00 0xd4>, 2055 <0xfd922b00 0x280>, 2056 <0xfd922d80 0x30>; 2057 reg-names = "dsi_pll", 2058 "dsi_phy", 2059 "dsi_phy_regulator"; 2060 2061 #clock-cells = <1>; 2062 #phy-cells = <0>; 2063 2064 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; 2065 clock-names = "iface", "ref"; 2066 2067 status = "disabled"; 2068 }; 2069 2070 mdss_dsi1: dsi@fd922e00 { 2071 compatible = "qcom,msm8974-dsi-ctrl", 2072 "qcom,mdss-dsi-ctrl"; 2073 reg = <0xfd922e00 0x1f8>; 2074 reg-names = "dsi_ctrl"; 2075 2076 interrupt-parent = <&mdss>; 2077 interrupts = <4>; 2078 2079 assigned-clocks = <&mmcc BYTE1_CLK_SRC>, 2080 <&mmcc PCLK1_CLK_SRC>; 2081 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 2082 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; 2083 2084 clocks = <&mmcc MDSS_MDP_CLK>, 2085 <&mmcc MDSS_AHB_CLK>, 2086 <&mmcc MDSS_AXI_CLK>, 2087 <&mmcc MDSS_BYTE1_CLK>, 2088 <&mmcc MDSS_PCLK1_CLK>, 2089 <&mmcc MDSS_ESC1_CLK>, 2090 <&mmcc MMSS_MISC_AHB_CLK>; 2091 clock-names = "mdp_core", 2092 "iface", 2093 "bus", 2094 "byte", 2095 "pixel", 2096 "core", 2097 "core_mmss"; 2098 2099 phys = <&mdss_dsi1_phy>; 2100 2101 status = "disabled"; 2102 2103 #address-cells = <1>; 2104 #size-cells = <0>; 2105 2106 ports { 2107 #address-cells = <1>; 2108 #size-cells = <0>; 2109 2110 port@0 { 2111 reg = <0>; 2112 mdss_dsi1_in: endpoint { 2113 remote-endpoint = <&mdp5_intf2_out>; 2114 }; 2115 }; 2116 2117 port@1 { 2118 reg = <1>; 2119 mdss_dsi1_out: endpoint { 2120 }; 2121 }; 2122 }; 2123 }; 2124 2125 mdss_dsi1_phy: phy@fd923000 { 2126 compatible = "qcom,dsi-phy-28nm-hpm"; 2127 reg = <0xfd923000 0xd4>, 2128 <0xfd923100 0x280>, 2129 <0xfd923380 0x30>; 2130 reg-names = "dsi_pll", 2131 "dsi_phy", 2132 "dsi_phy_regulator"; 2133 2134 #clock-cells = <1>; 2135 #phy-cells = <0>; 2136 2137 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; 2138 clock-names = "iface", "ref"; 2139 2140 status = "disabled"; 2141 }; 2142 }; 2143 2144 cci: cci@fda0c000 { 2145 compatible = "qcom,msm8974-cci"; 2146 #address-cells = <1>; 2147 #size-cells = <0>; 2148 reg = <0xfda0c000 0x1000>; 2149 interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; 2150 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 2151 <&mmcc CAMSS_CCI_CCI_AHB_CLK>, 2152 <&mmcc CAMSS_CCI_CCI_CLK>; 2153 clock-names = "camss_top_ahb", 2154 "cci_ahb", 2155 "cci"; 2156 2157 pinctrl-names = "default", "sleep"; 2158 pinctrl-0 = <&cci_default>; 2159 pinctrl-1 = <&cci_sleep>; 2160 2161 status = "disabled"; 2162 2163 cci_i2c0: i2c-bus@0 { 2164 reg = <0>; 2165 clock-frequency = <100000>; 2166 #address-cells = <1>; 2167 #size-cells = <0>; 2168 }; 2169 2170 cci_i2c1: i2c-bus@1 { 2171 reg = <1>; 2172 clock-frequency = <100000>; 2173 #address-cells = <1>; 2174 #size-cells = <0>; 2175 }; 2176 }; 2177 2178 gpu: gpu@fdb00000 { 2179 compatible = "qcom,adreno-330.1", "qcom,adreno"; 2180 reg = <0xfdb00000 0x10000>; 2181 reg-names = "kgsl_3d0_reg_memory"; 2182 2183 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 2184 interrupt-names = "kgsl_3d0_irq"; 2185 2186 clocks = <&mmcc OXILI_GFX3D_CLK>, 2187 <&mmcc OXILICX_AHB_CLK>, 2188 <&mmcc OXILICX_AXI_CLK>; 2189 clock-names = "core", "iface", "mem_iface"; 2190 2191 sram = <&gmu_sram>; 2192 power-domains = <&mmcc OXILICX_GDSC>; 2193 operating-points-v2 = <&gpu_opp_table>; 2194 2195 interconnects = <&mmssnoc MNOC_MAS_GRAPHICS_3D &bimc BIMC_SLV_EBI_CH0>, 2196 <&ocmemnoc OCMEM_VNOC_MAS_GFX3D &ocmemnoc OCMEM_SLV_OCMEM>; 2197 interconnect-names = "gfx-mem", "ocmem"; 2198 2199 // iommus = <&gpu_iommu 0>; 2200 2201 status = "disabled"; 2202 2203 gpu_opp_table: opp-table { 2204 compatible = "operating-points-v2"; 2205 2206 opp-320000000 { 2207 opp-hz = /bits/ 64 <320000000>; 2208 }; 2209 2210 opp-200000000 { 2211 opp-hz = /bits/ 64 <200000000>; 2212 }; 2213 2214 opp-27000000 { 2215 opp-hz = /bits/ 64 <27000000>; 2216 }; 2217 }; 2218 }; 2219 2220 sram@fdd00000 { 2221 compatible = "qcom,msm8974-ocmem"; 2222 reg = <0xfdd00000 0x2000>, 2223 <0xfec00000 0x180000>; 2224 reg-names = "ctrl", "mem"; 2225 ranges = <0 0xfec00000 0x180000>; 2226 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, 2227 <&mmcc OCMEMCX_OCMEMNOC_CLK>; 2228 clock-names = "core", "iface"; 2229 2230 #address-cells = <1>; 2231 #size-cells = <1>; 2232 2233 gmu_sram: gmu-sram@0 { 2234 reg = <0x0 0x100000>; 2235 }; 2236 }; 2237 2238 remoteproc_adsp: remoteproc@fe200000 { 2239 compatible = "qcom,msm8974-adsp-pil"; 2240 reg = <0xfe200000 0x100>; 2241 2242 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 2243 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2244 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2245 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2246 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2247 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 2248 2249 clocks = <&xo_board>; 2250 clock-names = "xo"; 2251 2252 power-domains = <&rpmpd MSM8974_VDDCX>; 2253 power-domain-names = "cx"; 2254 2255 memory-region = <&adsp_region>; 2256 2257 qcom,smem-states = <&adsp_smp2p_out 0>; 2258 qcom,smem-state-names = "stop"; 2259 2260 status = "disabled"; 2261 2262 smd-edge { 2263 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 2264 2265 mboxes = <&apcs 8>; 2266 qcom,smd-edge = <1>; 2267 label = "lpass"; 2268 }; 2269 }; 2270 2271 imem: sram@fe805000 { 2272 compatible = "qcom,msm8974-imem", "syscon", "simple-mfd"; 2273 reg = <0xfe805000 0x1000>; 2274 2275 reboot-mode { 2276 compatible = "syscon-reboot-mode"; 2277 offset = <0x65c>; 2278 }; 2279 }; 2280 }; 2281 2282 thermal-zones { 2283 cpu0-thermal { 2284 polling-delay-passive = <250>; 2285 polling-delay = <1000>; 2286 2287 thermal-sensors = <&tsens 5>; 2288 2289 trips { 2290 cpu_alert0: trip0 { 2291 temperature = <75000>; 2292 hysteresis = <2000>; 2293 type = "passive"; 2294 }; 2295 cpu_crit0: trip1 { 2296 temperature = <110000>; 2297 hysteresis = <2000>; 2298 type = "critical"; 2299 }; 2300 }; 2301 }; 2302 2303 cpu1-thermal { 2304 polling-delay-passive = <250>; 2305 polling-delay = <1000>; 2306 2307 thermal-sensors = <&tsens 6>; 2308 2309 trips { 2310 cpu_alert1: trip0 { 2311 temperature = <75000>; 2312 hysteresis = <2000>; 2313 type = "passive"; 2314 }; 2315 cpu_crit1: trip1 { 2316 temperature = <110000>; 2317 hysteresis = <2000>; 2318 type = "critical"; 2319 }; 2320 }; 2321 }; 2322 2323 cpu2-thermal { 2324 polling-delay-passive = <250>; 2325 polling-delay = <1000>; 2326 2327 thermal-sensors = <&tsens 7>; 2328 2329 trips { 2330 cpu_alert2: trip0 { 2331 temperature = <75000>; 2332 hysteresis = <2000>; 2333 type = "passive"; 2334 }; 2335 cpu_crit2: trip1 { 2336 temperature = <110000>; 2337 hysteresis = <2000>; 2338 type = "critical"; 2339 }; 2340 }; 2341 }; 2342 2343 cpu3-thermal { 2344 polling-delay-passive = <250>; 2345 polling-delay = <1000>; 2346 2347 thermal-sensors = <&tsens 8>; 2348 2349 trips { 2350 cpu_alert3: trip0 { 2351 temperature = <75000>; 2352 hysteresis = <2000>; 2353 type = "passive"; 2354 }; 2355 cpu_crit3: trip1 { 2356 temperature = <110000>; 2357 hysteresis = <2000>; 2358 type = "critical"; 2359 }; 2360 }; 2361 }; 2362 2363 q6-dsp-thermal { 2364 polling-delay-passive = <250>; 2365 polling-delay = <1000>; 2366 2367 thermal-sensors = <&tsens 1>; 2368 2369 trips { 2370 q6_dsp_alert0: trip-point0 { 2371 temperature = <90000>; 2372 hysteresis = <2000>; 2373 type = "hot"; 2374 }; 2375 }; 2376 }; 2377 2378 modemtx-thermal { 2379 polling-delay-passive = <250>; 2380 polling-delay = <1000>; 2381 2382 thermal-sensors = <&tsens 2>; 2383 2384 trips { 2385 modemtx_alert0: trip-point0 { 2386 temperature = <90000>; 2387 hysteresis = <2000>; 2388 type = "hot"; 2389 }; 2390 }; 2391 }; 2392 2393 video-thermal { 2394 polling-delay-passive = <250>; 2395 polling-delay = <1000>; 2396 2397 thermal-sensors = <&tsens 3>; 2398 2399 trips { 2400 video_alert0: trip-point0 { 2401 temperature = <95000>; 2402 hysteresis = <2000>; 2403 type = "hot"; 2404 }; 2405 }; 2406 }; 2407 2408 wlan-thermal { 2409 polling-delay-passive = <250>; 2410 polling-delay = <1000>; 2411 2412 thermal-sensors = <&tsens 4>; 2413 2414 trips { 2415 wlan_alert0: trip-point0 { 2416 temperature = <105000>; 2417 hysteresis = <2000>; 2418 type = "hot"; 2419 }; 2420 }; 2421 }; 2422 2423 gpu-top-thermal { 2424 polling-delay-passive = <250>; 2425 polling-delay = <1000>; 2426 2427 thermal-sensors = <&tsens 9>; 2428 2429 trips { 2430 gpu1_alert0: trip-point0 { 2431 temperature = <90000>; 2432 hysteresis = <2000>; 2433 type = "hot"; 2434 }; 2435 }; 2436 }; 2437 2438 gpu-bottom-thermal { 2439 polling-delay-passive = <250>; 2440 polling-delay = <1000>; 2441 2442 thermal-sensors = <&tsens 10>; 2443 2444 trips { 2445 gpu2_alert0: trip-point0 { 2446 temperature = <90000>; 2447 hysteresis = <2000>; 2448 type = "hot"; 2449 }; 2450 }; 2451 }; 2452 }; 2453 2454 timer { 2455 compatible = "arm,armv7-timer"; 2456 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2457 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2458 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2459 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2460 clock-frequency = <19200000>; 2461 }; 2462}; 2463