1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2#include <dt-bindings/interrupt-controller/arm-gic.h> 3 4/ { 5 compatible = "brcm,bcm2712"; 6 7 #address-cells = <2>; 8 #size-cells = <2>; 9 10 interrupt-parent = <&gicv2>; 11 12 clocks { 13 /* The oscillator is the root of the clock tree. */ 14 clk_osc: clk-osc { 15 compatible = "fixed-clock"; 16 #clock-cells = <0>; 17 clock-output-names = "osc"; 18 clock-frequency = <54000000>; 19 }; 20 21 clk_vpu: clk-vpu { 22 compatible = "fixed-clock"; 23 #clock-cells = <0>; 24 clock-frequency = <750000000>; 25 clock-output-names = "vpu-clock"; 26 }; 27 28 clk_uart: clk-uart { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <9216000>; 32 clock-output-names = "uart-clock"; 33 }; 34 35 clk_emmc2: clk-emmc2 { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <200000000>; 39 clock-output-names = "emmc2-clock"; 40 }; 41 42 clk_sw_baud: clk-sw-baud { 43 compatible = "fixed-clock"; 44 #clock-cells = <0>; 45 clock-frequency = <96000000>; 46 clock-output-names = "sw-baud"; 47 }; 48 }; 49 50 cpus: cpus { 51 #address-cells = <1>; 52 #size-cells = <0>; 53 54 /* Source for L1 d/i cache-line-size, cache-sets, cache-size 55 * https://developer.arm.com/documentation/100798/0401/L1-memory-system/About-the-L1-memory-system?lang=en 56 * Source for L2 cache-line-size and cache-sets: 57 * https://developer.arm.com/documentation/100798/0401/L2-memory-system/About-the-L2-memory-system?lang=en 58 * and for cache-size: 59 * https://www.raspberrypi.com/documentation/computers/processors.html#bcm2712 60 */ 61 cpu0: cpu@0 { 62 device_type = "cpu"; 63 compatible = "arm,cortex-a76"; 64 reg = <0x000>; 65 enable-method = "psci"; 66 d-cache-size = <0x10000>; 67 d-cache-line-size = <64>; 68 d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set 69 i-cache-size = <0x10000>; 70 i-cache-line-size = <64>; 71 i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set 72 next-level-cache = <&l2_cache_l0>; 73 74 l2_cache_l0: l2-cache { 75 compatible = "cache"; 76 cache-size = <0x80000>; 77 cache-line-size = <64>; 78 cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set 79 cache-level = <2>; 80 cache-unified; 81 next-level-cache = <&l3_cache>; 82 }; 83 }; 84 85 cpu1: cpu@1 { 86 device_type = "cpu"; 87 compatible = "arm,cortex-a76"; 88 reg = <0x100>; 89 enable-method = "psci"; 90 d-cache-size = <0x10000>; 91 d-cache-line-size = <64>; 92 d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set 93 i-cache-size = <0x10000>; 94 i-cache-line-size = <64>; 95 i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set 96 next-level-cache = <&l2_cache_l1>; 97 98 l2_cache_l1: l2-cache { 99 compatible = "cache"; 100 cache-size = <0x80000>; 101 cache-line-size = <64>; 102 cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set 103 cache-level = <2>; 104 cache-unified; 105 next-level-cache = <&l3_cache>; 106 }; 107 }; 108 109 cpu2: cpu@2 { 110 device_type = "cpu"; 111 compatible = "arm,cortex-a76"; 112 reg = <0x200>; 113 enable-method = "psci"; 114 d-cache-size = <0x10000>; 115 d-cache-line-size = <64>; 116 d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set 117 i-cache-size = <0x10000>; 118 i-cache-line-size = <64>; 119 i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set 120 next-level-cache = <&l2_cache_l2>; 121 122 l2_cache_l2: l2-cache { 123 compatible = "cache"; 124 cache-size = <0x80000>; 125 cache-line-size = <64>; 126 cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set 127 cache-level = <2>; 128 cache-unified; 129 next-level-cache = <&l3_cache>; 130 }; 131 }; 132 133 cpu3: cpu@3 { 134 device_type = "cpu"; 135 compatible = "arm,cortex-a76"; 136 reg = <0x300>; 137 enable-method = "psci"; 138 d-cache-size = <0x10000>; 139 d-cache-line-size = <64>; 140 d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set 141 i-cache-size = <0x10000>; 142 i-cache-line-size = <64>; 143 i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set 144 next-level-cache = <&l2_cache_l3>; 145 146 l2_cache_l3: l2-cache { 147 compatible = "cache"; 148 cache-size = <0x80000>; 149 cache-line-size = <64>; 150 cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set 151 cache-level = <2>; 152 cache-unified; 153 next-level-cache = <&l3_cache>; 154 }; 155 }; 156 157 /* Source for cache-line-size and cache-sets: 158 * https://developer.arm.com/documentation/100453/0401/L3-cache?lang=en 159 * Source for cache-size: 160 * https://www.raspberrypi.com/documentation/computers/processors.html#bcm2712 161 */ 162 l3_cache: l3-cache { 163 compatible = "cache"; 164 cache-size = <0x200000>; 165 cache-line-size = <64>; 166 cache-sets = <2048>; // 2MiB(size)/64(line-size)=32768ways/16-way set 167 cache-level = <3>; 168 cache-unified; 169 }; 170 }; 171 172 psci { 173 method = "smc"; 174 compatible = "arm,psci-1.0", "arm,psci-0.2"; 175 }; 176 177 rmem: reserved-memory { 178 ranges; 179 #address-cells = <2>; 180 #size-cells = <2>; 181 182 atf@0 { 183 reg = <0x0 0x0 0x0 0x80000>; 184 no-map; 185 }; 186 187 cma: linux,cma { 188 compatible = "shared-dma-pool"; 189 size = <0x0 0x4000000>; /* 64MB */ 190 reusable; 191 linux,cma-default; 192 alloc-ranges = <0x0 0x00000000 0x0 0x40000000>; 193 }; 194 }; 195 196 soc: soc@107c000000 { 197 compatible = "simple-bus"; 198 ranges = <0x00000000 0x10 0x00000000 0x80000000>; 199 #address-cells = <1>; 200 #size-cells = <1>; 201 202 pcie_rescal: reset-controller@119500 { 203 compatible = "brcm,bcm7216-pcie-sata-rescal"; 204 reg = <0x00119500 0x10>; 205 #reset-cells = <0>; 206 }; 207 208 sdio1: mmc@fff000 { 209 compatible = "brcm,bcm2712-sdhci", 210 "brcm,sdhci-brcmstb"; 211 reg = <0x00fff000 0x260>, 212 <0x00fff400 0x200>; 213 reg-names = "host", "cfg"; 214 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>; 215 clocks = <&clk_emmc2>; 216 clock-names = "sw_sdio"; 217 mmc-ddr-3_3v; 218 }; 219 220 bcm_reset: reset-controller@1504318 { 221 compatible = "brcm,brcmstb-reset"; 222 reg = <0x01504318 0x30>; 223 #reset-cells = <1>; 224 }; 225 226 system_timer: timer@7c003000 { 227 compatible = "brcm,bcm2835-system-timer"; 228 reg = <0x7c003000 0x1000>; 229 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 230 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 231 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 233 clock-frequency = <1000000>; 234 }; 235 236 mailbox: mailbox@7c013880 { 237 compatible = "brcm,bcm2835-mbox"; 238 reg = <0x7c013880 0x40>; 239 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 240 #mbox-cells = <0>; 241 }; 242 243 uart10: serial@7d001000 { 244 compatible = "arm,pl011", "arm,primecell"; 245 reg = <0x7d001000 0x200>; 246 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 247 clocks = <&clk_uart>, <&clk_vpu>; 248 clock-names = "uartclk", "apb_pclk"; 249 arm,primecell-periphid = <0x00341011>; 250 status = "disabled"; 251 }; 252 253 pm: watchdog@7d200000 { 254 compatible = "brcm,bcm2712-pm", "brcm,bcm2835-pm-wdt"; 255 reg = <0x7d200000 0x604>; 256 reg-names = "pm"; 257 #power-domain-cells = <1>; 258 #reset-cells = <1>; 259 system-power-controller; 260 }; 261 262 pinctrl: pinctrl@7d504100 { 263 compatible = "brcm,bcm2712c0-pinctrl"; 264 reg = <0x7d504100 0x30>; 265 }; 266 267 gio: gpio@7d508500 { 268 compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; 269 reg = <0x7d508500 0x40>; 270 interrupt-parent = <&main_irq>; 271 interrupts = <0>; 272 gpio-controller; 273 #gpio-cells = <2>; 274 interrupt-controller; 275 #interrupt-cells = <2>; 276 brcm,gpio-bank-widths = <32 22>; 277 }; 278 279 uarta: serial@7d50c000 { 280 compatible = "brcm,bcm7271-uart"; 281 reg = <0x7d50c000 0x20>; 282 reg-names = "uart"; 283 clocks = <&clk_sw_baud>; 284 clock-names = "sw_baud"; 285 interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>; 286 interrupt-names = "uart"; 287 status = "disabled"; 288 }; 289 290 pinctrl_aon: pinctrl@7d510700 { 291 compatible = "brcm,bcm2712c0-aon-pinctrl"; 292 reg = <0x7d510700 0x20>; 293 }; 294 295 random: rng@7d208000 { 296 compatible = "brcm,bcm2711-rng200"; 297 reg = <0x7d208000 0x28>; 298 status = "okay"; 299 }; 300 301 interrupt-controller@7d517000 { 302 compatible = "brcm,bcm7271-l2-intc"; 303 reg = <0x7d517000 0x10>; 304 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 305 interrupt-controller; 306 #interrupt-cells = <1>; 307 }; 308 309 gio_aon: gpio@7d517c00 { 310 compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; 311 reg = <0x7d517c00 0x40>; 312 gpio-controller; 313 #gpio-cells = <2>; 314 brcm,gpio-bank-widths = <17 6>; 315 /* The lack of 'interrupt-controller' property here is intended: 316 * don't use GIO_AON as an interrupt controller because it will 317 * clash with the firmware monitoring the PMIC interrupt via the VPU. 318 */ 319 }; 320 321 sdio2: mmc@1100000 { 322 compatible = "brcm,bcm2712-sdhci", 323 "brcm,sdhci-brcmstb"; 324 reg = <0x01100000 0x260>, 325 <0x01100400 0x200>; 326 reg-names = "host", "cfg"; 327 interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>; 328 clocks = <&clk_emmc2>; 329 clock-names = "sw_sdio"; 330 sdhci-caps-mask = <0x0000C000 0x0>; 331 sdhci-caps = <0x0 0x0>; 332 mmc-ddr-3_3v; 333 status = "disabled"; 334 }; 335 336 gicv2: interrupt-controller@7fff9000 { 337 compatible = "arm,gic-400"; 338 reg = <0x7fff9000 0x1000>, 339 <0x7fffa000 0x2000>, 340 <0x7fffc000 0x2000>, 341 <0x7fffe000 0x2000>; 342 interrupt-controller; 343 #address-cells = <0>; 344 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | 345 IRQ_TYPE_LEVEL_HIGH)>; 346 #interrupt-cells = <3>; 347 }; 348 349 aon_intr: interrupt-controller@7d510600 { 350 compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc"; 351 reg = <0x7d510600 0x30>; 352 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 353 interrupt-controller; 354 #interrupt-cells = <1>; 355 }; 356 357 pixelvalve0: pixelvalve@7c410000 { 358 compatible = "brcm,bcm2712-pixelvalve0"; 359 reg = <0x7c410000 0x100>; 360 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 361 }; 362 363 pixelvalve1: pixelvalve@7c411000 { 364 compatible = "brcm,bcm2712-pixelvalve1"; 365 reg = <0x7c411000 0x100>; 366 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 367 }; 368 369 mop: mop@7c500000 { 370 compatible = "brcm,bcm2712-mop"; 371 reg = <0x7c500000 0x28>; 372 interrupt-parent = <&disp_intr>; 373 interrupts = <1>; 374 }; 375 376 moplet: moplet@7c501000 { 377 compatible = "brcm,bcm2712-moplet"; 378 reg = <0x7c501000 0x20>; 379 interrupt-parent = <&disp_intr>; 380 interrupts = <0>; 381 }; 382 383 disp_intr: interrupt-controller@7c502000 { 384 compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc"; 385 reg = <0x7c502000 0x30>; 386 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 387 interrupt-controller; 388 #interrupt-cells = <1>; 389 }; 390 391 dvp: clock@7c700000 { 392 compatible = "brcm,brcm2711-dvp"; 393 reg = <0x7c700000 0x10>; 394 clocks = <&clk_108MHz>; 395 #clock-cells = <1>; 396 #reset-cells = <1>; 397 }; 398 399 ddc0: i2c@7d508200 { 400 compatible = "brcm,brcmstb-i2c"; 401 reg = <0x7d508200 0x58>; 402 interrupt-parent = <&bsc_irq>; 403 interrupts = <1>; 404 clock-frequency = <97500>; 405 #address-cells = <1>; 406 #size-cells = <0>; 407 }; 408 409 ddc1: i2c@7d508280 { 410 compatible = "brcm,brcmstb-i2c"; 411 reg = <0x7d508280 0x58>; 412 interrupt-parent = <&bsc_irq>; 413 interrupts = <2>; 414 clock-frequency = <97500>; 415 #address-cells = <1>; 416 #size-cells = <0>; 417 }; 418 419 bsc_irq: interrupt-controller@7d508380 { 420 compatible = "brcm,bcm7271-l2-intc"; 421 reg = <0x7d508380 0x10>; 422 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 423 interrupt-controller; 424 #interrupt-cells = <1>; 425 }; 426 427 main_irq: interrupt-controller@7d508400 { 428 compatible = "brcm,bcm7271-l2-intc"; 429 reg = <0x7d508400 0x10>; 430 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 431 interrupt-controller; 432 #interrupt-cells = <1>; 433 }; 434 435 hdmi0: hdmi@7c701400 { 436 compatible = "brcm,bcm2712-hdmi0"; 437 reg = <0x7c701400 0x300>, 438 <0x7c701000 0x200>, 439 <0x7c701d00 0x300>, 440 <0x7c702000 0x80>, 441 <0x7c703800 0x200>, 442 <0x7c704000 0x800>, 443 <0x7c700100 0x80>, 444 <0x7d510800 0x100>, 445 <0x7c720000 0x100>; 446 reg-names = "hdmi", 447 "dvp", 448 "phy", 449 "rm", 450 "packet", 451 "metadata", 452 "csc", 453 "cec", 454 "hd"; 455 resets = <&dvp 1>; 456 interrupt-parent = <&aon_intr>; 457 interrupts = <1>, <2>, <3>, 458 <7>, <8>; 459 interrupt-names = "cec-tx", "cec-rx", "cec-low", 460 "hpd-connected", "hpd-removed"; 461 ddc = <&ddc0>; 462 }; 463 464 hdmi1: hdmi@7c706400 { 465 compatible = "brcm,bcm2712-hdmi1"; 466 reg = <0x7c706400 0x300>, 467 <0x7c706000 0x200>, 468 <0x7c706d00 0x300>, 469 <0x7c707000 0x80>, 470 <0x7c708800 0x200>, 471 <0x7c709000 0x800>, 472 <0x7c700180 0x80>, 473 <0x7d511000 0x100>, 474 <0x7c720000 0x100>; 475 reg-names = "hdmi", 476 "dvp", 477 "phy", 478 "rm", 479 "packet", 480 "metadata", 481 "csc", 482 "cec", 483 "hd"; 484 resets = <&dvp 2>; 485 interrupt-parent = <&aon_intr>; 486 interrupts = <11>, <12>, <13>, 487 <14>, <15>; 488 interrupt-names = "cec-tx", "cec-rx", "cec-low", 489 "hpd-connected", "hpd-removed"; 490 ddc = <&ddc1>; 491 }; 492 }; 493 494 axi: axi { 495 compatible = "simple-bus"; 496 #address-cells = <2>; 497 #size-cells = <2>; 498 499 ranges = <0x00 0x00000000 0x00 0x00000000 0x10 0x00000000>, 500 <0x10 0x00000000 0x10 0x00000000 0x01 0x00000000>, 501 <0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>, 502 <0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>, 503 <0x1c 0x00000000 0x1c 0x00000000 0x04 0x00000000>; 504 505 dma-ranges = <0x00 0x00000000 0x00 0x00000000 0x10 0x00000000>, 506 <0x10 0x00000000 0x10 0x00000000 0x01 0x00000000>, 507 <0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>, 508 <0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>, 509 <0x1c 0x00000000 0x1c 0x00000000 0x04 0x00000000>; 510 511 vc4: gpu { 512 compatible = "brcm,bcm2712-vc6"; 513 }; 514 515 pcie0: pcie@1000100000 { 516 compatible = "brcm,bcm2712-pcie"; 517 reg = <0x10 0x00100000 0x00 0x9310>; 518 device_type = "pci"; 519 linux,pci-domain = <0>; 520 max-link-speed = <2>; 521 num-lanes = <1>; 522 #address-cells = <3>; 523 #interrupt-cells = <1>; 524 #size-cells = <2>; 525 interrupt-parent = <&gicv2>; 526 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; 528 interrupt-names = "pcie", "msi"; 529 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 530 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 531 <0 0 0 2 &gicv2 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 532 <0 0 0 3 &gicv2 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 533 <0 0 0 4 &gicv2 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; 534 resets = <&pcie_rescal>, <&bcm_reset 42>; 535 reset-names = "rescal", "bridge"; 536 msi-controller; 537 msi-parent = <&pcie0>; 538 539 ranges = 540 /* ~4GiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */ 541 <0x02000000 0x00 0x00000000 0x17 0x00000000 0x00 0xfffffffc>, 542 /* 12GiB, 64-bit, prefetchable at PCIe 04_0000_0000 */ 543 <0x43000000 0x04 0x00000000 0x14 0x00000000 0x03 0x00000000>; 544 545 dma-ranges = 546 /* 64GiB, 64-bit, prefetchable at PCIe 10_0000_0000 */ 547 <0x43000000 0x10 0x00000000 0x00 0x00000000 0x10 0x00000000>; 548 549 status = "disabled"; 550 }; 551 552 pcie1: pcie@1000110000 { 553 compatible = "brcm,bcm2712-pcie"; 554 reg = <0x10 0x00110000 0x00 0x9310>; 555 device_type = "pci"; 556 linux,pci-domain = <1>; 557 max-link-speed = <2>; 558 num-lanes = <1>; 559 #address-cells = <3>; 560 #interrupt-cells = <1>; 561 #size-cells = <2>; 562 interrupt-parent = <&gicv2>; 563 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, 564 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 565 interrupt-names = "pcie", "msi"; 566 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 567 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 568 <0 0 0 2 &gicv2 GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 569 <0 0 0 3 &gicv2 GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, 570 <0 0 0 4 &gicv2 GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 571 resets = <&pcie_rescal>, <&bcm_reset 43>; 572 reset-names = "rescal", "bridge"; 573 msi-controller; 574 msi-parent = <&mip1>; 575 576 ranges = 577 /* ~4GiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */ 578 <0x02000000 0x00 0x00000000 0x1b 0x00000000 0x00 0xfffffffc>, 579 /* 12GiB, 64-bit, prefetchable at PCIe 04_0000_0000 */ 580 <0x43000000 0x04 0x00000000 0x18 0x00000000 0x03 0x00000000>; 581 582 dma-ranges = 583 /* 64GiB, 64-bit, non-prefetchable at PCIe 10_0000_0000 */ 584 <0x03000000 0x10 0x00000000 0x00 0x00000000 0x10 0x00000000>, 585 /* 4KiB, 64-bit, non-prefetchable at PCIe ff_ffff_f000 MIP1 */ 586 <0x03000000 0xff 0xfffff000 0x10 0x00131000 0x00 0x00001000>; 587 588 status = "disabled"; 589 }; 590 591 pcie2: pcie@1000120000 { 592 compatible = "brcm,bcm2712-pcie"; 593 reg = <0x10 0x00120000 0x00 0x9310>; 594 device_type = "pci"; 595 linux,pci-domain = <2>; 596 max-link-speed = <2>; 597 num-lanes = <4>; 598 #address-cells = <3>; 599 #interrupt-cells = <1>; 600 #size-cells = <2>; 601 interrupt-parent = <&gicv2>; 602 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>, 603 <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 604 interrupt-names = "pcie", "msi"; 605 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 606 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 607 <0 0 0 2 &gicv2 GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 608 <0 0 0 3 &gicv2 GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 609 <0 0 0 4 &gicv2 GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 610 resets = <&pcie_rescal>, <&bcm_reset 44>; 611 reset-names = "rescal", "bridge"; 612 msi-controller; 613 msi-parent = <&mip0>; 614 615 ranges = 616 /* ~4GiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */ 617 <0x02000000 0x00 0x00000000 0x1f 0x00000000 0x00 0xfffffffc>, 618 /* 12GiB, 64-bit, prefetchable at PCIe 04_0000_0000 */ 619 <0x43000000 0x04 0x00000000 0x1c 0x00000000 0x03 0x00000000>; 620 621 dma-ranges = 622 /* 4MiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */ 623 <0x02000000 0x00 0x00000000 0x1f 0x00000000 0x00 0x00400000>, 624 /* 64GiB, 64-bit, prefetchable at PCIe 10_0000_0000 */ 625 <0x43000000 0x10 0x00000000 0x00 0x00000000 0x10 0x00000000>, 626 /* 4KiB, 64-bit, non-prefetchable at PCIe ff_ffff_f000 MIP0 */ 627 <0x03000000 0xff 0xfffff000 0x10 0x00130000 0x00 0x00001000>; 628 629 status = "disabled"; 630 }; 631 632 mip0: msi-controller@1000130000 { 633 compatible = "brcm,bcm2712-mip"; 634 reg = <0x10 0x00130000 0x00 0xc0>, 635 <0xff 0xfffff000 0x00 0x1000>; 636 msi-controller; 637 msi-ranges = <&gicv2 GIC_SPI 128 IRQ_TYPE_EDGE_RISING 64>; 638 brcm,msi-offset = <0>; 639 }; 640 641 mip1: msi-controller@1000131000 { 642 compatible = "brcm,bcm2712-mip"; 643 reg = <0x10 0x00131000 0x00 0xc0>, 644 <0xff 0xfffff000 0x00 0x1000>; 645 msi-controller; 646 msi-ranges = <&gicv2 GIC_SPI 247 IRQ_TYPE_EDGE_RISING 8>; 647 brcm,msi-offset = <8>; 648 }; 649 }; 650 651 timer { 652 compatible = "arm,armv8-timer"; 653 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | 654 IRQ_TYPE_LEVEL_LOW)>, 655 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | 656 IRQ_TYPE_LEVEL_LOW)>, 657 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | 658 IRQ_TYPE_LEVEL_LOW)>, 659 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | 660 IRQ_TYPE_LEVEL_LOW)>, 661 <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(4) | 662 IRQ_TYPE_LEVEL_LOW)>; 663 }; 664 665 clk_27MHz: clk-27M { 666 #clock-cells = <0>; 667 compatible = "fixed-clock"; 668 clock-frequency = <27000000>; 669 clock-output-names = "27MHz-clock"; 670 }; 671 672 clk_108MHz: clk-108M { 673 #clock-cells = <0>; 674 compatible = "fixed-clock"; 675 clock-frequency = <108000000>; 676 clock-output-names = "108MHz-clock"; 677 }; 678 679 hvs: hvs@107c580000 { 680 compatible = "brcm,bcm2712-hvs"; 681 reg = <0x10 0x7c580000 0x0 0x1a000>; 682 interrupt-parent = <&disp_intr>; 683 interrupts = <2>, <9>, <16>; 684 interrupt-names = "ch0-eof", "ch1-eof", "ch2-eof"; 685 }; 686}; 687