1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2018 Emmanuel Vadot <manu@FreeBSD.org>
5 * Copyright (c) 2013 Alexander Fedorov
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/bus.h>
33 #include <sys/conf.h>
34 #include <sys/kernel.h>
35 #include <sys/lock.h>
36 #include <sys/malloc.h>
37 #include <sys/module.h>
38 #include <sys/mutex.h>
39 #include <sys/resource.h>
40 #include <sys/rman.h>
41 #include <sys/sysctl.h>
42 #include <sys/queue.h>
43 #include <sys/taskqueue.h>
44
45 #include <machine/bus.h>
46
47 #include <dev/ofw/ofw_bus.h>
48 #include <dev/ofw/ofw_bus_subr.h>
49
50 #include <dev/mmc/bridge.h>
51 #include <dev/mmc/mmcbrvar.h>
52 #include <dev/mmc/mmc_fdt_helpers.h>
53
54 #include <arm/allwinner/aw_mmc.h>
55 #include <dev/clk/clk.h>
56 #include <dev/hwreset/hwreset.h>
57 #include <dev/regulator/regulator.h>
58
59 #include "opt_mmccam.h"
60
61 #ifdef MMCCAM
62 #include <cam/cam.h>
63 #include <cam/cam_ccb.h>
64 #include <cam/cam_debug.h>
65 #include <cam/cam_sim.h>
66 #include <cam/cam_xpt_sim.h>
67 #include <cam/mmc/mmc_sim.h>
68
69 #include "mmc_sim_if.h"
70 #endif
71
72 #include "mmc_pwrseq_if.h"
73
74 #define AW_MMC_MEMRES 0
75 #define AW_MMC_IRQRES 1
76 #define AW_MMC_RESSZ 2
77 #define AW_MMC_DMA_SEGS (PAGE_SIZE / sizeof(struct aw_mmc_dma_desc))
78 #define AW_MMC_DMA_DESC_SIZE (sizeof(struct aw_mmc_dma_desc) * AW_MMC_DMA_SEGS)
79 #define AW_MMC_DMA_FTRGLEVEL 0x20070008
80
81 #define AW_MMC_RESET_RETRY 1000
82
83 #define CARD_ID_FREQUENCY 400000
84
85 struct aw_mmc_conf {
86 uint32_t dma_xferlen;
87 uint32_t dma_desc_shift;
88 bool mask_data0;
89 bool can_calibrate;
90 bool new_timing;
91 bool zero_is_skip;
92 };
93
94 static const struct aw_mmc_conf a10_mmc_conf = {
95 .dma_xferlen = 0x2000,
96 .dma_desc_shift = 0,
97 };
98
99 static const struct aw_mmc_conf a13_mmc_conf = {
100 .dma_xferlen = 0x10000,
101 .dma_desc_shift = 0,
102 };
103
104 static const struct aw_mmc_conf a64_mmc_conf = {
105 .dma_xferlen = 0x10000,
106 .dma_desc_shift = 0,
107 .mask_data0 = true,
108 .can_calibrate = true,
109 .new_timing = true,
110 };
111
112 static const struct aw_mmc_conf a64_emmc_conf = {
113 .dma_xferlen = 0x2000,
114 .dma_desc_shift = 0,
115 .can_calibrate = true,
116 };
117
118 static const struct aw_mmc_conf h616_mmc_conf = {
119 .dma_xferlen = 0x10000,
120 .dma_desc_shift = 2,
121 .mask_data0 = true,
122 .can_calibrate = true,
123 .new_timing = true,
124 };
125
126 static const struct aw_mmc_conf h616_emmc_conf = {
127 .dma_xferlen = 0x10000,
128 .can_calibrate = true,
129 };
130
131 static const struct aw_mmc_conf d1_mmc_conf = {
132 .dma_xferlen = 0x1000,
133 .dma_desc_shift = 2,
134 .mask_data0 = true,
135 .can_calibrate = true,
136 .new_timing = true,
137 .zero_is_skip = true,
138 };
139
140 static struct ofw_compat_data compat_data[] = {
141 {"allwinner,sun4i-a10-mmc", (uintptr_t)&a10_mmc_conf},
142 {"allwinner,sun5i-a13-mmc", (uintptr_t)&a13_mmc_conf},
143 {"allwinner,sun7i-a20-mmc", (uintptr_t)&a13_mmc_conf},
144 {"allwinner,sun20i-d1-mmc", (uintptr_t)&d1_mmc_conf},
145 {"allwinner,sun50i-a64-mmc", (uintptr_t)&a64_mmc_conf},
146 {"allwinner,sun50i-a64-emmc", (uintptr_t)&a64_emmc_conf},
147 {"allwinner,sun50i-h616-mmc", (uintptr_t)&h616_mmc_conf},
148 {"allwinner,sun50i-h616-emmc", (uintptr_t)&h616_emmc_conf},
149 {NULL, 0}
150 };
151
152 struct aw_mmc_softc {
153 device_t aw_dev;
154 clk_t aw_clk_ahb;
155 clk_t aw_clk_mmc;
156 hwreset_t aw_rst_ahb;
157 int aw_bus_busy;
158 int aw_resid;
159 int aw_timeout;
160 struct callout aw_timeoutc;
161 struct mmc_host aw_host;
162 struct mmc_helper mmc_helper;
163 #ifdef MMCCAM
164 union ccb * ccb;
165 struct mmc_sim mmc_sim;
166 #else
167 struct mmc_request * aw_req;
168 #endif
169 struct mtx aw_mtx;
170 struct resource * aw_res[AW_MMC_RESSZ];
171 struct aw_mmc_conf * aw_mmc_conf;
172 uint32_t aw_intr;
173 uint32_t aw_intr_wait;
174 void * aw_intrhand;
175 unsigned int aw_clock;
176 device_t child;
177
178 /* Fields required for DMA access. */
179 bus_addr_t aw_dma_desc_phys;
180 bus_dmamap_t aw_dma_map;
181 bus_dma_tag_t aw_dma_tag;
182 void * aw_dma_desc;
183 bus_dmamap_t aw_dma_buf_map;
184 bus_dma_tag_t aw_dma_buf_tag;
185 int aw_dma_map_err;
186 };
187
188 static struct resource_spec aw_mmc_res_spec[] = {
189 { SYS_RES_MEMORY, 0, RF_ACTIVE },
190 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
191 { -1, 0, 0 }
192 };
193
194 static int aw_mmc_probe(device_t);
195 static int aw_mmc_attach(device_t);
196 static int aw_mmc_detach(device_t);
197 static int aw_mmc_setup_dma(struct aw_mmc_softc *);
198 static void aw_mmc_teardown_dma(struct aw_mmc_softc *sc);
199 static int aw_mmc_reset(struct aw_mmc_softc *);
200 static int aw_mmc_init(struct aw_mmc_softc *);
201 static void aw_mmc_intr(void *);
202 static int aw_mmc_update_clock(struct aw_mmc_softc *, uint32_t);
203 static void aw_mmc_helper_cd_handler(device_t, bool);
204
205 static void aw_mmc_print_error(uint32_t);
206 static int aw_mmc_update_ios(device_t, device_t);
207 static int aw_mmc_request(device_t, device_t, struct mmc_request *);
208
209 #ifndef MMCCAM
210 static int aw_mmc_get_ro(device_t, device_t);
211 static int aw_mmc_acquire_host(device_t, device_t);
212 static int aw_mmc_release_host(device_t, device_t);
213 #endif
214
215 #define AW_MMC_LOCK(_sc) mtx_lock(&(_sc)->aw_mtx)
216 #define AW_MMC_UNLOCK(_sc) mtx_unlock(&(_sc)->aw_mtx)
217 #define AW_MMC_READ_4(_sc, _reg) \
218 bus_read_4((_sc)->aw_res[AW_MMC_MEMRES], _reg)
219 #define AW_MMC_WRITE_4(_sc, _reg, _value) \
220 bus_write_4((_sc)->aw_res[AW_MMC_MEMRES], _reg, _value)
221
222 SYSCTL_NODE(_hw, OID_AUTO, aw_mmc, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
223 "aw_mmc driver");
224
225 static int aw_mmc_debug = 0;
226 SYSCTL_INT(_hw_aw_mmc, OID_AUTO, debug, CTLFLAG_RWTUN, &aw_mmc_debug, 0,
227 "Debug level bit0=card changes bit1=ios changes, bit2=interrupts, bit3=commands");
228 #define AW_MMC_DEBUG_CARD 0x1
229 #define AW_MMC_DEBUG_IOS 0x2
230 #define AW_MMC_DEBUG_INT 0x4
231 #define AW_MMC_DEBUG_CMD 0x8
232
233 #ifdef MMCCAM
234 static int
aw_mmc_get_tran_settings(device_t dev,struct ccb_trans_settings_mmc * cts)235 aw_mmc_get_tran_settings(device_t dev, struct ccb_trans_settings_mmc *cts)
236 {
237 struct aw_mmc_softc *sc;
238
239 sc = device_get_softc(dev);
240
241 cts->host_ocr = sc->aw_host.host_ocr;
242 cts->host_f_min = sc->aw_host.f_min;
243 cts->host_f_max = sc->aw_host.f_max;
244 cts->host_caps = sc->aw_host.caps;
245 cts->host_max_data = (sc->aw_mmc_conf->dma_xferlen *
246 AW_MMC_DMA_SEGS) / MMC_SECTOR_SIZE;
247 memcpy(&cts->ios, &sc->aw_host.ios, sizeof(struct mmc_ios));
248
249 return (0);
250 }
251
252 static int
aw_mmc_set_tran_settings(device_t dev,struct ccb_trans_settings_mmc * cts)253 aw_mmc_set_tran_settings(device_t dev, struct ccb_trans_settings_mmc *cts)
254 {
255 struct aw_mmc_softc *sc;
256 struct mmc_ios *ios;
257 struct mmc_ios *new_ios;
258
259 sc = device_get_softc(dev);
260 ios = &sc->aw_host.ios;
261 new_ios = &cts->ios;
262
263 /* Update only requested fields */
264 if (cts->ios_valid & MMC_CLK) {
265 ios->clock = new_ios->clock;
266 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_IOS))
267 device_printf(sc->aw_dev, "Clock => %d\n", ios->clock);
268 }
269 if (cts->ios_valid & MMC_VDD) {
270 ios->vdd = new_ios->vdd;
271 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_IOS))
272 device_printf(sc->aw_dev, "VDD => %d\n", ios->vdd);
273 }
274 if (cts->ios_valid & MMC_CS) {
275 ios->chip_select = new_ios->chip_select;
276 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_IOS))
277 device_printf(sc->aw_dev, "CS => %d\n", ios->chip_select);
278 }
279 if (cts->ios_valid & MMC_BW) {
280 ios->bus_width = new_ios->bus_width;
281 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_IOS))
282 device_printf(sc->aw_dev, "Bus width => %d\n", ios->bus_width);
283 }
284 if (cts->ios_valid & MMC_PM) {
285 ios->power_mode = new_ios->power_mode;
286 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_IOS))
287 device_printf(sc->aw_dev, "Power mode => %d\n", ios->power_mode);
288 }
289 if (cts->ios_valid & MMC_BT) {
290 ios->timing = new_ios->timing;
291 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_IOS))
292 device_printf(sc->aw_dev, "Timing => %d\n", ios->timing);
293 }
294 if (cts->ios_valid & MMC_BM) {
295 ios->bus_mode = new_ios->bus_mode;
296 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_IOS))
297 device_printf(sc->aw_dev, "Bus mode => %d\n", ios->bus_mode);
298 }
299
300 return (aw_mmc_update_ios(sc->aw_dev, NULL));
301 }
302
303 static int
aw_mmc_cam_request(device_t dev,union ccb * ccb)304 aw_mmc_cam_request(device_t dev, union ccb *ccb)
305 {
306 struct aw_mmc_softc *sc;
307 struct ccb_mmcio *mmcio;
308
309 sc = device_get_softc(dev);
310 mmcio = &ccb->mmcio;
311
312 AW_MMC_LOCK(sc);
313
314 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_CMD)) {
315 device_printf(sc->aw_dev, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n",
316 mmcio->cmd.opcode, mmcio->cmd.arg, mmcio->cmd.flags,
317 mmcio->cmd.data != NULL ? (unsigned int) mmcio->cmd.data->len : 0,
318 mmcio->cmd.data != NULL ? mmcio->cmd.data->flags: 0);
319 }
320 if (mmcio->cmd.data != NULL) {
321 if (mmcio->cmd.data->len == 0 || mmcio->cmd.data->flags == 0)
322 panic("data->len = %d, data->flags = %d -- something is b0rked",
323 (int)mmcio->cmd.data->len, mmcio->cmd.data->flags);
324 }
325 if (sc->ccb != NULL) {
326 device_printf(sc->aw_dev, "Controller still has an active command\n");
327 return (EBUSY);
328 }
329 sc->ccb = ccb;
330 /* aw_mmc_request locks again */
331 AW_MMC_UNLOCK(sc);
332 aw_mmc_request(sc->aw_dev, NULL, NULL);
333
334 return (0);
335 }
336
337 static void
aw_mmc_cam_poll(device_t dev)338 aw_mmc_cam_poll(device_t dev)
339 {
340 struct aw_mmc_softc *sc;
341
342 sc = device_get_softc(dev);
343 aw_mmc_intr(sc);
344 }
345 #endif /* MMCCAM */
346
347 static void
aw_mmc_helper_cd_handler(device_t dev,bool present)348 aw_mmc_helper_cd_handler(device_t dev, bool present)
349 {
350 struct aw_mmc_softc *sc;
351
352 sc = device_get_softc(dev);
353 #ifdef MMCCAM
354 mmc_cam_sim_discover(&sc->mmc_sim);
355 #else
356 bus_topo_lock();
357 if (present) {
358 if (sc->child == NULL) {
359 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_CARD))
360 device_printf(sc->aw_dev, "Card inserted\n");
361
362 sc->child = device_add_child(sc->aw_dev, "mmc", DEVICE_UNIT_ANY);
363 if (sc->child) {
364 device_set_ivars(sc->child, sc);
365 (void)device_probe_and_attach(sc->child);
366 }
367 }
368 } else {
369 /* Card isn't present, detach if necessary */
370 if (sc->child != NULL) {
371 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_CARD))
372 device_printf(sc->aw_dev, "Card removed\n");
373
374 device_delete_child(sc->aw_dev, sc->child);
375 sc->child = NULL;
376 }
377 }
378 bus_topo_unlock();
379 #endif /* MMCCAM */
380 }
381
382 static int
aw_mmc_probe(device_t dev)383 aw_mmc_probe(device_t dev)
384 {
385
386 if (!ofw_bus_status_okay(dev))
387 return (ENXIO);
388 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
389 return (ENXIO);
390
391 device_set_desc(dev, "Allwinner Integrated MMC/SD controller");
392
393 return (BUS_PROBE_DEFAULT);
394 }
395
396 static int
aw_mmc_attach(device_t dev)397 aw_mmc_attach(device_t dev)
398 {
399 struct aw_mmc_softc *sc;
400 struct sysctl_ctx_list *ctx;
401 struct sysctl_oid_list *tree;
402 int error;
403
404 sc = device_get_softc(dev);
405 sc->aw_dev = dev;
406
407 sc->aw_mmc_conf = (struct aw_mmc_conf *)ofw_bus_search_compatible(dev, compat_data)->ocd_data;
408
409 #ifndef MMCCAM
410 sc->aw_req = NULL;
411 #endif
412 if (bus_alloc_resources(dev, aw_mmc_res_spec, sc->aw_res) != 0) {
413 device_printf(dev, "cannot allocate device resources\n");
414 return (ENXIO);
415 }
416 if (bus_setup_intr(dev, sc->aw_res[AW_MMC_IRQRES],
417 INTR_TYPE_NET | INTR_MPSAFE, NULL, aw_mmc_intr, sc,
418 &sc->aw_intrhand)) {
419 bus_release_resources(dev, aw_mmc_res_spec, sc->aw_res);
420 device_printf(dev, "cannot setup interrupt handler\n");
421 return (ENXIO);
422 }
423 mtx_init(&sc->aw_mtx, device_get_nameunit(sc->aw_dev), "aw_mmc",
424 MTX_DEF);
425 callout_init_mtx(&sc->aw_timeoutc, &sc->aw_mtx, 0);
426
427 /* De-assert reset */
428 if (hwreset_get_by_ofw_name(dev, 0, "ahb", &sc->aw_rst_ahb) == 0) {
429 error = hwreset_deassert(sc->aw_rst_ahb);
430 if (error != 0) {
431 device_printf(dev, "cannot de-assert reset\n");
432 goto fail;
433 }
434 }
435
436 /* Activate the module clock. */
437 error = clk_get_by_ofw_name(dev, 0, "ahb", &sc->aw_clk_ahb);
438 if (error != 0) {
439 device_printf(dev, "cannot get ahb clock\n");
440 goto fail;
441 }
442 error = clk_enable(sc->aw_clk_ahb);
443 if (error != 0) {
444 device_printf(dev, "cannot enable ahb clock\n");
445 goto fail;
446 }
447 error = clk_get_by_ofw_name(dev, 0, "mmc", &sc->aw_clk_mmc);
448 if (error != 0) {
449 device_printf(dev, "cannot get mmc clock\n");
450 goto fail;
451 }
452 error = clk_set_freq(sc->aw_clk_mmc, CARD_ID_FREQUENCY,
453 CLK_SET_ROUND_DOWN);
454 if (error != 0) {
455 device_printf(dev, "cannot init mmc clock\n");
456 goto fail;
457 }
458 error = clk_enable(sc->aw_clk_mmc);
459 if (error != 0) {
460 device_printf(dev, "cannot enable mmc clock\n");
461 goto fail;
462 }
463
464 sc->aw_timeout = 10;
465 ctx = device_get_sysctl_ctx(dev);
466 tree = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
467 SYSCTL_ADD_INT(ctx, tree, OID_AUTO, "req_timeout", CTLFLAG_RW,
468 &sc->aw_timeout, 0, "Request timeout in seconds");
469
470 /* Soft Reset controller. */
471 if (aw_mmc_reset(sc) != 0) {
472 device_printf(dev, "cannot reset the controller\n");
473 goto fail;
474 }
475
476 if (aw_mmc_setup_dma(sc) != 0) {
477 device_printf(sc->aw_dev, "Couldn't setup DMA!\n");
478 goto fail;
479 }
480
481 /* Set some defaults for freq and supported mode */
482 sc->aw_host.f_min = 400000;
483 sc->aw_host.f_max = 52000000;
484 sc->aw_host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340;
485 sc->aw_host.caps |= MMC_CAP_HSPEED | MMC_CAP_SIGNALING_330;
486 mmc_fdt_parse(dev, 0, &sc->mmc_helper, &sc->aw_host);
487 mmc_fdt_gpio_setup(dev, 0, &sc->mmc_helper, aw_mmc_helper_cd_handler);
488
489 #ifdef MMCCAM
490 sc->ccb = NULL;
491
492 if (mmc_cam_sim_alloc(dev, "aw_mmc", &sc->mmc_sim) != 0) {
493 device_printf(dev, "cannot alloc cam sim\n");
494 goto fail;
495 }
496 #endif /* MMCCAM */
497
498 return (0);
499
500 fail:
501 callout_drain(&sc->aw_timeoutc);
502 mtx_destroy(&sc->aw_mtx);
503 bus_teardown_intr(dev, sc->aw_res[AW_MMC_IRQRES], sc->aw_intrhand);
504 bus_release_resources(dev, aw_mmc_res_spec, sc->aw_res);
505
506 return (ENXIO);
507 }
508
509 static int
aw_mmc_detach(device_t dev)510 aw_mmc_detach(device_t dev)
511 {
512 struct aw_mmc_softc *sc;
513
514 sc = device_get_softc(dev);
515
516 clk_disable(sc->aw_clk_mmc);
517 clk_disable(sc->aw_clk_ahb);
518 hwreset_assert(sc->aw_rst_ahb);
519
520 mmc_fdt_gpio_teardown(&sc->mmc_helper);
521
522 callout_drain(&sc->aw_timeoutc);
523
524 device_delete_children(sc->aw_dev);
525
526 aw_mmc_teardown_dma(sc);
527
528 mtx_destroy(&sc->aw_mtx);
529
530 bus_teardown_intr(dev, sc->aw_res[AW_MMC_IRQRES], sc->aw_intrhand);
531 bus_release_resources(dev, aw_mmc_res_spec, sc->aw_res);
532
533 #ifdef MMCCAM
534 mmc_cam_sim_free(&sc->mmc_sim);
535 #endif
536
537 return (0);
538 }
539
540 static void
aw_dma_desc_cb(void * arg,bus_dma_segment_t * segs,int nsegs,int err)541 aw_dma_desc_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int err)
542 {
543 struct aw_mmc_softc *sc;
544
545 sc = (struct aw_mmc_softc *)arg;
546 if (err) {
547 sc->aw_dma_map_err = err;
548 return;
549 }
550 sc->aw_dma_desc_phys = segs[0].ds_addr;
551 }
552
553 static int
aw_mmc_setup_dma(struct aw_mmc_softc * sc)554 aw_mmc_setup_dma(struct aw_mmc_softc *sc)
555 {
556 int error;
557
558 /* Allocate the DMA descriptor memory. */
559 error = bus_dma_tag_create(
560 bus_get_dma_tag(sc->aw_dev), /* parent */
561 AW_MMC_DMA_ALIGN, 0, /* align, boundary */
562 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
563 BUS_SPACE_MAXADDR, /* highaddr */
564 NULL, NULL, /* filter, filterarg*/
565 AW_MMC_DMA_DESC_SIZE, 1, /* maxsize, nsegment */
566 AW_MMC_DMA_DESC_SIZE, /* maxsegsize */
567 0, /* flags */
568 NULL, NULL, /* lock, lockarg*/
569 &sc->aw_dma_tag);
570 if (error)
571 return (error);
572
573 error = bus_dmamem_alloc(sc->aw_dma_tag, &sc->aw_dma_desc,
574 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO,
575 &sc->aw_dma_map);
576 if (error)
577 return (error);
578
579 error = bus_dmamap_load(sc->aw_dma_tag,
580 sc->aw_dma_map,
581 sc->aw_dma_desc, AW_MMC_DMA_DESC_SIZE,
582 aw_dma_desc_cb, sc, 0);
583 if (error)
584 return (error);
585 if (sc->aw_dma_map_err)
586 return (sc->aw_dma_map_err);
587
588 /* Create the DMA map for data transfers. */
589 error = bus_dma_tag_create(
590 bus_get_dma_tag(sc->aw_dev), /* parent */
591 AW_MMC_DMA_ALIGN, 0, /* align, boundary */
592 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
593 BUS_SPACE_MAXADDR, /* highaddr */
594 NULL, NULL, /* filter, filterarg*/
595 sc->aw_mmc_conf->dma_xferlen *
596 AW_MMC_DMA_SEGS, AW_MMC_DMA_SEGS, /* maxsize, nsegments */
597 sc->aw_mmc_conf->dma_xferlen, /* maxsegsize */
598 BUS_DMA_ALLOCNOW, /* flags */
599 NULL, NULL, /* lock, lockarg*/
600 &sc->aw_dma_buf_tag);
601 if (error)
602 return (error);
603 error = bus_dmamap_create(sc->aw_dma_buf_tag, 0,
604 &sc->aw_dma_buf_map);
605 if (error)
606 return (error);
607
608 return (0);
609 }
610
611 static void
aw_mmc_teardown_dma(struct aw_mmc_softc * sc)612 aw_mmc_teardown_dma(struct aw_mmc_softc *sc)
613 {
614
615 bus_dmamap_unload(sc->aw_dma_tag, sc->aw_dma_map);
616 bus_dmamem_free(sc->aw_dma_tag, sc->aw_dma_desc, sc->aw_dma_map);
617 if (bus_dma_tag_destroy(sc->aw_dma_tag) != 0)
618 device_printf(sc->aw_dev, "Cannot destroy the dma tag\n");
619
620 bus_dmamap_unload(sc->aw_dma_buf_tag, sc->aw_dma_buf_map);
621 bus_dmamap_destroy(sc->aw_dma_buf_tag, sc->aw_dma_buf_map);
622 if (bus_dma_tag_destroy(sc->aw_dma_buf_tag) != 0)
623 device_printf(sc->aw_dev, "Cannot destroy the dma buf tag\n");
624 }
625
626 static void
aw_dma_cb(void * arg,bus_dma_segment_t * segs,int nsegs,int err)627 aw_dma_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int err)
628 {
629 int i;
630 struct aw_mmc_dma_desc *dma_desc;
631 struct aw_mmc_softc *sc;
632
633 sc = (struct aw_mmc_softc *)arg;
634 sc->aw_dma_map_err = err;
635
636 if (err)
637 return;
638
639 dma_desc = sc->aw_dma_desc;
640 for (i = 0; i < nsegs; i++) {
641 if ((segs[i].ds_len == sc->aw_mmc_conf->dma_xferlen) &&
642 !sc->aw_mmc_conf->zero_is_skip)
643 dma_desc[i].buf_size = 0; /* Size of 0 indicate max len */
644 else
645 dma_desc[i].buf_size = segs[i].ds_len;
646 dma_desc[i].buf_addr = segs[i].ds_addr >>
647 sc->aw_mmc_conf->dma_desc_shift;
648 dma_desc[i].config = AW_MMC_DMA_CONFIG_CH |
649 AW_MMC_DMA_CONFIG_OWN | AW_MMC_DMA_CONFIG_DIC;
650 dma_desc[i].next = (sc->aw_dma_desc_phys +
651 (i + 1) * sizeof(struct aw_mmc_dma_desc)) >>
652 sc->aw_mmc_conf->dma_desc_shift;
653 }
654
655 dma_desc[0].config |= AW_MMC_DMA_CONFIG_FD;
656 dma_desc[nsegs - 1].config |= AW_MMC_DMA_CONFIG_LD |
657 AW_MMC_DMA_CONFIG_ER;
658 dma_desc[nsegs - 1].config &= ~AW_MMC_DMA_CONFIG_DIC;
659 dma_desc[nsegs - 1].next = 0;
660 }
661
662 static int
aw_mmc_prepare_dma(struct aw_mmc_softc * sc)663 aw_mmc_prepare_dma(struct aw_mmc_softc *sc)
664 {
665 bus_dmasync_op_t sync_op;
666 int error;
667 struct mmc_command *cmd;
668 uint32_t val;
669
670 #ifdef MMCCAM
671 cmd = &sc->ccb->mmcio.cmd;
672 #else
673 cmd = sc->aw_req->cmd;
674 #endif
675 if (cmd->data->len > (sc->aw_mmc_conf->dma_xferlen * AW_MMC_DMA_SEGS))
676 return (EFBIG);
677 error = bus_dmamap_load(sc->aw_dma_buf_tag, sc->aw_dma_buf_map,
678 cmd->data->data, cmd->data->len, aw_dma_cb, sc, 0);
679 if (error)
680 return (error);
681 if (sc->aw_dma_map_err)
682 return (sc->aw_dma_map_err);
683
684 if (cmd->data->flags & MMC_DATA_WRITE)
685 sync_op = BUS_DMASYNC_PREWRITE;
686 else
687 sync_op = BUS_DMASYNC_PREREAD;
688 bus_dmamap_sync(sc->aw_dma_buf_tag, sc->aw_dma_buf_map, sync_op);
689 bus_dmamap_sync(sc->aw_dma_tag, sc->aw_dma_map, BUS_DMASYNC_PREWRITE);
690
691 /* Enable DMA */
692 val = AW_MMC_READ_4(sc, AW_MMC_GCTL);
693 val &= ~AW_MMC_GCTL_FIFO_AC_MOD;
694 val |= AW_MMC_GCTL_DMA_ENB;
695 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val);
696
697 /* Reset DMA */
698 val |= AW_MMC_GCTL_DMA_RST;
699 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val);
700
701 AW_MMC_WRITE_4(sc, AW_MMC_DMAC, AW_MMC_DMAC_IDMAC_SOFT_RST);
702 AW_MMC_WRITE_4(sc, AW_MMC_DMAC,
703 AW_MMC_DMAC_IDMAC_IDMA_ON | AW_MMC_DMAC_IDMAC_FIX_BURST);
704
705 /* Enable RX or TX DMA interrupt */
706 val = AW_MMC_READ_4(sc, AW_MMC_IDIE);
707 if (cmd->data->flags & MMC_DATA_WRITE)
708 val |= AW_MMC_IDST_TX_INT;
709 else
710 val |= AW_MMC_IDST_RX_INT;
711 AW_MMC_WRITE_4(sc, AW_MMC_IDIE, val);
712
713 /* Set DMA descritptor list address */
714 AW_MMC_WRITE_4(sc, AW_MMC_DLBA, sc->aw_dma_desc_phys >>
715 sc->aw_mmc_conf->dma_desc_shift);
716
717 /* FIFO trigger level */
718 AW_MMC_WRITE_4(sc, AW_MMC_FWLR, AW_MMC_DMA_FTRGLEVEL);
719
720 return (0);
721 }
722
723 static int
aw_mmc_reset(struct aw_mmc_softc * sc)724 aw_mmc_reset(struct aw_mmc_softc *sc)
725 {
726 uint32_t reg;
727 int timeout;
728
729 reg = AW_MMC_READ_4(sc, AW_MMC_GCTL);
730 reg |= AW_MMC_GCTL_RESET;
731 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg);
732 timeout = AW_MMC_RESET_RETRY;
733 while (--timeout > 0) {
734 if ((AW_MMC_READ_4(sc, AW_MMC_GCTL) & AW_MMC_GCTL_RESET) == 0)
735 break;
736 DELAY(100);
737 }
738 if (timeout == 0)
739 return (ETIMEDOUT);
740
741 /*
742 * Assert hardware reset and have the card move to the pre-idle state.
743 * This is needed on H616 to get the card into a functional state.
744 */
745 AW_MMC_WRITE_4(sc, AW_MMC_HWRST, AW_MMC_HWRST_ASSERT);
746 AW_MMC_WRITE_4(sc, AW_MMC_HWRST, AW_MMC_HWRST_DEASSERT);
747
748 return (0);
749 }
750
751 static int
aw_mmc_init(struct aw_mmc_softc * sc)752 aw_mmc_init(struct aw_mmc_softc *sc)
753 {
754 uint32_t reg;
755 int ret;
756
757 ret = aw_mmc_reset(sc);
758 if (ret != 0)
759 return (ret);
760
761 /* Set the timeout. */
762 AW_MMC_WRITE_4(sc, AW_MMC_TMOR,
763 AW_MMC_TMOR_DTO_LMT_SHIFT(AW_MMC_TMOR_DTO_LMT_MASK) |
764 AW_MMC_TMOR_RTO_LMT_SHIFT(AW_MMC_TMOR_RTO_LMT_MASK));
765
766 /* Unmask interrupts. */
767 AW_MMC_WRITE_4(sc, AW_MMC_IMKR, 0);
768
769 /* Clear pending interrupts. */
770 AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff);
771
772 /* Debug register, undocumented */
773 AW_MMC_WRITE_4(sc, AW_MMC_DBGC, 0xdeb);
774
775 /* Function select register */
776 AW_MMC_WRITE_4(sc, AW_MMC_FUNS, 0xceaa0000);
777
778 AW_MMC_WRITE_4(sc, AW_MMC_IDST, 0xffffffff);
779
780 /* Enable interrupts and disable AHB access. */
781 reg = AW_MMC_READ_4(sc, AW_MMC_GCTL);
782 reg |= AW_MMC_GCTL_INT_ENB;
783 reg &= ~AW_MMC_GCTL_FIFO_AC_MOD;
784 reg &= ~AW_MMC_GCTL_WAIT_MEM_ACCESS;
785 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg);
786
787 return (0);
788 }
789
790 static void
aw_mmc_req_done(struct aw_mmc_softc * sc)791 aw_mmc_req_done(struct aw_mmc_softc *sc)
792 {
793 struct mmc_command *cmd;
794 #ifdef MMCCAM
795 union ccb *ccb;
796 #else
797 struct mmc_request *req;
798 #endif
799 uint32_t val, mask;
800 int retry;
801
802 #ifdef MMCCAM
803 ccb = sc->ccb;
804 cmd = &ccb->mmcio.cmd;
805 #else
806 cmd = sc->aw_req->cmd;
807 #endif
808 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_CMD)) {
809 device_printf(sc->aw_dev, "%s: cmd %d err %d\n", __func__, cmd->opcode, cmd->error);
810 }
811 if (cmd->error != MMC_ERR_NONE) {
812 /* Reset the FIFO and DMA engines. */
813 mask = AW_MMC_GCTL_FIFO_RST | AW_MMC_GCTL_DMA_RST;
814 val = AW_MMC_READ_4(sc, AW_MMC_GCTL);
815 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val | mask);
816
817 retry = AW_MMC_RESET_RETRY;
818 while (--retry > 0) {
819 if ((AW_MMC_READ_4(sc, AW_MMC_GCTL) &
820 AW_MMC_GCTL_RESET) == 0)
821 break;
822 DELAY(100);
823 }
824 if (retry == 0)
825 device_printf(sc->aw_dev,
826 "timeout resetting DMA/FIFO\n");
827 aw_mmc_update_clock(sc, 1);
828 }
829
830 if (!dumping)
831 callout_stop(&sc->aw_timeoutc);
832 sc->aw_intr = 0;
833 sc->aw_resid = 0;
834 sc->aw_dma_map_err = 0;
835 sc->aw_intr_wait = 0;
836 #ifdef MMCCAM
837 sc->ccb = NULL;
838 ccb->ccb_h.status =
839 (ccb->mmcio.cmd.error == 0 ? CAM_REQ_CMP : CAM_REQ_CMP_ERR);
840 xpt_done(ccb);
841 #else
842 req = sc->aw_req;
843 sc->aw_req = NULL;
844 req->done(req);
845 #endif
846 }
847
848 static void
aw_mmc_req_ok(struct aw_mmc_softc * sc)849 aw_mmc_req_ok(struct aw_mmc_softc *sc)
850 {
851 int timeout;
852 struct mmc_command *cmd;
853 uint32_t status;
854
855 timeout = 1000;
856 while (--timeout > 0) {
857 status = AW_MMC_READ_4(sc, AW_MMC_STAR);
858 if ((status & AW_MMC_STAR_CARD_BUSY) == 0)
859 break;
860 DELAY(1000);
861 }
862 #ifdef MMCCAM
863 cmd = &sc->ccb->mmcio.cmd;
864 #else
865 cmd = sc->aw_req->cmd;
866 #endif
867 if (timeout == 0) {
868 cmd->error = MMC_ERR_FAILED;
869 aw_mmc_req_done(sc);
870 return;
871 }
872 if (cmd->flags & MMC_RSP_PRESENT) {
873 if (cmd->flags & MMC_RSP_136) {
874 cmd->resp[0] = AW_MMC_READ_4(sc, AW_MMC_RESP3);
875 cmd->resp[1] = AW_MMC_READ_4(sc, AW_MMC_RESP2);
876 cmd->resp[2] = AW_MMC_READ_4(sc, AW_MMC_RESP1);
877 cmd->resp[3] = AW_MMC_READ_4(sc, AW_MMC_RESP0);
878 } else
879 cmd->resp[0] = AW_MMC_READ_4(sc, AW_MMC_RESP0);
880 }
881 /* All data has been transferred ? */
882 if (cmd->data != NULL && (sc->aw_resid << 2) < cmd->data->len)
883 cmd->error = MMC_ERR_FAILED;
884 aw_mmc_req_done(sc);
885 }
886
887 static inline void
set_mmc_error(struct aw_mmc_softc * sc,int error_code)888 set_mmc_error(struct aw_mmc_softc *sc, int error_code)
889 {
890 #ifdef MMCCAM
891 sc->ccb->mmcio.cmd.error = error_code;
892 #else
893 sc->aw_req->cmd->error = error_code;
894 #endif
895 }
896
897 static void
aw_mmc_timeout(void * arg)898 aw_mmc_timeout(void *arg)
899 {
900 struct aw_mmc_softc *sc;
901
902 sc = (struct aw_mmc_softc *)arg;
903 #ifdef MMCCAM
904 if (sc->ccb != NULL) {
905 #else
906 if (sc->aw_req != NULL) {
907 #endif
908 device_printf(sc->aw_dev, "controller timeout\n");
909 set_mmc_error(sc, MMC_ERR_TIMEOUT);
910 aw_mmc_req_done(sc);
911 } else
912 device_printf(sc->aw_dev,
913 "Spurious timeout - no active request\n");
914 }
915
916 static void
917 aw_mmc_print_error(uint32_t err)
918 {
919 if(err & AW_MMC_INT_RESP_ERR)
920 printf("AW_MMC_INT_RESP_ERR ");
921 if (err & AW_MMC_INT_RESP_CRC_ERR)
922 printf("AW_MMC_INT_RESP_CRC_ERR ");
923 if (err & AW_MMC_INT_DATA_CRC_ERR)
924 printf("AW_MMC_INT_DATA_CRC_ERR ");
925 if (err & AW_MMC_INT_RESP_TIMEOUT)
926 printf("AW_MMC_INT_RESP_TIMEOUT ");
927 if (err & AW_MMC_INT_FIFO_RUN_ERR)
928 printf("AW_MMC_INT_FIFO_RUN_ERR ");
929 if (err & AW_MMC_INT_CMD_BUSY)
930 printf("AW_MMC_INT_CMD_BUSY ");
931 if (err & AW_MMC_INT_DATA_START_ERR)
932 printf("AW_MMC_INT_DATA_START_ERR ");
933 if (err & AW_MMC_INT_DATA_END_BIT_ERR)
934 printf("AW_MMC_INT_DATA_END_BIT_ERR");
935 printf("\n");
936 }
937
938 static void
939 aw_mmc_intr(void *arg)
940 {
941 bus_dmasync_op_t sync_op;
942 struct aw_mmc_softc *sc;
943 struct mmc_data *data;
944 uint32_t idst, imask, rint;
945
946 sc = (struct aw_mmc_softc *)arg;
947 AW_MMC_LOCK(sc);
948 rint = AW_MMC_READ_4(sc, AW_MMC_RISR);
949 idst = AW_MMC_READ_4(sc, AW_MMC_IDST);
950 imask = AW_MMC_READ_4(sc, AW_MMC_IMKR);
951 if (idst == 0 && imask == 0 && rint == 0) {
952 AW_MMC_UNLOCK(sc);
953 return;
954 }
955 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_INT)) {
956 device_printf(sc->aw_dev, "idst: %#x, imask: %#x, rint: %#x\n",
957 idst, imask, rint);
958 }
959 #ifdef MMCCAM
960 if (sc->ccb == NULL) {
961 #else
962 if (sc->aw_req == NULL) {
963 #endif
964 device_printf(sc->aw_dev,
965 "Spurious interrupt - no active request, rint: 0x%08X\n",
966 rint);
967 aw_mmc_print_error(rint);
968 goto end;
969 }
970 if (rint & AW_MMC_INT_ERR_BIT) {
971 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_INT)) {
972 device_printf(sc->aw_dev, "error rint: 0x%08X\n", rint);
973 aw_mmc_print_error(rint);
974 }
975 if (rint & AW_MMC_INT_RESP_TIMEOUT)
976 set_mmc_error(sc, MMC_ERR_TIMEOUT);
977 else
978 set_mmc_error(sc, MMC_ERR_FAILED);
979 aw_mmc_req_done(sc);
980 goto end;
981 }
982 if (idst & AW_MMC_IDST_ERROR) {
983 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_INT))
984 device_printf(sc->aw_dev, "error idst: 0x%08x\n", idst);
985 set_mmc_error(sc, MMC_ERR_FAILED);
986 aw_mmc_req_done(sc);
987 goto end;
988 }
989
990 sc->aw_intr |= rint;
991 #ifdef MMCCAM
992 data = sc->ccb->mmcio.cmd.data;
993 #else
994 data = sc->aw_req->cmd->data;
995 #endif
996 if (data != NULL && (idst & AW_MMC_IDST_COMPLETE) != 0) {
997 if (data->flags & MMC_DATA_WRITE)
998 sync_op = BUS_DMASYNC_POSTWRITE;
999 else
1000 sync_op = BUS_DMASYNC_POSTREAD;
1001 bus_dmamap_sync(sc->aw_dma_buf_tag, sc->aw_dma_buf_map,
1002 sync_op);
1003 bus_dmamap_sync(sc->aw_dma_tag, sc->aw_dma_map,
1004 BUS_DMASYNC_POSTWRITE);
1005 bus_dmamap_unload(sc->aw_dma_buf_tag, sc->aw_dma_buf_map);
1006 sc->aw_resid = data->len >> 2;
1007 }
1008 if ((sc->aw_intr & sc->aw_intr_wait) == sc->aw_intr_wait)
1009 aw_mmc_req_ok(sc);
1010
1011 end:
1012 AW_MMC_WRITE_4(sc, AW_MMC_IDST, idst);
1013 AW_MMC_WRITE_4(sc, AW_MMC_RISR, rint);
1014 AW_MMC_UNLOCK(sc);
1015 }
1016
1017 static int
1018 aw_mmc_request(device_t bus, device_t child, struct mmc_request *req)
1019 {
1020 int blksz;
1021 struct aw_mmc_softc *sc;
1022 struct mmc_command *cmd;
1023 uint32_t cmdreg, imask;
1024 int err;
1025
1026 sc = device_get_softc(bus);
1027
1028 AW_MMC_LOCK(sc);
1029 #ifdef MMCCAM
1030 KASSERT(req == NULL, ("req should be NULL in MMCCAM case!"));
1031 /*
1032 * For MMCCAM, sc->ccb has been NULL-checked and populated
1033 * by aw_mmc_cam_request() already.
1034 */
1035 cmd = &sc->ccb->mmcio.cmd;
1036 #else
1037 if (sc->aw_req) {
1038 AW_MMC_UNLOCK(sc);
1039 return (EBUSY);
1040 }
1041 sc->aw_req = req;
1042 cmd = req->cmd;
1043
1044 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_CMD)) {
1045 device_printf(sc->aw_dev, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n",
1046 cmd->opcode, cmd->arg, cmd->flags,
1047 cmd->data != NULL ? (unsigned int)cmd->data->len : 0,
1048 cmd->data != NULL ? cmd->data->flags: 0);
1049 }
1050 #endif
1051 cmdreg = AW_MMC_CMDR_LOAD;
1052 imask = AW_MMC_INT_ERR_BIT;
1053 sc->aw_intr_wait = 0;
1054 sc->aw_intr = 0;
1055 sc->aw_resid = 0;
1056 cmd->error = MMC_ERR_NONE;
1057
1058 if (cmd->opcode == MMC_GO_IDLE_STATE)
1059 cmdreg |= AW_MMC_CMDR_SEND_INIT_SEQ;
1060
1061 if (cmd->flags & MMC_RSP_PRESENT)
1062 cmdreg |= AW_MMC_CMDR_RESP_RCV;
1063 if (cmd->flags & MMC_RSP_136)
1064 cmdreg |= AW_MMC_CMDR_LONG_RESP;
1065 if (cmd->flags & MMC_RSP_CRC)
1066 cmdreg |= AW_MMC_CMDR_CHK_RESP_CRC;
1067
1068 if (cmd->data) {
1069 cmdreg |= AW_MMC_CMDR_DATA_TRANS | AW_MMC_CMDR_WAIT_PRE_OVER;
1070
1071 if (cmd->data->flags & MMC_DATA_MULTI) {
1072 cmdreg |= AW_MMC_CMDR_STOP_CMD_FLAG;
1073 imask |= AW_MMC_INT_AUTO_STOP_DONE;
1074 sc->aw_intr_wait |= AW_MMC_INT_AUTO_STOP_DONE;
1075 } else {
1076 sc->aw_intr_wait |= AW_MMC_INT_DATA_OVER;
1077 imask |= AW_MMC_INT_DATA_OVER;
1078 }
1079 if (cmd->data->flags & MMC_DATA_WRITE)
1080 cmdreg |= AW_MMC_CMDR_DIR_WRITE;
1081 #ifdef MMCCAM
1082 if (cmd->data->flags & MMC_DATA_BLOCK_SIZE) {
1083 AW_MMC_WRITE_4(sc, AW_MMC_BKSR, cmd->data->block_size);
1084 AW_MMC_WRITE_4(sc, AW_MMC_BYCR, cmd->data->len);
1085 } else
1086 #endif
1087 {
1088 blksz = min(cmd->data->len, MMC_SECTOR_SIZE);
1089 AW_MMC_WRITE_4(sc, AW_MMC_BKSR, blksz);
1090 AW_MMC_WRITE_4(sc, AW_MMC_BYCR, cmd->data->len);
1091 }
1092 } else {
1093 imask |= AW_MMC_INT_CMD_DONE;
1094 }
1095
1096 /* Enable the interrupts we are interested in */
1097 AW_MMC_WRITE_4(sc, AW_MMC_IMKR, imask);
1098 AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff);
1099
1100 /* Enable auto stop if needed */
1101 AW_MMC_WRITE_4(sc, AW_MMC_A12A,
1102 cmdreg & AW_MMC_CMDR_STOP_CMD_FLAG ? 0 : 0xffff);
1103
1104 /* Write the command argument */
1105 AW_MMC_WRITE_4(sc, AW_MMC_CAGR, cmd->arg);
1106
1107 /*
1108 * If we don't have data start the request
1109 * if we do prepare the dma request and start the request
1110 */
1111 if (cmd->data == NULL) {
1112 AW_MMC_WRITE_4(sc, AW_MMC_CMDR, cmdreg | cmd->opcode);
1113 } else {
1114 err = aw_mmc_prepare_dma(sc);
1115 if (err != 0)
1116 device_printf(sc->aw_dev, "prepare_dma failed: %d\n", err);
1117
1118 AW_MMC_WRITE_4(sc, AW_MMC_CMDR, cmdreg | cmd->opcode);
1119 }
1120
1121 if (!dumping) {
1122 callout_reset(&sc->aw_timeoutc, sc->aw_timeout * hz,
1123 aw_mmc_timeout, sc);
1124 }
1125 AW_MMC_UNLOCK(sc);
1126
1127 return (0);
1128 }
1129
1130 static int
1131 aw_mmc_read_ivar(device_t bus, device_t child, int which,
1132 uintptr_t *result)
1133 {
1134 struct aw_mmc_softc *sc;
1135
1136 sc = device_get_softc(bus);
1137 switch (which) {
1138 default:
1139 return (EINVAL);
1140 case MMCBR_IVAR_BUS_MODE:
1141 *(int *)result = sc->aw_host.ios.bus_mode;
1142 break;
1143 case MMCBR_IVAR_BUS_WIDTH:
1144 *(int *)result = sc->aw_host.ios.bus_width;
1145 break;
1146 case MMCBR_IVAR_CHIP_SELECT:
1147 *(int *)result = sc->aw_host.ios.chip_select;
1148 break;
1149 case MMCBR_IVAR_CLOCK:
1150 *(int *)result = sc->aw_host.ios.clock;
1151 break;
1152 case MMCBR_IVAR_F_MIN:
1153 *(int *)result = sc->aw_host.f_min;
1154 break;
1155 case MMCBR_IVAR_F_MAX:
1156 *(int *)result = sc->aw_host.f_max;
1157 break;
1158 case MMCBR_IVAR_HOST_OCR:
1159 *(int *)result = sc->aw_host.host_ocr;
1160 break;
1161 case MMCBR_IVAR_MODE:
1162 *(int *)result = sc->aw_host.mode;
1163 break;
1164 case MMCBR_IVAR_OCR:
1165 *(int *)result = sc->aw_host.ocr;
1166 break;
1167 case MMCBR_IVAR_POWER_MODE:
1168 *(int *)result = sc->aw_host.ios.power_mode;
1169 break;
1170 case MMCBR_IVAR_VDD:
1171 *(int *)result = sc->aw_host.ios.vdd;
1172 break;
1173 case MMCBR_IVAR_VCCQ:
1174 *(int *)result = sc->aw_host.ios.vccq;
1175 break;
1176 case MMCBR_IVAR_CAPS:
1177 *(int *)result = sc->aw_host.caps;
1178 break;
1179 case MMCBR_IVAR_TIMING:
1180 *(int *)result = sc->aw_host.ios.timing;
1181 break;
1182 case MMCBR_IVAR_MAX_DATA:
1183 *(int *)result = (sc->aw_mmc_conf->dma_xferlen *
1184 AW_MMC_DMA_SEGS) / MMC_SECTOR_SIZE;
1185 break;
1186 case MMCBR_IVAR_RETUNE_REQ:
1187 *(int *)result = retune_req_none;
1188 break;
1189 }
1190
1191 return (0);
1192 }
1193
1194 static int
1195 aw_mmc_write_ivar(device_t bus, device_t child, int which,
1196 uintptr_t value)
1197 {
1198 struct aw_mmc_softc *sc;
1199
1200 sc = device_get_softc(bus);
1201 switch (which) {
1202 default:
1203 return (EINVAL);
1204 case MMCBR_IVAR_BUS_MODE:
1205 sc->aw_host.ios.bus_mode = value;
1206 break;
1207 case MMCBR_IVAR_BUS_WIDTH:
1208 sc->aw_host.ios.bus_width = value;
1209 break;
1210 case MMCBR_IVAR_CHIP_SELECT:
1211 sc->aw_host.ios.chip_select = value;
1212 break;
1213 case MMCBR_IVAR_CLOCK:
1214 sc->aw_host.ios.clock = value;
1215 break;
1216 case MMCBR_IVAR_MODE:
1217 sc->aw_host.mode = value;
1218 break;
1219 case MMCBR_IVAR_OCR:
1220 sc->aw_host.ocr = value;
1221 break;
1222 case MMCBR_IVAR_POWER_MODE:
1223 sc->aw_host.ios.power_mode = value;
1224 break;
1225 case MMCBR_IVAR_VDD:
1226 sc->aw_host.ios.vdd = value;
1227 break;
1228 case MMCBR_IVAR_VCCQ:
1229 sc->aw_host.ios.vccq = value;
1230 break;
1231 case MMCBR_IVAR_TIMING:
1232 sc->aw_host.ios.timing = value;
1233 break;
1234 /* These are read-only */
1235 case MMCBR_IVAR_CAPS:
1236 case MMCBR_IVAR_HOST_OCR:
1237 case MMCBR_IVAR_F_MIN:
1238 case MMCBR_IVAR_F_MAX:
1239 case MMCBR_IVAR_MAX_DATA:
1240 return (EINVAL);
1241 }
1242
1243 return (0);
1244 }
1245
1246 static int
1247 aw_mmc_update_clock(struct aw_mmc_softc *sc, uint32_t clkon)
1248 {
1249 uint32_t reg;
1250 int retry;
1251
1252 reg = AW_MMC_READ_4(sc, AW_MMC_CKCR);
1253 reg &= ~(AW_MMC_CKCR_ENB | AW_MMC_CKCR_LOW_POWER |
1254 AW_MMC_CKCR_MASK_DATA0);
1255
1256 if (clkon)
1257 reg |= AW_MMC_CKCR_ENB;
1258 if (sc->aw_mmc_conf->mask_data0)
1259 reg |= AW_MMC_CKCR_MASK_DATA0;
1260
1261 AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg);
1262
1263 reg = AW_MMC_CMDR_LOAD | AW_MMC_CMDR_PRG_CLK |
1264 AW_MMC_CMDR_WAIT_PRE_OVER;
1265 AW_MMC_WRITE_4(sc, AW_MMC_CMDR, reg);
1266 retry = 0xfffff;
1267
1268 while (reg & AW_MMC_CMDR_LOAD && --retry > 0) {
1269 reg = AW_MMC_READ_4(sc, AW_MMC_CMDR);
1270 DELAY(10);
1271 }
1272 AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff);
1273
1274 if (reg & AW_MMC_CMDR_LOAD) {
1275 device_printf(sc->aw_dev, "timeout updating clock\n");
1276 return (ETIMEDOUT);
1277 }
1278
1279 if (sc->aw_mmc_conf->mask_data0) {
1280 reg = AW_MMC_READ_4(sc, AW_MMC_CKCR);
1281 reg &= ~AW_MMC_CKCR_MASK_DATA0;
1282 AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg);
1283 }
1284
1285 return (0);
1286 }
1287
1288 #ifndef MMCCAM
1289 static int
1290 aw_mmc_switch_vccq(device_t bus, device_t child)
1291 {
1292 struct aw_mmc_softc *sc;
1293 int uvolt, err;
1294
1295 sc = device_get_softc(bus);
1296
1297 if (sc->mmc_helper.vqmmc_supply == NULL)
1298 return EOPNOTSUPP;
1299
1300 switch (sc->aw_host.ios.vccq) {
1301 case vccq_180:
1302 uvolt = 1800000;
1303 break;
1304 case vccq_330:
1305 uvolt = 3300000;
1306 break;
1307 default:
1308 return EINVAL;
1309 }
1310
1311 err = regulator_set_voltage(sc->mmc_helper.vqmmc_supply, uvolt, uvolt);
1312 if (err != 0) {
1313 device_printf(sc->aw_dev,
1314 "Cannot set vqmmc to %d<->%d\n",
1315 uvolt,
1316 uvolt);
1317 return (err);
1318 }
1319
1320 return (0);
1321 }
1322 #endif
1323
1324 static int
1325 aw_mmc_update_ios(device_t bus, device_t child)
1326 {
1327 int error;
1328 struct aw_mmc_softc *sc;
1329 struct mmc_ios *ios;
1330 unsigned int clock;
1331 uint32_t reg, div = 1;
1332 int reg_status;
1333 int rv;
1334
1335 sc = device_get_softc(bus);
1336
1337 ios = &sc->aw_host.ios;
1338
1339 /* Set the bus width. */
1340 switch (ios->bus_width) {
1341 case bus_width_1:
1342 AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR1);
1343 break;
1344 case bus_width_4:
1345 AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR4);
1346 break;
1347 case bus_width_8:
1348 AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR8);
1349 break;
1350 }
1351
1352 switch (ios->power_mode) {
1353 case power_on:
1354 break;
1355 case power_off:
1356 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_CARD))
1357 device_printf(sc->aw_dev, "Powering down sd/mmc\n");
1358
1359 if (sc->mmc_helper.vmmc_supply) {
1360 rv = regulator_status(sc->mmc_helper.vmmc_supply, ®_status);
1361 if (rv == 0 && reg_status == REGULATOR_STATUS_ENABLED)
1362 regulator_disable(sc->mmc_helper.vmmc_supply);
1363 }
1364 if (sc->mmc_helper.vqmmc_supply) {
1365 rv = regulator_status(sc->mmc_helper.vqmmc_supply, ®_status);
1366 if (rv == 0 && reg_status == REGULATOR_STATUS_ENABLED)
1367 regulator_disable(sc->mmc_helper.vqmmc_supply);
1368 }
1369
1370 if (sc->mmc_helper.mmc_pwrseq)
1371 MMC_PWRSEQ_SET_POWER(sc->mmc_helper.mmc_pwrseq, false);
1372
1373 aw_mmc_reset(sc);
1374 break;
1375 case power_up:
1376 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_CARD))
1377 device_printf(sc->aw_dev, "Powering up sd/mmc\n");
1378
1379 if (sc->mmc_helper.vmmc_supply) {
1380 rv = regulator_status(sc->mmc_helper.vmmc_supply, ®_status);
1381 if (rv == 0 && reg_status != REGULATOR_STATUS_ENABLED)
1382 regulator_enable(sc->mmc_helper.vmmc_supply);
1383 }
1384 if (sc->mmc_helper.vqmmc_supply) {
1385 rv = regulator_status(sc->mmc_helper.vqmmc_supply, ®_status);
1386 if (rv == 0 && reg_status != REGULATOR_STATUS_ENABLED)
1387 regulator_enable(sc->mmc_helper.vqmmc_supply);
1388 }
1389
1390 if (sc->mmc_helper.mmc_pwrseq)
1391 MMC_PWRSEQ_SET_POWER(sc->mmc_helper.mmc_pwrseq, true);
1392 aw_mmc_init(sc);
1393 break;
1394 };
1395
1396 /* Enable ddr mode if needed */
1397 reg = AW_MMC_READ_4(sc, AW_MMC_GCTL);
1398 if (ios->timing == bus_timing_uhs_ddr50 ||
1399 ios->timing == bus_timing_mmc_ddr52)
1400 reg |= AW_MMC_GCTL_DDR_MOD_SEL;
1401 else
1402 reg &= ~AW_MMC_GCTL_DDR_MOD_SEL;
1403 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg);
1404
1405 if (ios->clock && ios->clock != sc->aw_clock) {
1406 sc->aw_clock = clock = ios->clock;
1407
1408 /* Disable clock */
1409 error = aw_mmc_update_clock(sc, 0);
1410 if (error != 0)
1411 return (error);
1412
1413 if (ios->timing == bus_timing_mmc_ddr52 &&
1414 (sc->aw_mmc_conf->new_timing ||
1415 ios->bus_width == bus_width_8)) {
1416 div = 2;
1417 clock <<= 1;
1418 }
1419
1420 /* Reset the divider. */
1421 reg = AW_MMC_READ_4(sc, AW_MMC_CKCR);
1422 reg &= ~AW_MMC_CKCR_DIV;
1423 reg |= div - 1;
1424 AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg);
1425
1426 /* New timing mode if needed */
1427 if (sc->aw_mmc_conf->new_timing) {
1428 reg = AW_MMC_READ_4(sc, AW_MMC_NTSR);
1429 reg |= AW_MMC_NTSR_MODE_SELECT;
1430 AW_MMC_WRITE_4(sc, AW_MMC_NTSR, reg);
1431 }
1432
1433 /* Set the MMC clock. */
1434 error = clk_disable(sc->aw_clk_mmc);
1435 if (error != 0 && bootverbose)
1436 device_printf(sc->aw_dev,
1437 "failed to disable mmc clock: %d\n", error);
1438 error = clk_set_freq(sc->aw_clk_mmc, clock,
1439 CLK_SET_ROUND_DOWN);
1440 if (error != 0) {
1441 device_printf(sc->aw_dev,
1442 "failed to set frequency to %u Hz: %d\n",
1443 clock, error);
1444 return (error);
1445 }
1446 error = clk_enable(sc->aw_clk_mmc);
1447 if (error != 0 && bootverbose)
1448 device_printf(sc->aw_dev,
1449 "failed to re-enable mmc clock: %d\n", error);
1450
1451 if (sc->aw_mmc_conf->can_calibrate)
1452 AW_MMC_WRITE_4(sc, AW_MMC_SAMP_DL, AW_MMC_SAMP_DL_SW_EN);
1453
1454 /* Enable clock. */
1455 error = aw_mmc_update_clock(sc, 1);
1456 if (error != 0)
1457 return (error);
1458 }
1459
1460 return (0);
1461 }
1462
1463 #ifndef MMCCAM
1464 static int
1465 aw_mmc_get_ro(device_t bus, device_t child)
1466 {
1467 struct aw_mmc_softc *sc;
1468
1469 sc = device_get_softc(bus);
1470
1471 return (mmc_fdt_gpio_get_readonly(&sc->mmc_helper));
1472 }
1473
1474 static int
1475 aw_mmc_acquire_host(device_t bus, device_t child)
1476 {
1477 struct aw_mmc_softc *sc;
1478 int error;
1479
1480 sc = device_get_softc(bus);
1481 AW_MMC_LOCK(sc);
1482 while (sc->aw_bus_busy) {
1483 error = msleep(sc, &sc->aw_mtx, PCATCH, "mmchw", 0);
1484 if (error != 0) {
1485 AW_MMC_UNLOCK(sc);
1486 return (error);
1487 }
1488 }
1489 sc->aw_bus_busy++;
1490 AW_MMC_UNLOCK(sc);
1491
1492 return (0);
1493 }
1494
1495 static int
1496 aw_mmc_release_host(device_t bus, device_t child)
1497 {
1498 struct aw_mmc_softc *sc;
1499
1500 sc = device_get_softc(bus);
1501 AW_MMC_LOCK(sc);
1502 sc->aw_bus_busy--;
1503 wakeup(sc);
1504 AW_MMC_UNLOCK(sc);
1505
1506 return (0);
1507 }
1508 #endif
1509
1510 static device_method_t aw_mmc_methods[] = {
1511 /* Device interface */
1512 DEVMETHOD(device_probe, aw_mmc_probe),
1513 DEVMETHOD(device_attach, aw_mmc_attach),
1514 DEVMETHOD(device_detach, aw_mmc_detach),
1515
1516 /* Bus interface */
1517 DEVMETHOD(bus_read_ivar, aw_mmc_read_ivar),
1518 DEVMETHOD(bus_write_ivar, aw_mmc_write_ivar),
1519 DEVMETHOD(bus_add_child, bus_generic_add_child),
1520
1521 #ifndef MMCCAM
1522 /* MMC bridge interface */
1523 DEVMETHOD(mmcbr_update_ios, aw_mmc_update_ios),
1524 DEVMETHOD(mmcbr_request, aw_mmc_request),
1525 DEVMETHOD(mmcbr_get_ro, aw_mmc_get_ro),
1526 DEVMETHOD(mmcbr_switch_vccq, aw_mmc_switch_vccq),
1527 DEVMETHOD(mmcbr_acquire_host, aw_mmc_acquire_host),
1528 DEVMETHOD(mmcbr_release_host, aw_mmc_release_host),
1529 #endif
1530
1531 #ifdef MMCCAM
1532 /* MMCCAM interface */
1533 DEVMETHOD(mmc_sim_get_tran_settings, aw_mmc_get_tran_settings),
1534 DEVMETHOD(mmc_sim_set_tran_settings, aw_mmc_set_tran_settings),
1535 DEVMETHOD(mmc_sim_cam_request, aw_mmc_cam_request),
1536 DEVMETHOD(mmc_sim_cam_poll, aw_mmc_cam_poll),
1537 #endif
1538
1539 DEVMETHOD_END
1540 };
1541
1542 static driver_t aw_mmc_driver = {
1543 "aw_mmc",
1544 aw_mmc_methods,
1545 sizeof(struct aw_mmc_softc),
1546 };
1547
1548 DRIVER_MODULE(aw_mmc, simplebus, aw_mmc_driver, NULL, NULL);
1549 #ifndef MMCCAM
1550 MMC_DECLARE_BRIDGE(aw_mmc);
1551 #endif
1552 SIMPLEBUS_PNP_INFO(compat_data);
1553