1 /*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24
25 #include <linux/firmware.h>
26
27 #include "amdgpu.h"
28 #include "sid.h"
29 #include "ppsmc.h"
30 #include "amdgpu_ucode.h"
31 #include "sislands_smc.h"
32
33 #include "smu/smu_6_0_d.h"
34 #include "smu/smu_6_0_sh_mask.h"
35
36 #include "gca/gfx_6_0_d.h"
37 #include "gca/gfx_6_0_sh_mask.h"
38
si_set_smc_sram_address(struct amdgpu_device * adev,u32 smc_address,u32 limit)39 static int si_set_smc_sram_address(struct amdgpu_device *adev,
40 u32 smc_address, u32 limit)
41 {
42 if (smc_address & 3)
43 return -EINVAL;
44 if ((smc_address + 3) > limit)
45 return -EINVAL;
46
47 WREG32(mmSMC_IND_INDEX_0, smc_address);
48 WREG32_P(mmSMC_IND_ACCESS_CNTL, 0, ~SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK);
49
50 return 0;
51 }
52
amdgpu_si_copy_bytes_to_smc(struct amdgpu_device * adev,u32 smc_start_address,const u8 * src,u32 byte_count,u32 limit)53 int amdgpu_si_copy_bytes_to_smc(struct amdgpu_device *adev,
54 u32 smc_start_address,
55 const u8 *src, u32 byte_count, u32 limit)
56 {
57 unsigned long flags;
58 int ret = 0;
59 u32 data, original_data, addr, extra_shift;
60
61 if (smc_start_address & 3)
62 return -EINVAL;
63 if ((smc_start_address + byte_count) > limit)
64 return -EINVAL;
65
66 addr = smc_start_address;
67
68 spin_lock_irqsave(&adev->smc_idx_lock, flags);
69 while (byte_count >= 4) {
70 /* SMC address space is BE */
71 data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3];
72
73 ret = si_set_smc_sram_address(adev, addr, limit);
74 if (ret)
75 goto done;
76
77 WREG32(mmSMC_IND_DATA_0, data);
78
79 src += 4;
80 byte_count -= 4;
81 addr += 4;
82 }
83
84 /* RMW for the final bytes */
85 if (byte_count > 0) {
86 data = 0;
87
88 ret = si_set_smc_sram_address(adev, addr, limit);
89 if (ret)
90 goto done;
91
92 original_data = RREG32(mmSMC_IND_DATA_0);
93 extra_shift = 8 * (4 - byte_count);
94
95 while (byte_count > 0) {
96 /* SMC address space is BE */
97 data = (data << 8) + *src++;
98 byte_count--;
99 }
100
101 data <<= extra_shift;
102 data |= (original_data & ~((~0UL) << extra_shift));
103
104 ret = si_set_smc_sram_address(adev, addr, limit);
105 if (ret)
106 goto done;
107
108 WREG32(mmSMC_IND_DATA_0, data);
109 }
110
111 done:
112 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
113
114 return ret;
115 }
116
amdgpu_si_start_smc(struct amdgpu_device * adev)117 void amdgpu_si_start_smc(struct amdgpu_device *adev)
118 {
119 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
120
121 tmp &= ~RST_REG;
122
123 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
124 }
125
amdgpu_si_reset_smc(struct amdgpu_device * adev)126 void amdgpu_si_reset_smc(struct amdgpu_device *adev)
127 {
128 u32 tmp;
129
130 RREG32(mmCB_CGTT_SCLK_CTRL);
131 RREG32(mmCB_CGTT_SCLK_CTRL);
132 RREG32(mmCB_CGTT_SCLK_CTRL);
133 RREG32(mmCB_CGTT_SCLK_CTRL);
134
135 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL) |
136 RST_REG;
137 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
138 }
139
amdgpu_si_program_jump_on_start(struct amdgpu_device * adev)140 int amdgpu_si_program_jump_on_start(struct amdgpu_device *adev)
141 {
142 static const u8 data[] = { 0x0E, 0x00, 0x40, 0x40 };
143
144 return amdgpu_si_copy_bytes_to_smc(adev, 0x0, data, 4, sizeof(data)+1);
145 }
146
amdgpu_si_smc_clock(struct amdgpu_device * adev,bool enable)147 void amdgpu_si_smc_clock(struct amdgpu_device *adev, bool enable)
148 {
149 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
150
151 if (enable)
152 tmp &= ~CK_DISABLE;
153 else
154 tmp |= CK_DISABLE;
155
156 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);
157 }
158
amdgpu_si_is_smc_running(struct amdgpu_device * adev)159 bool amdgpu_si_is_smc_running(struct amdgpu_device *adev)
160 {
161 u32 rst = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
162 u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
163
164 if (!(rst & RST_REG) && !(clk & CK_DISABLE))
165 return true;
166
167 return false;
168 }
169
amdgpu_si_send_msg_to_smc(struct amdgpu_device * adev,PPSMC_Msg msg)170 PPSMC_Result amdgpu_si_send_msg_to_smc(struct amdgpu_device *adev,
171 PPSMC_Msg msg)
172 {
173 u32 tmp;
174 int i;
175
176 if (!amdgpu_si_is_smc_running(adev))
177 return PPSMC_Result_Failed;
178
179 WREG32(mmSMC_MESSAGE_0, msg);
180
181 for (i = 0; i < adev->usec_timeout; i++) {
182 tmp = RREG32(mmSMC_RESP_0);
183 if (tmp != 0)
184 break;
185 udelay(1);
186 }
187
188 return (PPSMC_Result)RREG32(mmSMC_RESP_0);
189 }
190
amdgpu_si_wait_for_smc_inactive(struct amdgpu_device * adev)191 PPSMC_Result amdgpu_si_wait_for_smc_inactive(struct amdgpu_device *adev)
192 {
193 u32 tmp;
194 int i;
195
196 if (!amdgpu_si_is_smc_running(adev))
197 return PPSMC_Result_OK;
198
199 for (i = 0; i < adev->usec_timeout; i++) {
200 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
201 if ((tmp & CKEN) == 0)
202 break;
203 udelay(1);
204 }
205
206 return PPSMC_Result_OK;
207 }
208
amdgpu_si_load_smc_ucode(struct amdgpu_device * adev,u32 limit)209 int amdgpu_si_load_smc_ucode(struct amdgpu_device *adev, u32 limit)
210 {
211 const struct smc_firmware_header_v1_0 *hdr;
212 unsigned long flags;
213 u32 ucode_start_address;
214 u32 ucode_size;
215 const u8 *src;
216 u32 data;
217
218 if (!adev->pm.fw)
219 return -EINVAL;
220
221 hdr = (const struct smc_firmware_header_v1_0 *)adev->pm.fw->data;
222
223 amdgpu_ucode_print_smc_hdr(&hdr->header);
224
225 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
226 ucode_start_address = le32_to_cpu(hdr->ucode_start_addr);
227 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes);
228 src = (const u8 *)
229 (adev->pm.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
230 if (ucode_size & 3)
231 return -EINVAL;
232
233 spin_lock_irqsave(&adev->smc_idx_lock, flags);
234 WREG32(mmSMC_IND_INDEX_0, ucode_start_address);
235 WREG32_P(mmSMC_IND_ACCESS_CNTL, SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK, ~SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK);
236 while (ucode_size >= 4) {
237 /* SMC address space is BE */
238 data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3];
239
240 WREG32(mmSMC_IND_DATA_0, data);
241
242 src += 4;
243 ucode_size -= 4;
244 }
245 WREG32_P(mmSMC_IND_ACCESS_CNTL, 0, ~SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK);
246 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
247
248 return 0;
249 }
250
amdgpu_si_read_smc_sram_dword(struct amdgpu_device * adev,u32 smc_address,u32 * value,u32 limit)251 int amdgpu_si_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,
252 u32 *value, u32 limit)
253 {
254 unsigned long flags;
255 int ret;
256
257 spin_lock_irqsave(&adev->smc_idx_lock, flags);
258 ret = si_set_smc_sram_address(adev, smc_address, limit);
259 if (ret == 0)
260 *value = RREG32(mmSMC_IND_DATA_0);
261 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
262
263 return ret;
264 }
265
amdgpu_si_write_smc_sram_dword(struct amdgpu_device * adev,u32 smc_address,u32 value,u32 limit)266 int amdgpu_si_write_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,
267 u32 value, u32 limit)
268 {
269 unsigned long flags;
270 int ret;
271
272 spin_lock_irqsave(&adev->smc_idx_lock, flags);
273 ret = si_set_smc_sram_address(adev, smc_address, limit);
274 if (ret == 0)
275 WREG32(mmSMC_IND_DATA_0, value);
276 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
277
278 return ret;
279 }
280