1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Cryptographic API.
4 *
5 * Support for OMAP AES HW acceleration.
6 *
7 * Copyright (c) 2010 Nokia Corporation
8 * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
9 * Copyright (c) 2011 Texas Instruments Incorporated
10 */
11
12 #define pr_fmt(fmt) "%20s: " fmt, __func__
13 #define prn(num) pr_debug(#num "=%d\n", num)
14 #define prx(num) pr_debug(#num "=%x\n", num)
15
16 #include <crypto/aes.h>
17 #include <crypto/gcm.h>
18 #include <crypto/internal/aead.h>
19 #include <crypto/internal/engine.h>
20 #include <crypto/internal/skcipher.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/dmaengine.h>
23 #include <linux/err.h>
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
26 #include <linux/io.h>
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/of.h>
30 #include <linux/of_address.h>
31 #include <linux/platform_device.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/scatterlist.h>
34 #include <linux/string.h>
35
36 #include "omap-crypto.h"
37 #include "omap-aes.h"
38
39 /* keep registered devices data here */
40 static LIST_HEAD(dev_list);
41 static DEFINE_SPINLOCK(list_lock);
42
43 static int aes_fallback_sz = 200;
44
45 #ifdef DEBUG
46 #define omap_aes_read(dd, offset) \
47 ({ \
48 int _read_ret; \
49 _read_ret = __raw_readl(dd->io_base + offset); \
50 pr_debug("omap_aes_read(" #offset "=%#x)= %#x\n", \
51 offset, _read_ret); \
52 _read_ret; \
53 })
54 #else
omap_aes_read(struct omap_aes_dev * dd,u32 offset)55 inline u32 omap_aes_read(struct omap_aes_dev *dd, u32 offset)
56 {
57 return __raw_readl(dd->io_base + offset);
58 }
59 #endif
60
61 #ifdef DEBUG
62 #define omap_aes_write(dd, offset, value) \
63 do { \
64 pr_debug("omap_aes_write(" #offset "=%#x) value=%#x\n", \
65 offset, value); \
66 __raw_writel(value, dd->io_base + offset); \
67 } while (0)
68 #else
omap_aes_write(struct omap_aes_dev * dd,u32 offset,u32 value)69 inline void omap_aes_write(struct omap_aes_dev *dd, u32 offset,
70 u32 value)
71 {
72 __raw_writel(value, dd->io_base + offset);
73 }
74 #endif
75
omap_aes_write_mask(struct omap_aes_dev * dd,u32 offset,u32 value,u32 mask)76 static inline void omap_aes_write_mask(struct omap_aes_dev *dd, u32 offset,
77 u32 value, u32 mask)
78 {
79 u32 val;
80
81 val = omap_aes_read(dd, offset);
82 val &= ~mask;
83 val |= value;
84 omap_aes_write(dd, offset, val);
85 }
86
omap_aes_write_n(struct omap_aes_dev * dd,u32 offset,u32 * value,int count)87 static void omap_aes_write_n(struct omap_aes_dev *dd, u32 offset,
88 u32 *value, int count)
89 {
90 for (; count--; value++, offset += 4)
91 omap_aes_write(dd, offset, *value);
92 }
93
omap_aes_hw_init(struct omap_aes_dev * dd)94 static int omap_aes_hw_init(struct omap_aes_dev *dd)
95 {
96 int err;
97
98 if (!(dd->flags & FLAGS_INIT)) {
99 dd->flags |= FLAGS_INIT;
100 dd->err = 0;
101 }
102
103 err = pm_runtime_resume_and_get(dd->dev);
104 if (err < 0) {
105 dev_err(dd->dev, "failed to get sync: %d\n", err);
106 return err;
107 }
108
109 return 0;
110 }
111
omap_aes_clear_copy_flags(struct omap_aes_dev * dd)112 void omap_aes_clear_copy_flags(struct omap_aes_dev *dd)
113 {
114 dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_IN_DATA_ST_SHIFT);
115 dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_OUT_DATA_ST_SHIFT);
116 dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_ASSOC_DATA_ST_SHIFT);
117 }
118
omap_aes_write_ctrl(struct omap_aes_dev * dd)119 int omap_aes_write_ctrl(struct omap_aes_dev *dd)
120 {
121 struct omap_aes_reqctx *rctx;
122 unsigned int key32;
123 int i, err;
124 u32 val;
125
126 err = omap_aes_hw_init(dd);
127 if (err)
128 return err;
129
130 key32 = dd->ctx->keylen / sizeof(u32);
131
132 /* RESET the key as previous HASH keys should not get affected*/
133 if (dd->flags & FLAGS_GCM)
134 for (i = 0; i < 0x40; i = i + 4)
135 omap_aes_write(dd, i, 0x0);
136
137 for (i = 0; i < key32; i++) {
138 omap_aes_write(dd, AES_REG_KEY(dd, i),
139 (__force u32)cpu_to_le32(dd->ctx->key[i]));
140 }
141
142 if ((dd->flags & (FLAGS_CBC | FLAGS_CTR)) && dd->req->iv)
143 omap_aes_write_n(dd, AES_REG_IV(dd, 0), (void *)dd->req->iv, 4);
144
145 if ((dd->flags & (FLAGS_GCM)) && dd->aead_req->iv) {
146 rctx = aead_request_ctx(dd->aead_req);
147 omap_aes_write_n(dd, AES_REG_IV(dd, 0), (u32 *)rctx->iv, 4);
148 }
149
150 val = FLD_VAL(((dd->ctx->keylen >> 3) - 1), 4, 3);
151 if (dd->flags & FLAGS_CBC)
152 val |= AES_REG_CTRL_CBC;
153
154 if (dd->flags & (FLAGS_CTR | FLAGS_GCM))
155 val |= AES_REG_CTRL_CTR | AES_REG_CTRL_CTR_WIDTH_128;
156
157 if (dd->flags & FLAGS_GCM)
158 val |= AES_REG_CTRL_GCM;
159
160 if (dd->flags & FLAGS_ENCRYPT)
161 val |= AES_REG_CTRL_DIRECTION;
162
163 omap_aes_write_mask(dd, AES_REG_CTRL(dd), val, AES_REG_CTRL_MASK);
164
165 return 0;
166 }
167
omap_aes_dma_trigger_omap2(struct omap_aes_dev * dd,int length)168 static void omap_aes_dma_trigger_omap2(struct omap_aes_dev *dd, int length)
169 {
170 u32 mask, val;
171
172 val = dd->pdata->dma_start;
173
174 if (dd->dma_lch_out != NULL)
175 val |= dd->pdata->dma_enable_out;
176 if (dd->dma_lch_in != NULL)
177 val |= dd->pdata->dma_enable_in;
178
179 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
180 dd->pdata->dma_start;
181
182 omap_aes_write_mask(dd, AES_REG_MASK(dd), val, mask);
183
184 }
185
omap_aes_dma_trigger_omap4(struct omap_aes_dev * dd,int length)186 static void omap_aes_dma_trigger_omap4(struct omap_aes_dev *dd, int length)
187 {
188 omap_aes_write(dd, AES_REG_LENGTH_N(0), length);
189 omap_aes_write(dd, AES_REG_LENGTH_N(1), 0);
190 if (dd->flags & FLAGS_GCM)
191 omap_aes_write(dd, AES_REG_A_LEN, dd->assoc_len);
192
193 omap_aes_dma_trigger_omap2(dd, length);
194 }
195
omap_aes_dma_stop(struct omap_aes_dev * dd)196 static void omap_aes_dma_stop(struct omap_aes_dev *dd)
197 {
198 u32 mask;
199
200 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
201 dd->pdata->dma_start;
202
203 omap_aes_write_mask(dd, AES_REG_MASK(dd), 0, mask);
204 }
205
omap_aes_find_dev(struct omap_aes_reqctx * rctx)206 struct omap_aes_dev *omap_aes_find_dev(struct omap_aes_reqctx *rctx)
207 {
208 struct omap_aes_dev *dd;
209
210 spin_lock_bh(&list_lock);
211 dd = list_first_entry(&dev_list, struct omap_aes_dev, list);
212 list_move_tail(&dd->list, &dev_list);
213 rctx->dd = dd;
214 spin_unlock_bh(&list_lock);
215
216 return dd;
217 }
218
omap_aes_dma_out_callback(void * data)219 static void omap_aes_dma_out_callback(void *data)
220 {
221 struct omap_aes_dev *dd = data;
222
223 /* dma_lch_out - completed */
224 tasklet_schedule(&dd->done_task);
225 }
226
omap_aes_dma_init(struct omap_aes_dev * dd)227 static int omap_aes_dma_init(struct omap_aes_dev *dd)
228 {
229 int err;
230
231 dd->dma_lch_out = NULL;
232 dd->dma_lch_in = NULL;
233
234 dd->dma_lch_in = dma_request_chan(dd->dev, "rx");
235 if (IS_ERR(dd->dma_lch_in)) {
236 dev_err(dd->dev, "Unable to request in DMA channel\n");
237 return PTR_ERR(dd->dma_lch_in);
238 }
239
240 dd->dma_lch_out = dma_request_chan(dd->dev, "tx");
241 if (IS_ERR(dd->dma_lch_out)) {
242 dev_err(dd->dev, "Unable to request out DMA channel\n");
243 err = PTR_ERR(dd->dma_lch_out);
244 goto err_dma_out;
245 }
246
247 return 0;
248
249 err_dma_out:
250 dma_release_channel(dd->dma_lch_in);
251
252 return err;
253 }
254
omap_aes_dma_cleanup(struct omap_aes_dev * dd)255 static void omap_aes_dma_cleanup(struct omap_aes_dev *dd)
256 {
257 if (dd->pio_only)
258 return;
259
260 dma_release_channel(dd->dma_lch_out);
261 dma_release_channel(dd->dma_lch_in);
262 }
263
omap_aes_crypt_dma(struct omap_aes_dev * dd,struct scatterlist * in_sg,struct scatterlist * out_sg,int in_sg_len,int out_sg_len)264 static int omap_aes_crypt_dma(struct omap_aes_dev *dd,
265 struct scatterlist *in_sg,
266 struct scatterlist *out_sg,
267 int in_sg_len, int out_sg_len)
268 {
269 struct dma_async_tx_descriptor *tx_in, *tx_out = NULL, *cb_desc;
270 struct dma_slave_config cfg;
271 int ret;
272
273 if (dd->pio_only) {
274 dd->in_sg_offset = 0;
275 if (out_sg_len)
276 dd->out_sg_offset = 0;
277
278 /* Enable DATAIN interrupt and let it take
279 care of the rest */
280 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2);
281 return 0;
282 }
283
284 dma_sync_sg_for_device(dd->dev, dd->in_sg, in_sg_len, DMA_TO_DEVICE);
285
286 memset(&cfg, 0, sizeof(cfg));
287
288 cfg.src_addr = dd->phys_base + AES_REG_DATA_N(dd, 0);
289 cfg.dst_addr = dd->phys_base + AES_REG_DATA_N(dd, 0);
290 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
291 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
292 cfg.src_maxburst = DST_MAXBURST;
293 cfg.dst_maxburst = DST_MAXBURST;
294
295 /* IN */
296 ret = dmaengine_slave_config(dd->dma_lch_in, &cfg);
297 if (ret) {
298 dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n",
299 ret);
300 return ret;
301 }
302
303 tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, in_sg_len,
304 DMA_MEM_TO_DEV,
305 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
306 if (!tx_in) {
307 dev_err(dd->dev, "IN prep_slave_sg() failed\n");
308 return -EINVAL;
309 }
310
311 /* No callback necessary */
312 tx_in->callback_param = dd;
313 tx_in->callback = NULL;
314
315 /* OUT */
316 if (out_sg_len) {
317 ret = dmaengine_slave_config(dd->dma_lch_out, &cfg);
318 if (ret) {
319 dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n",
320 ret);
321 return ret;
322 }
323
324 tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg,
325 out_sg_len,
326 DMA_DEV_TO_MEM,
327 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
328 if (!tx_out) {
329 dev_err(dd->dev, "OUT prep_slave_sg() failed\n");
330 return -EINVAL;
331 }
332
333 cb_desc = tx_out;
334 } else {
335 cb_desc = tx_in;
336 }
337
338 if (dd->flags & FLAGS_GCM)
339 cb_desc->callback = omap_aes_gcm_dma_out_callback;
340 else
341 cb_desc->callback = omap_aes_dma_out_callback;
342 cb_desc->callback_param = dd;
343
344
345 dmaengine_submit(tx_in);
346 if (tx_out)
347 dmaengine_submit(tx_out);
348
349 dma_async_issue_pending(dd->dma_lch_in);
350 if (out_sg_len)
351 dma_async_issue_pending(dd->dma_lch_out);
352
353 /* start DMA */
354 dd->pdata->trigger(dd, dd->total);
355
356 return 0;
357 }
358
omap_aes_crypt_dma_start(struct omap_aes_dev * dd)359 int omap_aes_crypt_dma_start(struct omap_aes_dev *dd)
360 {
361 int err;
362
363 pr_debug("total: %zu\n", dd->total);
364
365 if (!dd->pio_only) {
366 err = dma_map_sg(dd->dev, dd->in_sg, dd->in_sg_len,
367 DMA_TO_DEVICE);
368 if (!err) {
369 dev_err(dd->dev, "dma_map_sg() error\n");
370 return -EINVAL;
371 }
372
373 if (dd->out_sg_len) {
374 err = dma_map_sg(dd->dev, dd->out_sg, dd->out_sg_len,
375 DMA_FROM_DEVICE);
376 if (!err) {
377 dev_err(dd->dev, "dma_map_sg() error\n");
378 return -EINVAL;
379 }
380 }
381 }
382
383 err = omap_aes_crypt_dma(dd, dd->in_sg, dd->out_sg, dd->in_sg_len,
384 dd->out_sg_len);
385 if (err && !dd->pio_only) {
386 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
387 if (dd->out_sg_len)
388 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
389 DMA_FROM_DEVICE);
390 }
391
392 return err;
393 }
394
omap_aes_finish_req(struct omap_aes_dev * dd,int err)395 static void omap_aes_finish_req(struct omap_aes_dev *dd, int err)
396 {
397 struct skcipher_request *req = dd->req;
398
399 pr_debug("err: %d\n", err);
400
401 crypto_finalize_skcipher_request(dd->engine, req, err);
402
403 pm_runtime_put_autosuspend(dd->dev);
404 }
405
omap_aes_crypt_dma_stop(struct omap_aes_dev * dd)406 int omap_aes_crypt_dma_stop(struct omap_aes_dev *dd)
407 {
408 pr_debug("total: %zu\n", dd->total);
409
410 omap_aes_dma_stop(dd);
411
412
413 return 0;
414 }
415
omap_aes_handle_queue(struct omap_aes_dev * dd,struct skcipher_request * req)416 static int omap_aes_handle_queue(struct omap_aes_dev *dd,
417 struct skcipher_request *req)
418 {
419 if (req)
420 return crypto_transfer_skcipher_request_to_engine(dd->engine, req);
421
422 return 0;
423 }
424
omap_aes_prepare_req(struct skcipher_request * req,struct omap_aes_dev * dd)425 static int omap_aes_prepare_req(struct skcipher_request *req,
426 struct omap_aes_dev *dd)
427 {
428 struct omap_aes_ctx *ctx = crypto_skcipher_ctx(
429 crypto_skcipher_reqtfm(req));
430 struct omap_aes_reqctx *rctx = skcipher_request_ctx(req);
431 int ret;
432 u16 flags;
433
434 /* assign new request to device */
435 dd->req = req;
436 dd->total = req->cryptlen;
437 dd->total_save = req->cryptlen;
438 dd->in_sg = req->src;
439 dd->out_sg = req->dst;
440 dd->orig_out = req->dst;
441
442 flags = OMAP_CRYPTO_COPY_DATA;
443 if (req->src == req->dst)
444 flags |= OMAP_CRYPTO_FORCE_COPY;
445
446 ret = omap_crypto_align_sg(&dd->in_sg, dd->total, AES_BLOCK_SIZE,
447 dd->in_sgl, flags,
448 FLAGS_IN_DATA_ST_SHIFT, &dd->flags);
449 if (ret)
450 return ret;
451
452 ret = omap_crypto_align_sg(&dd->out_sg, dd->total, AES_BLOCK_SIZE,
453 &dd->out_sgl, 0,
454 FLAGS_OUT_DATA_ST_SHIFT, &dd->flags);
455 if (ret)
456 return ret;
457
458 dd->in_sg_len = sg_nents_for_len(dd->in_sg, dd->total);
459 if (dd->in_sg_len < 0)
460 return dd->in_sg_len;
461
462 dd->out_sg_len = sg_nents_for_len(dd->out_sg, dd->total);
463 if (dd->out_sg_len < 0)
464 return dd->out_sg_len;
465
466 rctx->mode &= FLAGS_MODE_MASK;
467 dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode;
468
469 dd->ctx = ctx;
470 rctx->dd = dd;
471
472 return omap_aes_write_ctrl(dd);
473 }
474
omap_aes_crypt_req(struct crypto_engine * engine,void * areq)475 static int omap_aes_crypt_req(struct crypto_engine *engine,
476 void *areq)
477 {
478 struct skcipher_request *req = container_of(areq, struct skcipher_request, base);
479 struct omap_aes_reqctx *rctx = skcipher_request_ctx(req);
480 struct omap_aes_dev *dd = rctx->dd;
481
482 if (!dd)
483 return -ENODEV;
484
485 return omap_aes_prepare_req(req, dd) ?:
486 omap_aes_crypt_dma_start(dd);
487 }
488
omap_aes_copy_ivout(struct omap_aes_dev * dd,u8 * ivbuf)489 static void omap_aes_copy_ivout(struct omap_aes_dev *dd, u8 *ivbuf)
490 {
491 int i;
492
493 for (i = 0; i < 4; i++)
494 ((u32 *)ivbuf)[i] = omap_aes_read(dd, AES_REG_IV(dd, i));
495 }
496
omap_aes_done_task(unsigned long data)497 static void omap_aes_done_task(unsigned long data)
498 {
499 struct omap_aes_dev *dd = (struct omap_aes_dev *)data;
500
501 pr_debug("enter done_task\n");
502
503 if (!dd->pio_only) {
504 dma_sync_sg_for_device(dd->dev, dd->out_sg, dd->out_sg_len,
505 DMA_FROM_DEVICE);
506 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
507 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
508 DMA_FROM_DEVICE);
509 omap_aes_crypt_dma_stop(dd);
510 }
511
512 omap_crypto_cleanup(dd->in_sg, NULL, 0, dd->total_save,
513 FLAGS_IN_DATA_ST_SHIFT, dd->flags);
514
515 omap_crypto_cleanup(dd->out_sg, dd->orig_out, 0, dd->total_save,
516 FLAGS_OUT_DATA_ST_SHIFT, dd->flags);
517
518 /* Update IV output */
519 if (dd->flags & (FLAGS_CBC | FLAGS_CTR))
520 omap_aes_copy_ivout(dd, dd->req->iv);
521
522 omap_aes_finish_req(dd, 0);
523
524 pr_debug("exit\n");
525 }
526
omap_aes_crypt(struct skcipher_request * req,unsigned long mode)527 static int omap_aes_crypt(struct skcipher_request *req, unsigned long mode)
528 {
529 struct omap_aes_ctx *ctx = crypto_skcipher_ctx(
530 crypto_skcipher_reqtfm(req));
531 struct omap_aes_reqctx *rctx = skcipher_request_ctx(req);
532 struct omap_aes_dev *dd;
533 int ret;
534
535 if ((req->cryptlen % AES_BLOCK_SIZE) && !(mode & FLAGS_CTR))
536 return -EINVAL;
537
538 pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->cryptlen,
539 !!(mode & FLAGS_ENCRYPT),
540 !!(mode & FLAGS_CBC));
541
542 if (req->cryptlen < aes_fallback_sz) {
543 skcipher_request_set_tfm(&rctx->fallback_req, ctx->fallback);
544 skcipher_request_set_callback(&rctx->fallback_req,
545 req->base.flags,
546 req->base.complete,
547 req->base.data);
548 skcipher_request_set_crypt(&rctx->fallback_req, req->src,
549 req->dst, req->cryptlen, req->iv);
550
551 if (mode & FLAGS_ENCRYPT)
552 ret = crypto_skcipher_encrypt(&rctx->fallback_req);
553 else
554 ret = crypto_skcipher_decrypt(&rctx->fallback_req);
555 return ret;
556 }
557 dd = omap_aes_find_dev(rctx);
558 if (!dd)
559 return -ENODEV;
560
561 rctx->mode = mode;
562
563 return omap_aes_handle_queue(dd, req);
564 }
565
566 /* ********************** ALG API ************************************ */
567
omap_aes_setkey(struct crypto_skcipher * tfm,const u8 * key,unsigned int keylen)568 static int omap_aes_setkey(struct crypto_skcipher *tfm, const u8 *key,
569 unsigned int keylen)
570 {
571 struct omap_aes_ctx *ctx = crypto_skcipher_ctx(tfm);
572 int ret;
573
574 if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 &&
575 keylen != AES_KEYSIZE_256)
576 return -EINVAL;
577
578 pr_debug("enter, keylen: %d\n", keylen);
579
580 memcpy(ctx->key, key, keylen);
581 ctx->keylen = keylen;
582
583 crypto_skcipher_clear_flags(ctx->fallback, CRYPTO_TFM_REQ_MASK);
584 crypto_skcipher_set_flags(ctx->fallback, tfm->base.crt_flags &
585 CRYPTO_TFM_REQ_MASK);
586
587 ret = crypto_skcipher_setkey(ctx->fallback, key, keylen);
588 if (!ret)
589 return 0;
590
591 return 0;
592 }
593
omap_aes_ecb_encrypt(struct skcipher_request * req)594 static int omap_aes_ecb_encrypt(struct skcipher_request *req)
595 {
596 return omap_aes_crypt(req, FLAGS_ENCRYPT);
597 }
598
omap_aes_ecb_decrypt(struct skcipher_request * req)599 static int omap_aes_ecb_decrypt(struct skcipher_request *req)
600 {
601 return omap_aes_crypt(req, 0);
602 }
603
omap_aes_cbc_encrypt(struct skcipher_request * req)604 static int omap_aes_cbc_encrypt(struct skcipher_request *req)
605 {
606 return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC);
607 }
608
omap_aes_cbc_decrypt(struct skcipher_request * req)609 static int omap_aes_cbc_decrypt(struct skcipher_request *req)
610 {
611 return omap_aes_crypt(req, FLAGS_CBC);
612 }
613
omap_aes_ctr_encrypt(struct skcipher_request * req)614 static int omap_aes_ctr_encrypt(struct skcipher_request *req)
615 {
616 return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CTR);
617 }
618
omap_aes_ctr_decrypt(struct skcipher_request * req)619 static int omap_aes_ctr_decrypt(struct skcipher_request *req)
620 {
621 return omap_aes_crypt(req, FLAGS_CTR);
622 }
623
omap_aes_init_tfm(struct crypto_skcipher * tfm)624 static int omap_aes_init_tfm(struct crypto_skcipher *tfm)
625 {
626 const char *name = crypto_tfm_alg_name(&tfm->base);
627 struct omap_aes_ctx *ctx = crypto_skcipher_ctx(tfm);
628 struct crypto_skcipher *blk;
629
630 blk = crypto_alloc_skcipher(name, 0, CRYPTO_ALG_NEED_FALLBACK);
631 if (IS_ERR(blk))
632 return PTR_ERR(blk);
633
634 ctx->fallback = blk;
635
636 crypto_skcipher_set_reqsize(tfm, sizeof(struct omap_aes_reqctx) +
637 crypto_skcipher_reqsize(blk));
638
639 return 0;
640 }
641
omap_aes_exit_tfm(struct crypto_skcipher * tfm)642 static void omap_aes_exit_tfm(struct crypto_skcipher *tfm)
643 {
644 struct omap_aes_ctx *ctx = crypto_skcipher_ctx(tfm);
645
646 if (ctx->fallback)
647 crypto_free_skcipher(ctx->fallback);
648
649 ctx->fallback = NULL;
650 }
651
652 /* ********************** ALGS ************************************ */
653
654 static struct skcipher_engine_alg algs_ecb_cbc[] = {
655 {
656 .base = {
657 .base.cra_name = "ecb(aes)",
658 .base.cra_driver_name = "ecb-aes-omap",
659 .base.cra_priority = 300,
660 .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
661 CRYPTO_ALG_ASYNC |
662 CRYPTO_ALG_NEED_FALLBACK,
663 .base.cra_blocksize = AES_BLOCK_SIZE,
664 .base.cra_ctxsize = sizeof(struct omap_aes_ctx),
665 .base.cra_module = THIS_MODULE,
666
667 .min_keysize = AES_MIN_KEY_SIZE,
668 .max_keysize = AES_MAX_KEY_SIZE,
669 .setkey = omap_aes_setkey,
670 .encrypt = omap_aes_ecb_encrypt,
671 .decrypt = omap_aes_ecb_decrypt,
672 .init = omap_aes_init_tfm,
673 .exit = omap_aes_exit_tfm,
674 },
675 .op.do_one_request = omap_aes_crypt_req,
676 },
677 {
678 .base = {
679 .base.cra_name = "cbc(aes)",
680 .base.cra_driver_name = "cbc-aes-omap",
681 .base.cra_priority = 300,
682 .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
683 CRYPTO_ALG_ASYNC |
684 CRYPTO_ALG_NEED_FALLBACK,
685 .base.cra_blocksize = AES_BLOCK_SIZE,
686 .base.cra_ctxsize = sizeof(struct omap_aes_ctx),
687 .base.cra_module = THIS_MODULE,
688
689 .min_keysize = AES_MIN_KEY_SIZE,
690 .max_keysize = AES_MAX_KEY_SIZE,
691 .ivsize = AES_BLOCK_SIZE,
692 .setkey = omap_aes_setkey,
693 .encrypt = omap_aes_cbc_encrypt,
694 .decrypt = omap_aes_cbc_decrypt,
695 .init = omap_aes_init_tfm,
696 .exit = omap_aes_exit_tfm,
697 },
698 .op.do_one_request = omap_aes_crypt_req,
699 }
700 };
701
702 static struct skcipher_engine_alg algs_ctr[] = {
703 {
704 .base = {
705 .base.cra_name = "ctr(aes)",
706 .base.cra_driver_name = "ctr-aes-omap",
707 .base.cra_priority = 300,
708 .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
709 CRYPTO_ALG_ASYNC |
710 CRYPTO_ALG_NEED_FALLBACK,
711 .base.cra_blocksize = 1,
712 .base.cra_ctxsize = sizeof(struct omap_aes_ctx),
713 .base.cra_module = THIS_MODULE,
714
715 .min_keysize = AES_MIN_KEY_SIZE,
716 .max_keysize = AES_MAX_KEY_SIZE,
717 .ivsize = AES_BLOCK_SIZE,
718 .setkey = omap_aes_setkey,
719 .encrypt = omap_aes_ctr_encrypt,
720 .decrypt = omap_aes_ctr_decrypt,
721 .init = omap_aes_init_tfm,
722 .exit = omap_aes_exit_tfm,
723 },
724 .op.do_one_request = omap_aes_crypt_req,
725 }
726 };
727
728 static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc[] = {
729 {
730 .algs_list = algs_ecb_cbc,
731 .size = ARRAY_SIZE(algs_ecb_cbc),
732 },
733 };
734
735 static struct aead_engine_alg algs_aead_gcm[] = {
736 {
737 .base = {
738 .base = {
739 .cra_name = "gcm(aes)",
740 .cra_driver_name = "gcm-aes-omap",
741 .cra_priority = 300,
742 .cra_flags = CRYPTO_ALG_ASYNC |
743 CRYPTO_ALG_KERN_DRIVER_ONLY,
744 .cra_blocksize = 1,
745 .cra_ctxsize = sizeof(struct omap_aes_gcm_ctx),
746 .cra_alignmask = 0xf,
747 .cra_module = THIS_MODULE,
748 },
749 .init = omap_aes_gcm_cra_init,
750 .ivsize = GCM_AES_IV_SIZE,
751 .maxauthsize = AES_BLOCK_SIZE,
752 .setkey = omap_aes_gcm_setkey,
753 .setauthsize = omap_aes_gcm_setauthsize,
754 .encrypt = omap_aes_gcm_encrypt,
755 .decrypt = omap_aes_gcm_decrypt,
756 },
757 .op.do_one_request = omap_aes_gcm_crypt_req,
758 },
759 {
760 .base = {
761 .base = {
762 .cra_name = "rfc4106(gcm(aes))",
763 .cra_driver_name = "rfc4106-gcm-aes-omap",
764 .cra_priority = 300,
765 .cra_flags = CRYPTO_ALG_ASYNC |
766 CRYPTO_ALG_KERN_DRIVER_ONLY,
767 .cra_blocksize = 1,
768 .cra_ctxsize = sizeof(struct omap_aes_gcm_ctx),
769 .cra_alignmask = 0xf,
770 .cra_module = THIS_MODULE,
771 },
772 .init = omap_aes_gcm_cra_init,
773 .maxauthsize = AES_BLOCK_SIZE,
774 .ivsize = GCM_RFC4106_IV_SIZE,
775 .setkey = omap_aes_4106gcm_setkey,
776 .setauthsize = omap_aes_4106gcm_setauthsize,
777 .encrypt = omap_aes_4106gcm_encrypt,
778 .decrypt = omap_aes_4106gcm_decrypt,
779 },
780 .op.do_one_request = omap_aes_gcm_crypt_req,
781 },
782 };
783
784 static struct omap_aes_aead_algs omap_aes_aead_info = {
785 .algs_list = algs_aead_gcm,
786 .size = ARRAY_SIZE(algs_aead_gcm),
787 };
788
789 static const struct omap_aes_pdata omap_aes_pdata_omap2 = {
790 .algs_info = omap_aes_algs_info_ecb_cbc,
791 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc),
792 .trigger = omap_aes_dma_trigger_omap2,
793 .key_ofs = 0x1c,
794 .iv_ofs = 0x20,
795 .ctrl_ofs = 0x30,
796 .data_ofs = 0x34,
797 .rev_ofs = 0x44,
798 .mask_ofs = 0x48,
799 .dma_enable_in = BIT(2),
800 .dma_enable_out = BIT(3),
801 .dma_start = BIT(5),
802 .major_mask = 0xf0,
803 .major_shift = 4,
804 .minor_mask = 0x0f,
805 .minor_shift = 0,
806 };
807
808 #ifdef CONFIG_OF
809 static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc_ctr[] = {
810 {
811 .algs_list = algs_ecb_cbc,
812 .size = ARRAY_SIZE(algs_ecb_cbc),
813 },
814 {
815 .algs_list = algs_ctr,
816 .size = ARRAY_SIZE(algs_ctr),
817 },
818 };
819
820 static const struct omap_aes_pdata omap_aes_pdata_omap3 = {
821 .algs_info = omap_aes_algs_info_ecb_cbc_ctr,
822 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr),
823 .trigger = omap_aes_dma_trigger_omap2,
824 .key_ofs = 0x1c,
825 .iv_ofs = 0x20,
826 .ctrl_ofs = 0x30,
827 .data_ofs = 0x34,
828 .rev_ofs = 0x44,
829 .mask_ofs = 0x48,
830 .dma_enable_in = BIT(2),
831 .dma_enable_out = BIT(3),
832 .dma_start = BIT(5),
833 .major_mask = 0xf0,
834 .major_shift = 4,
835 .minor_mask = 0x0f,
836 .minor_shift = 0,
837 };
838
839 static const struct omap_aes_pdata omap_aes_pdata_omap4 = {
840 .algs_info = omap_aes_algs_info_ecb_cbc_ctr,
841 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr),
842 .aead_algs_info = &omap_aes_aead_info,
843 .trigger = omap_aes_dma_trigger_omap4,
844 .key_ofs = 0x3c,
845 .iv_ofs = 0x40,
846 .ctrl_ofs = 0x50,
847 .data_ofs = 0x60,
848 .rev_ofs = 0x80,
849 .mask_ofs = 0x84,
850 .irq_status_ofs = 0x8c,
851 .irq_enable_ofs = 0x90,
852 .dma_enable_in = BIT(5),
853 .dma_enable_out = BIT(6),
854 .major_mask = 0x0700,
855 .major_shift = 8,
856 .minor_mask = 0x003f,
857 .minor_shift = 0,
858 };
859
omap_aes_irq(int irq,void * dev_id)860 static irqreturn_t omap_aes_irq(int irq, void *dev_id)
861 {
862 struct omap_aes_dev *dd = dev_id;
863 u32 status, i;
864 u32 *src, *dst;
865
866 status = omap_aes_read(dd, AES_REG_IRQ_STATUS(dd));
867 if (status & AES_REG_IRQ_DATA_IN) {
868 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0);
869
870 BUG_ON(!dd->in_sg);
871
872 BUG_ON(dd->in_sg_offset > dd->in_sg->length);
873
874 src = sg_virt(dd->in_sg) + dd->in_sg_offset;
875
876 for (i = 0; i < AES_BLOCK_WORDS; i++) {
877 omap_aes_write(dd, AES_REG_DATA_N(dd, i), *src);
878 dd->in_sg_offset += 4;
879 if (dd->in_sg_offset == dd->in_sg->length) {
880 dd->in_sg = sg_next(dd->in_sg);
881 if (dd->in_sg) {
882 dd->in_sg_offset = 0;
883 src = sg_virt(dd->in_sg);
884 }
885 } else {
886 src++;
887 }
888 }
889
890 /* Clear IRQ status */
891 status &= ~AES_REG_IRQ_DATA_IN;
892 omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status);
893
894 /* Enable DATA_OUT interrupt */
895 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x4);
896
897 } else if (status & AES_REG_IRQ_DATA_OUT) {
898 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0);
899
900 BUG_ON(!dd->out_sg);
901
902 BUG_ON(dd->out_sg_offset > dd->out_sg->length);
903
904 dst = sg_virt(dd->out_sg) + dd->out_sg_offset;
905
906 for (i = 0; i < AES_BLOCK_WORDS; i++) {
907 *dst = omap_aes_read(dd, AES_REG_DATA_N(dd, i));
908 dd->out_sg_offset += 4;
909 if (dd->out_sg_offset == dd->out_sg->length) {
910 dd->out_sg = sg_next(dd->out_sg);
911 if (dd->out_sg) {
912 dd->out_sg_offset = 0;
913 dst = sg_virt(dd->out_sg);
914 }
915 } else {
916 dst++;
917 }
918 }
919
920 dd->total -= min_t(size_t, AES_BLOCK_SIZE, dd->total);
921
922 /* Clear IRQ status */
923 status &= ~AES_REG_IRQ_DATA_OUT;
924 omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status);
925
926 if (!dd->total)
927 /* All bytes read! */
928 tasklet_schedule(&dd->done_task);
929 else
930 /* Enable DATA_IN interrupt for next block */
931 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2);
932 }
933
934 return IRQ_HANDLED;
935 }
936
937 static const struct of_device_id omap_aes_of_match[] = {
938 {
939 .compatible = "ti,omap2-aes",
940 .data = &omap_aes_pdata_omap2,
941 },
942 {
943 .compatible = "ti,omap3-aes",
944 .data = &omap_aes_pdata_omap3,
945 },
946 {
947 .compatible = "ti,omap4-aes",
948 .data = &omap_aes_pdata_omap4,
949 },
950 {},
951 };
952 MODULE_DEVICE_TABLE(of, omap_aes_of_match);
953
omap_aes_get_res_of(struct omap_aes_dev * dd,struct device * dev,struct resource * res)954 static int omap_aes_get_res_of(struct omap_aes_dev *dd,
955 struct device *dev, struct resource *res)
956 {
957 struct device_node *node = dev->of_node;
958 int err = 0;
959
960 dd->pdata = of_device_get_match_data(dev);
961 if (!dd->pdata) {
962 dev_err(dev, "no compatible OF match\n");
963 err = -EINVAL;
964 goto err;
965 }
966
967 err = of_address_to_resource(node, 0, res);
968 if (err < 0) {
969 dev_err(dev, "can't translate OF node address\n");
970 err = -EINVAL;
971 goto err;
972 }
973
974 err:
975 return err;
976 }
977 #else
978 static const struct of_device_id omap_aes_of_match[] = {
979 {},
980 };
981
omap_aes_get_res_of(struct omap_aes_dev * dd,struct device * dev,struct resource * res)982 static int omap_aes_get_res_of(struct omap_aes_dev *dd,
983 struct device *dev, struct resource *res)
984 {
985 return -EINVAL;
986 }
987 #endif
988
omap_aes_get_res_pdev(struct omap_aes_dev * dd,struct platform_device * pdev,struct resource * res)989 static int omap_aes_get_res_pdev(struct omap_aes_dev *dd,
990 struct platform_device *pdev, struct resource *res)
991 {
992 struct device *dev = &pdev->dev;
993 struct resource *r;
994 int err = 0;
995
996 /* Get the base address */
997 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
998 if (!r) {
999 dev_err(dev, "no MEM resource info\n");
1000 err = -ENODEV;
1001 goto err;
1002 }
1003 memcpy(res, r, sizeof(*res));
1004
1005 /* Only OMAP2/3 can be non-DT */
1006 dd->pdata = &omap_aes_pdata_omap2;
1007
1008 err:
1009 return err;
1010 }
1011
fallback_show(struct device * dev,struct device_attribute * attr,char * buf)1012 static ssize_t fallback_show(struct device *dev, struct device_attribute *attr,
1013 char *buf)
1014 {
1015 return sprintf(buf, "%d\n", aes_fallback_sz);
1016 }
1017
fallback_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t size)1018 static ssize_t fallback_store(struct device *dev, struct device_attribute *attr,
1019 const char *buf, size_t size)
1020 {
1021 ssize_t status;
1022 long value;
1023
1024 status = kstrtol(buf, 0, &value);
1025 if (status)
1026 return status;
1027
1028 /* HW accelerator only works with buffers > 9 */
1029 if (value < 9) {
1030 dev_err(dev, "minimum fallback size 9\n");
1031 return -EINVAL;
1032 }
1033
1034 aes_fallback_sz = value;
1035
1036 return size;
1037 }
1038
queue_len_show(struct device * dev,struct device_attribute * attr,char * buf)1039 static ssize_t queue_len_show(struct device *dev, struct device_attribute *attr,
1040 char *buf)
1041 {
1042 struct omap_aes_dev *dd = dev_get_drvdata(dev);
1043
1044 return sprintf(buf, "%d\n", dd->engine->queue.max_qlen);
1045 }
1046
queue_len_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t size)1047 static ssize_t queue_len_store(struct device *dev,
1048 struct device_attribute *attr, const char *buf,
1049 size_t size)
1050 {
1051 struct omap_aes_dev *dd;
1052 ssize_t status;
1053 long value;
1054 unsigned long flags;
1055
1056 status = kstrtol(buf, 0, &value);
1057 if (status)
1058 return status;
1059
1060 if (value < 1)
1061 return -EINVAL;
1062
1063 /*
1064 * Changing the queue size in fly is safe, if size becomes smaller
1065 * than current size, it will just not accept new entries until
1066 * it has shrank enough.
1067 */
1068 spin_lock_bh(&list_lock);
1069 list_for_each_entry(dd, &dev_list, list) {
1070 spin_lock_irqsave(&dd->lock, flags);
1071 dd->engine->queue.max_qlen = value;
1072 dd->aead_queue.base.max_qlen = value;
1073 spin_unlock_irqrestore(&dd->lock, flags);
1074 }
1075 spin_unlock_bh(&list_lock);
1076
1077 return size;
1078 }
1079
1080 static DEVICE_ATTR_RW(queue_len);
1081 static DEVICE_ATTR_RW(fallback);
1082
1083 static struct attribute *omap_aes_attrs[] = {
1084 &dev_attr_queue_len.attr,
1085 &dev_attr_fallback.attr,
1086 NULL,
1087 };
1088 ATTRIBUTE_GROUPS(omap_aes);
1089
omap_aes_probe(struct platform_device * pdev)1090 static int omap_aes_probe(struct platform_device *pdev)
1091 {
1092 struct device *dev = &pdev->dev;
1093 struct omap_aes_dev *dd;
1094 struct skcipher_engine_alg *algp;
1095 struct aead_engine_alg *aalg;
1096 struct resource res;
1097 int err = -ENOMEM, i, j, irq = -1;
1098 u32 reg;
1099
1100 dd = devm_kzalloc(dev, sizeof(struct omap_aes_dev), GFP_KERNEL);
1101 if (dd == NULL) {
1102 dev_err(dev, "unable to alloc data struct.\n");
1103 goto err_data;
1104 }
1105 dd->dev = dev;
1106 platform_set_drvdata(pdev, dd);
1107
1108 aead_init_queue(&dd->aead_queue, OMAP_AES_QUEUE_LENGTH);
1109
1110 err = (dev->of_node) ? omap_aes_get_res_of(dd, dev, &res) :
1111 omap_aes_get_res_pdev(dd, pdev, &res);
1112 if (err)
1113 goto err_res;
1114
1115 dd->io_base = devm_ioremap_resource(dev, &res);
1116 if (IS_ERR(dd->io_base)) {
1117 err = PTR_ERR(dd->io_base);
1118 goto err_res;
1119 }
1120 dd->phys_base = res.start;
1121
1122 pm_runtime_use_autosuspend(dev);
1123 pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY);
1124
1125 pm_runtime_enable(dev);
1126 err = pm_runtime_resume_and_get(dev);
1127 if (err < 0) {
1128 dev_err(dev, "%s: failed to get_sync(%d)\n",
1129 __func__, err);
1130 goto err_pm_disable;
1131 }
1132
1133 omap_aes_dma_stop(dd);
1134
1135 reg = omap_aes_read(dd, AES_REG_REV(dd));
1136
1137 pm_runtime_put_sync(dev);
1138
1139 dev_info(dev, "OMAP AES hw accel rev: %u.%u\n",
1140 (reg & dd->pdata->major_mask) >> dd->pdata->major_shift,
1141 (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
1142
1143 tasklet_init(&dd->done_task, omap_aes_done_task, (unsigned long)dd);
1144
1145 err = omap_aes_dma_init(dd);
1146 if (err == -EPROBE_DEFER) {
1147 goto err_irq;
1148 } else if (err && AES_REG_IRQ_STATUS(dd) && AES_REG_IRQ_ENABLE(dd)) {
1149 dd->pio_only = 1;
1150
1151 irq = platform_get_irq(pdev, 0);
1152 if (irq < 0) {
1153 err = irq;
1154 goto err_irq;
1155 }
1156
1157 err = devm_request_irq(dev, irq, omap_aes_irq, 0,
1158 dev_name(dev), dd);
1159 if (err) {
1160 dev_err(dev, "Unable to grab omap-aes IRQ\n");
1161 goto err_irq;
1162 }
1163 }
1164
1165 spin_lock_init(&dd->lock);
1166
1167 INIT_LIST_HEAD(&dd->list);
1168 spin_lock_bh(&list_lock);
1169 list_add_tail(&dd->list, &dev_list);
1170 spin_unlock_bh(&list_lock);
1171
1172 /* Initialize crypto engine */
1173 dd->engine = crypto_engine_alloc_init(dev, 1);
1174 if (!dd->engine) {
1175 err = -ENOMEM;
1176 goto err_engine;
1177 }
1178
1179 err = crypto_engine_start(dd->engine);
1180 if (err)
1181 goto err_engine;
1182
1183 for (i = 0; i < dd->pdata->algs_info_size; i++) {
1184 if (!dd->pdata->algs_info[i].registered) {
1185 for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
1186 algp = &dd->pdata->algs_info[i].algs_list[j];
1187
1188 pr_debug("reg alg: %s\n", algp->base.base.cra_name);
1189
1190 err = crypto_engine_register_skcipher(algp);
1191 if (err)
1192 goto err_algs;
1193
1194 dd->pdata->algs_info[i].registered++;
1195 }
1196 }
1197 }
1198
1199 if (dd->pdata->aead_algs_info &&
1200 !dd->pdata->aead_algs_info->registered) {
1201 for (i = 0; i < dd->pdata->aead_algs_info->size; i++) {
1202 aalg = &dd->pdata->aead_algs_info->algs_list[i];
1203
1204 pr_debug("reg alg: %s\n", aalg->base.base.cra_name);
1205
1206 err = crypto_engine_register_aead(aalg);
1207 if (err)
1208 goto err_aead_algs;
1209
1210 dd->pdata->aead_algs_info->registered++;
1211 }
1212 }
1213
1214 return 0;
1215 err_aead_algs:
1216 for (i = dd->pdata->aead_algs_info->registered - 1; i >= 0; i--) {
1217 aalg = &dd->pdata->aead_algs_info->algs_list[i];
1218 crypto_engine_unregister_aead(aalg);
1219 }
1220 err_algs:
1221 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1222 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1223 crypto_engine_unregister_skcipher(
1224 &dd->pdata->algs_info[i].algs_list[j]);
1225
1226 err_engine:
1227 if (dd->engine)
1228 crypto_engine_exit(dd->engine);
1229
1230 omap_aes_dma_cleanup(dd);
1231 err_irq:
1232 tasklet_kill(&dd->done_task);
1233 err_pm_disable:
1234 pm_runtime_disable(dev);
1235 err_res:
1236 dd = NULL;
1237 err_data:
1238 dev_err(dev, "initialization failed.\n");
1239 return err;
1240 }
1241
omap_aes_remove(struct platform_device * pdev)1242 static void omap_aes_remove(struct platform_device *pdev)
1243 {
1244 struct omap_aes_dev *dd = platform_get_drvdata(pdev);
1245 struct aead_engine_alg *aalg;
1246 int i, j;
1247
1248 spin_lock_bh(&list_lock);
1249 list_del(&dd->list);
1250 spin_unlock_bh(&list_lock);
1251
1252 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1253 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) {
1254 crypto_engine_unregister_skcipher(
1255 &dd->pdata->algs_info[i].algs_list[j]);
1256 dd->pdata->algs_info[i].registered--;
1257 }
1258
1259 for (i = dd->pdata->aead_algs_info->registered - 1; i >= 0; i--) {
1260 aalg = &dd->pdata->aead_algs_info->algs_list[i];
1261 crypto_engine_unregister_aead(aalg);
1262 dd->pdata->aead_algs_info->registered--;
1263 }
1264
1265 crypto_engine_exit(dd->engine);
1266
1267 tasklet_kill(&dd->done_task);
1268 omap_aes_dma_cleanup(dd);
1269 pm_runtime_disable(dd->dev);
1270 }
1271
1272 #ifdef CONFIG_PM_SLEEP
omap_aes_suspend(struct device * dev)1273 static int omap_aes_suspend(struct device *dev)
1274 {
1275 pm_runtime_put_sync(dev);
1276 return 0;
1277 }
1278
omap_aes_resume(struct device * dev)1279 static int omap_aes_resume(struct device *dev)
1280 {
1281 pm_runtime_get_sync(dev);
1282 return 0;
1283 }
1284 #endif
1285
1286 static SIMPLE_DEV_PM_OPS(omap_aes_pm_ops, omap_aes_suspend, omap_aes_resume);
1287
1288 static struct platform_driver omap_aes_driver = {
1289 .probe = omap_aes_probe,
1290 .remove = omap_aes_remove,
1291 .driver = {
1292 .name = "omap-aes",
1293 .pm = &omap_aes_pm_ops,
1294 .of_match_table = omap_aes_of_match,
1295 .dev_groups = omap_aes_groups,
1296 },
1297 };
1298
1299 module_platform_driver(omap_aes_driver);
1300
1301 MODULE_DESCRIPTION("OMAP AES hw acceleration support.");
1302 MODULE_LICENSE("GPL v2");
1303 MODULE_AUTHOR("Dmitry Kasatkin");
1304
1305