1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2/* 3 * Copyright (C) 2020 PHYTEC Messtechnik GmbH 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/phy/phy-imx8-pcie.h> 9#include <dt-bindings/leds/leds-pca9532.h> 10#include <dt-bindings/thermal/thermal.h> 11#include "imx8mp-phycore-som.dtsi" 12 13/ { 14 model = "PHYTEC phyBOARD-Pollux i.MX8MP"; 15 compatible = "phytec,imx8mp-phyboard-pollux-rdk", 16 "phytec,imx8mp-phycore-som", "fsl,imx8mp"; 17 18 chosen { 19 stdout-path = &uart1; 20 }; 21 22 backlight_lvds1: backlight1 { 23 compatible = "pwm-backlight"; 24 pinctrl-0 = <&pinctrl_lvds1>; 25 pinctrl-names = "default"; 26 power-supply = <®_lvds1_reg_en>; 27 status = "disabled"; 28 }; 29 30 fan0: fan { 31 compatible = "gpio-fan"; 32 pinctrl-names = "default"; 33 pinctrl-0 = <&pinctrl_fan>; 34 fan-supply = <®_vcc_5v_sw>; 35 gpio-fan,speed-map = <0 0 36 13000 1>; 37 gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; 38 #cooling-cells = <2>; 39 }; 40 41 panel_lvds1: panel-lvds1 { 42 /* compatible panel in overlay */ 43 backlight = <&backlight_lvds1>; 44 power-supply = <®_vcc_3v3_sw>; 45 status = "disabled"; 46 47 port { 48 panel1_in: endpoint { 49 remote-endpoint = <&ldb_lvds_ch1>; 50 }; 51 }; 52 }; 53 54 reg_vcc_5v_sw: regulator-vcc-5v-sw { 55 compatible = "regulator-fixed"; 56 regulator-always-on; 57 regulator-boot-on; 58 regulator-max-microvolt = <5000000>; 59 regulator-min-microvolt = <5000000>; 60 regulator-name = "VCC_5V_SW"; 61 }; 62 63 reg_can1_stby: regulator-can1-stby { 64 compatible = "regulator-fixed"; 65 pinctrl-names = "default"; 66 pinctrl-0 = <&pinctrl_flexcan1_reg>; 67 gpio = <&gpio3 20 GPIO_ACTIVE_LOW>; 68 regulator-max-microvolt = <3300000>; 69 regulator-min-microvolt = <3300000>; 70 regulator-name = "can1-stby"; 71 }; 72 73 reg_can2_stby: regulator-can2-stby { 74 compatible = "regulator-fixed"; 75 pinctrl-names = "default"; 76 pinctrl-0 = <&pinctrl_flexcan2_reg>; 77 gpio = <&gpio3 21 GPIO_ACTIVE_LOW>; 78 regulator-max-microvolt = <3300000>; 79 regulator-min-microvolt = <3300000>; 80 regulator-name = "can2-stby"; 81 }; 82 83 reg_lvds1_reg_en: regulator-lvds1 { 84 compatible = "regulator-fixed"; 85 enable-active-high; 86 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; 87 regulator-max-microvolt = <1200000>; 88 regulator-min-microvolt = <1200000>; 89 regulator-name = "lvds1_reg_en"; 90 }; 91 92 reg_usb1_vbus: regulator-usb1-vbus { 93 compatible = "regulator-fixed"; 94 pinctrl-names = "default"; 95 pinctrl-0 = <&pinctrl_usb1_vbus>; 96 gpio = <&gpio1 12 GPIO_ACTIVE_LOW>; 97 regulator-max-microvolt = <5000000>; 98 regulator-min-microvolt = <5000000>; 99 regulator-name = "usb1_host_vbus"; 100 }; 101 102 reg_usdhc2_vmmc: regulator-usdhc2 { 103 compatible = "regulator-fixed"; 104 pinctrl-names = "default"; 105 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 106 regulator-name = "VSD_3V3"; 107 regulator-min-microvolt = <3300000>; 108 regulator-max-microvolt = <3300000>; 109 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 110 enable-active-high; 111 startup-delay-us = <100>; 112 off-on-delay-us = <12000>; 113 }; 114 115 reg_vcc_3v3_sw: regulator-vcc-3v3-sw { 116 compatible = "regulator-fixed"; 117 regulator-name = "VCC_3V3_SW"; 118 regulator-min-microvolt = <3300000>; 119 regulator-max-microvolt = <3300000>; 120 }; 121 122 reg_vcc_1v8_exp_con: regulator-vcc-1v8 { 123 compatible = "regulator-fixed"; 124 regulator-max-microvolt = <1800000>; 125 regulator-min-microvolt = <1800000>; 126 regulator-name = "VCC_1V8_EXP_CON"; 127 }; 128 129 thermal-zones { 130 soc-thermal { 131 trips { 132 active1: trip2 { 133 temperature = <60000>; 134 hysteresis = <2000>; 135 type = "active"; 136 }; 137 }; 138 139 cooling-maps { 140 map1 { 141 trip = <&active1>; 142 cooling-device = <&fan0 1 THERMAL_NO_LIMIT>; 143 }; 144 }; 145 }; 146 }; 147}; 148 149/* TPM */ 150&ecspi1 { 151 #address-cells = <1>; 152 #size-cells = <0>; 153 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 154 pinctrl-names = "default"; 155 pinctrl-0 = <&pinctrl_ecspi1>; 156 status = "okay"; 157 158 tpm: tpm@0 { 159 compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; 160 reg = <0>; 161 spi-max-frequency = <38000000>; 162 }; 163}; 164 165&eqos { 166 pinctrl-names = "default"; 167 pinctrl-0 = <&pinctrl_eqos>; 168 phy-mode = "rgmii-id"; 169 phy-handle = <ðphy0>; 170 status = "okay"; 171 172 mdio { 173 compatible = "snps,dwmac-mdio"; 174 #address-cells = <1>; 175 #size-cells = <0>; 176 177 ethphy0: ethernet-phy@1 { 178 compatible = "ethernet-phy-ieee802.3-c22"; 179 reg = <0x1>; 180 ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>; 181 ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>; 182 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 183 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 184 enet-phy-lane-no-swap; 185 }; 186 }; 187}; 188 189/* CAN FD */ 190&flexcan1 { 191 pinctrl-names = "default"; 192 pinctrl-0 = <&pinctrl_flexcan1>; 193 xceiver-supply = <®_can1_stby>; 194 status = "okay"; 195}; 196 197&flexcan2 { 198 pinctrl-names = "default"; 199 pinctrl-0 = <&pinctrl_flexcan2>; 200 xceiver-supply = <®_can2_stby>; 201 status = "okay"; 202}; 203 204&i2c2 { 205 clock-frequency = <400000>; 206 pinctrl-names = "default", "gpio"; 207 pinctrl-0 = <&pinctrl_i2c2>; 208 pinctrl-1 = <&pinctrl_i2c2_gpio>; 209 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 210 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 211 status = "okay"; 212 213 eeprom@51 { 214 compatible = "atmel,24c02"; 215 reg = <0x51>; 216 pagesize = <16>; 217 vcc-supply = <®_vcc_3v3_sw>; 218 }; 219 220 leds@62 { 221 compatible = "nxp,pca9533"; 222 reg = <0x62>; 223 224 led-1 { 225 type = <PCA9532_TYPE_LED>; 226 }; 227 228 led-2 { 229 type = <PCA9532_TYPE_LED>; 230 }; 231 232 led-3 { 233 type = <PCA9532_TYPE_LED>; 234 }; 235 }; 236}; 237 238&i2c3 { 239 clock-frequency = <400000>; 240 pinctrl-names = "default", "gpio"; 241 pinctrl-0 = <&pinctrl_i2c3>; 242 pinctrl-1 = <&pinctrl_i2c3_gpio>; 243 sda-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 244 scl-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 245}; 246 247&ldb_lvds_ch1 { 248 remote-endpoint = <&panel1_in>; 249}; 250 251&snvs_pwrkey { 252 status = "okay"; 253}; 254 255&pcie_phy { 256 clocks = <&hsio_blk_ctrl>; 257 clock-names = "ref"; 258 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; 259 fsl,clkreq-unsupported; 260 status = "okay"; 261}; 262 263/* Mini PCIe */ 264&pcie { 265 pinctrl-names = "default"; 266 pinctrl-0 = <&pinctrl_pcie0>; 267 reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; 268 vpcie-supply = <®_vcc_3v3_sw>; 269 status = "okay"; 270}; 271 272&pwm3 { 273 pinctrl-0 = <&pinctrl_pwm3>; 274 pinctrl-names = "default"; 275}; 276 277&rv3028 { 278 pinctrl-names = "default"; 279 pinctrl-0 = <&pinctrl_rtc>; 280 interrupt-parent = <&gpio4>; 281 interrupts = <19 IRQ_TYPE_LEVEL_LOW>; 282 aux-voltage-chargeable = <1>; 283 wakeup-source; 284 trickle-resistor-ohms = <3000>; 285}; 286 287/* debug console */ 288&uart1 { 289 pinctrl-names = "default"; 290 pinctrl-0 = <&pinctrl_uart1>; 291 status = "okay"; 292}; 293 294/* USB1 Host mode Type-A */ 295&usb3_phy0 { 296 vbus-supply = <®_usb1_vbus>; 297 status = "okay"; 298}; 299 300&usb3_0 { 301 status = "okay"; 302}; 303 304&usb_dwc3_0 { 305 dr_mode = "host"; 306 status = "okay"; 307}; 308 309/* USB2 4-port USB3.0 HUB */ 310&usb3_phy1 { 311 vbus-supply = <®_vcc_5v_sw>; 312 status = "okay"; 313}; 314 315&usb3_1 { 316 fsl,permanently-attached; 317 fsl,disable-port-power-control; 318 status = "okay"; 319}; 320 321&usb_dwc3_1 { 322 dr_mode = "host"; 323 status = "okay"; 324}; 325 326/* RS232/RS485 */ 327&uart2 { 328 assigned-clocks = <&clk IMX8MP_CLK_UART2>; 329 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 330 pinctrl-names = "default"; 331 pinctrl-0 = <&pinctrl_uart2>; 332 uart-has-rtscts; 333 status = "okay"; 334}; 335 336/* SD-Card */ 337&usdhc2 { 338 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; 339 assigned-clock-rates = <200000000>; 340 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 341 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_pins>; 342 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_pins>; 343 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_pins>; 344 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 345 disable-wp; 346 vmmc-supply = <®_usdhc2_vmmc>; 347 vqmmc-supply = <&ldo5>; 348 bus-width = <4>; 349 status = "okay"; 350}; 351 352&gpio1 { 353 gpio-line-names = "", "", "X_PMIC_WDOG_B", "", 354 "PMIC_SD_VSEL", "", "", "", "PCIe_nPERST", "LVDS1REG_EN", 355 "PCIe_nWAKE", "PCIe_nCLKREQ", "USB1_OTG_PWR", "", 356 "PCIe_nW_DISABLE"; 357}; 358 359&gpio2 { 360 gpio-line-names = "", "", "", "", 361 "", "", "", "", "", "", 362 "", "", "X_SD2_CD_B", "", "", "", 363 "", "", "", "SD2_RESET_B", "LVDS1_BL_EN"; 364}; 365 366&gpio3 { 367 gpio-line-names = "", "", "", "", 368 "", "", "", "", "", "", 369 "", "", "", "", "", "", 370 "", "", "", "", "nCAN1_EN", "nCAN2_EN"; 371}; 372 373&gpio4 { 374 gpio-line-names = "", "", "", "", 375 "", "", "", "", "", "", 376 "", "", "", "", "", "", 377 "", "", "X_PMIC_IRQ_B", "nRTC_INT", "nENET0_INT_PWDN"; 378}; 379 380&gpio5 { 381 gpio-line-names = "", "", "", "", 382 "", "", "", "", "", "X_ECSPI1_SSO"; 383}; 384 385&iomuxc { 386 pinctrl_ecspi1: ecspi1grp { 387 fsl,pins = < 388 MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x80 389 MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x80 390 MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x80 391 MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x00 392 >; 393 }; 394 395 pinctrl_eqos: eqosgrp { 396 fsl,pins = < 397 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 398 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 399 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 400 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 401 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 402 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 403 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 404 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 405 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x12 406 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x12 407 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x12 408 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x12 409 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x12 410 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x12 411 MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x10 412 >; 413 }; 414 415 pinctrl_fan: fan0grp { 416 fsl,pins = < 417 MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x16 418 >; 419 }; 420 421 pinctrl_flexcan1: flexcan1grp { 422 fsl,pins = < 423 MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x154 424 MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x154 425 >; 426 }; 427 428 pinctrl_flexcan2: flexcan2grp { 429 fsl,pins = < 430 MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 431 MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 432 >; 433 }; 434 435 pinctrl_flexcan1_reg: flexcan1reggrp { 436 fsl,pins = < 437 MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x154 438 >; 439 }; 440 441 pinctrl_flexcan2_reg: flexcan2reggrp { 442 fsl,pins = < 443 MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x154 444 >; 445 }; 446 447 pinctrl_i2c2: i2c2grp { 448 fsl,pins = < 449 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 450 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 451 >; 452 }; 453 454 pinctrl_i2c2_gpio: i2c2gpiogrp { 455 fsl,pins = < 456 MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1e2 457 MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1e2 458 >; 459 }; 460 461 pinctrl_i2c3: i2c3grp { 462 fsl,pins = < 463 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 464 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 465 >; 466 }; 467 468 pinctrl_i2c3_gpio: i2c3gpiogrp { 469 fsl,pins = < 470 MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x1e2 471 MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x1e2 472 >; 473 }; 474 475 pinctrl_lvds1: lvds1grp { 476 fsl,pins = < 477 MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x12 478 >; 479 }; 480 481 pinctrl_pcie0: pcie0grp { 482 fsl,pins = < 483 MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x40 484 MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x60 485 MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x60 /* open drain, pull up */ 486 MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x40 487 >; 488 }; 489 490 pinctrl_pwm3: pwm3grp { 491 fsl,pins = < 492 MX8MP_IOMUXC_SPDIF_TX__PWM3_OUT 0x12 493 >; 494 }; 495 496 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 497 fsl,pins = < 498 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 499 >; 500 }; 501 502 pinctrl_rtc: rtcgrp { 503 fsl,pins = < 504 MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x1c0 505 >; 506 }; 507 508 pinctrl_uart1: uart1grp { 509 fsl,pins = < 510 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 511 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 512 >; 513 }; 514 515 pinctrl_usb1_vbus: usb1vbusgrp { 516 fsl,pins = < 517 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x10 518 >; 519 }; 520 521 pinctrl_uart2: uart2grp { 522 fsl,pins = < 523 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 524 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 525 MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS 0x140 526 MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS 0x140 527 >; 528 }; 529 530 pinctrl_usdhc2_pins: usdhc2-gpiogrp { 531 fsl,pins = < 532 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x40 533 >; 534 }; 535 536 pinctrl_usdhc2: usdhc2grp { 537 fsl,pins = < 538 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 539 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 540 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 541 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 542 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 543 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 544 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 545 >; 546 }; 547 548 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 549 fsl,pins = < 550 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 551 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 552 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 553 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 554 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 555 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 556 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 557 >; 558 }; 559 560 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 561 fsl,pins = < 562 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 563 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 564 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 565 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 566 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 567 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 568 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 569 >; 570 }; 571}; 572