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/linux/drivers/clk/sprd/
H A Dgate.h31 #define SPRD_SC_GATE_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \ argument
47 #define SPRD_SC_GATE_CLK_OPS_UDELAY(_struct, _name, _parent, _reg, \ argument
54 #define SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, _sc_offset, \ argument
60 #define SPRD_SC_GATE_CLK(_struct, _name, _parent, _reg, _sc_offset, \ argument
66 #define SPRD_GATE_CLK(_struct, _name, _parent, _reg, \ argument
72 SPRD_PLL_SC_GATE_CLK(_struct,_name,_parent,_reg,_sc_offset,_enable_mask,_flags,_gate_flags,_udelay) global() argument
81 SPRD_SC_GATE_CLK_HW_OPS_UDELAY(_struct,_name,_parent,_reg,_sc_offset,_enable_mask,_flags,_gate_flags,_udelay,_ops) global() argument
90 SPRD_SC_GATE_CLK_HW_OPS(_struct,_name,_parent,_reg,_sc_offset,_enable_mask,_flags,_gate_flags,_ops) global() argument
97 SPRD_SC_GATE_CLK_HW(_struct,_name,_parent,_reg,_sc_offset,_enable_mask,_flags,_gate_flags) global() argument
104 SPRD_GATE_CLK_HW(_struct,_name,_parent,_reg,_enable_mask,_flags,_gate_flags) global() argument
110 SPRD_PLL_SC_GATE_CLK_HW(_struct,_name,_parent,_reg,_sc_offset,_enable_mask,_flags,_gate_flags,_udelay) global() argument
119 SPRD_SC_GATE_CLK_FW_NAME_OPS_UDELAY(_struct,_name,_parent,_reg,_sc_offset,_enable_mask,_flags,_gate_flags,_udelay,_ops) global() argument
127 SPRD_SC_GATE_CLK_FW_NAME_OPS(_struct,_name,_parent,_reg,_sc_offset,_enable_mask,_flags,_gate_flags,_ops) global() argument
135 SPRD_SC_GATE_CLK_FW_NAME(_struct,_name,_parent,_reg,_sc_offset,_enable_mask,_flags,_gate_flags) global() argument
142 SPRD_GATE_CLK_FW_NAME(_struct,_name,_parent,_reg,_enable_mask,_flags,_gate_flags) global() argument
148 SPRD_PLL_SC_GATE_CLK_FW_NAME(_struct,_name,_parent,_reg,_sc_offset,_enable_mask,_flags,_gate_flags,_udelay) global() argument
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H A Dcomposite.h21 #define SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \ argument
35 #define SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, _table, \ argument
41 #define SPRD_COMP_CLK(_struct, _name, _parent, _reg, _mshift, \ argument
46 #define SPRD_COMP_CLK_DATA_TABLE(_struct, _name, _parent, _reg, _table, \ argument
54 #define SPRD_COMP_CLK_DATA(_struct, _name, _parent, _reg, _mshift, \ argument
60 SPRD_COMP_CLK_DATA_TABLE_OFFSET(_struct,_name,_parent,_reg,_table,_mshift,_mwidth,_doffset,_dshift,_dwidth,_flags) global() argument
69 SPRD_COMP_CLK_DATA_OFFSET(_struct,_name,_parent,_reg,_mshift,_mwidth,_doffset,_dshift,_dwidth,_flags) global() argument
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H A Dmux.h40 _reg, _shift, _width, _flags, _fn) \ argument
52 _reg, _shift, _width, _flags) \ argument
57 #define SPRD_MUX_CLK(_struct, _name, _parents, _reg, \ argument
63 _reg, _shift, _width, _flags) \ argument
68 #define SPRD_MUX_CLK_DATA(_struct, _name, _parents, _reg, \ argument
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H A Ddiv.h40 #define SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _offset, \ argument
52 #define SPRD_DIV_CLK(_struct, _name, _parent, _reg, \ argument
57 #define SPRD_DIV_CLK_FW_NAME(_struct, _name, _parent, _reg, \ argument
62 #define SPRD_DIV_CLK_HW(_struct, _name, _parent, _reg, \ argument
H A Dpll.h64 #define SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, \ argument
85 #define SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \ argument
92 #define SPRD_PLL_WITH_ITABLE_K(_struct, _name, _parent, _reg, \ argument
99 #define SPRD_PLL_WITH_ITABLE_1K(_struct, _name, _parent, _reg, \ argument
105 #define SPRD_PLL_FW_NAME(_struct, _name, _parent, _reg, _regs_num, \ argument
112 SPRD_PLL_HW(_struct,_name,_parent,_reg,_regs_num,_itable,_factors,_udelay,_k1,_k2,_fflag,_fvco) global() argument
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/linux/drivers/clk/sophgo/
H A Dclk-cv18xx-pll.h50 #define PLL_GET_PRE_DIV_SEL(_reg) \ argument
52 #define PLL_GET_POST_DIV_SEL(_reg) \ argument
54 #define PLL_GET_SEL_MODE(_reg) \ argument
56 #define PLL_GET_DIV_SEL(_reg) \ argument
58 #define PLL_GET_ICTRL(_reg) \ argument
61 PLL_SET_PRE_DIV_SEL(_reg,_val) global() argument
63 PLL_SET_POST_DIV_SEL(_reg,_val) global() argument
65 PLL_SET_SEL_MODE(_reg,_val) global() argument
67 PLL_SET_DIV_SEL(_reg,_val) global() argument
69 PLL_SET_ICTRL(_reg,_val) global() argument
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H A Dclk-cv18xx-common.h45 #define CV1800_CLK_BIT(_reg, _shift) \ argument
51 #define CV1800_CLK_REG(_reg, _shift, _width, _initval, _flags) \ argument
60 #define cv1800_clk_regfield_genmask(_reg) \ argument
62 #define cv1800_clk_regfield_get(_val, _reg) \ argument
64 cv1800_clk_regfield_set(_val,_new,_reg) global() argument
68 _CV1800_SET_FIELD(_reg,_val,_field) global() argument
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/linux/drivers/clk/meson/
H A Daxg-audio.c80 #define AUD_GATE(_name, _reg, _bit, _pname, _iflags) { \ argument
94 #define AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pdata, _iflags) { \ argument
110 #define AUD_DIV(_name, _reg, _shift, _width, _dflags, _pname, _iflags) { \ argument
126 #define AUD_PCLK_GATE(_name, _reg, _bit) { \ argument
139 #define AUD_SCLK_DIV(_name, _reg, _div_shift, _div_width, \ argument
162 AUD_TRIPHASE(_name,_reg,_width,_shift0,_shift1,_shift2,_pname,_iflags) global() argument
190 AUD_PHASE(_name,_reg,_width,_shift,_pname,_iflags) global() argument
207 AUD_SCLK_WS(_name,_reg,_width,_shift_ph,_shift_ws,_pname,_iflags) global() argument
242 AUD_MST_MUX(_name,_reg,_flag) global() argument
245 AUD_MST_DIV(_name,_reg,_flag) global() argument
248 AUD_MST_MCLK_GATE(_name,_reg) global() argument
252 AUD_MST_MCLK_MUX(_name,_reg) global() argument
254 AUD_MST_MCLK_DIV(_name,_reg) global() argument
257 AUD_MST_SYS_MUX(_name,_reg) global() argument
259 AUD_MST_SYS_DIV(_name,_reg) global() argument
263 AUD_MST_SCLK_PRE_EN(_name,_reg) global() argument
266 AUD_MST_SCLK_DIV(_name,_reg) global() argument
270 AUD_MST_SCLK_POST_EN(_name,_reg) global() argument
273 AUD_MST_SCLK(_name,_reg) global() argument
277 AUD_MST_LRCLK_DIV(_name,_reg) global() argument
280 AUD_MST_LRCLK(_name,_reg) global() argument
324 AUD_TDM_SCLK_MUX(_name,_reg) global() argument
327 AUD_TDM_SCLK_PRE_EN(_name,_reg) global() argument
330 AUD_TDM_SCLK_POST_EN(_name,_reg) global() argument
333 AUD_TDM_SCLK(_name,_reg) global() argument
337 AUD_TDM_SCLK_WS(_name,_reg) global() argument
342 AUD_TDM_LRLCK(_name,_reg) global() argument
376 AUD_TDM_PAD_CTRL(_name,_reg,_shift,_parents) global() argument
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H A Dclk-regmap.h121 #define __MESON_PCLK(_name, _reg, _bit, _ops, _pname) \ argument
136 #define MESON_PCLK(_name, _reg, _bit, _pname) \ argument
139 #define MESON_PCLK_RO(_name, _reg, _bit, _pname) \ argument
H A Dc3-peripherals.c167 #define C3_CLK_GATE(_name, _reg, _bit, _fw_name, _ops, _flags) \ argument
184 #define C3_SYS_GATE(_name, _reg, _bit, _flags) \ argument
188 #define C3_SYS_GATE_RO(_name, _reg, _bit) \ argument
293 #define C3_AXI_GATE(_name, _reg, _bit, _flags) \ argument
532 #define AML_PWM_CLK_MUX(_name, _reg, _shift) { \ argument
546 AML_PWM_CLK_DIV(_name,_reg,_shift) global() argument
561 AML_PWM_CLK_GATE(_name,_reg,_bit) global() argument
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/linux/drivers/clk/sunxi-ng/
H A Dccu_gate.h19 #define SUNXI_CCU_GATE(_struct, _name, _parent, _reg, _gate, _flags) \ argument
31 #define SUNXI_CCU_GATE_HW(_struct, _name, _parent, _reg, _gate, _flags) \ argument
43 #define SUNXI_CCU_GATE_FW(_struct, _name, _parent, _reg, _gate, _flags) \ argument
59 #define SUNXI_CCU_GATE_HWS(_struct, _name, _parent, _reg, _gate, _flags) \ argument
71 #define SUNXI_CCU_GATE_HWS_WITH_PREDIV(_struct, _name, _parent, _reg, \ argument
86 SUNXI_CCU_GATE_DATA(_struct,_name,_data,_reg,_gate,_flags) global() argument
99 SUNXI_CCU_GATE_DATA_WITH_PREDIV(_struct,_name,_parent,_reg,_gate,_prediv,_flags) global() argument
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H A Dccu_div.h87 #define SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \ argument
104 #define SUNXI_CCU_DIV_TABLE(_struct, _name, _parent, _reg, \ argument
111 #define SUNXI_CCU_DIV_TABLE_HW(_struct, _name, _parent, _reg, \ argument
129 _reg, \ argument
148 _reg, \ argument
166 SUNXI_CCU_M_WITH_MUX_GATE(_struct,_name,_parents,_reg,_mshift,_mwidth,_muxshift,_muxwidth,_gate,_flags) global() argument
176 SUNXI_CCU_M_WITH_MUX_GATE_CLOSEST(_struct,_name,_parents,_reg,_mshift,_mwidth,_muxshift,_muxwidth,_gate,_flags) global() argument
185 SUNXI_CCU_M_WITH_MUX(_struct,_name,_parents,_reg,_mshift,_mwidth,_muxshift,_muxwidth,_flags) global() argument
195 SUNXI_CCU_M_WITH_GATE(_struct,_name,_parent,_reg,_mshift,_mwidth,_gate,_flags) global() argument
210 SUNXI_CCU_M(_struct,_name,_parent,_reg,_mshift,_mwidth,_flags) global() argument
215 SUNXI_CCU_M_DATA_WITH_MUX_GATE(_struct,_name,_parents,_reg,_mshift,_mwidth,_muxshift,_muxwidth,_gate,_flags) global() argument
232 SUNXI_CCU_M_DATA_WITH_MUX(_struct,_name,_parents,_reg,_mshift,_mwidth,_muxshift,_muxwidth,_flags) global() argument
241 SUNXI_CCU_M_HW_WITH_MUX_GATE(_struct,_name,_parents,_reg,_mshift,_mwidth,_muxshift,_muxwidth,_gate,_flags) global() argument
257 SUNXI_CCU_M_HWS_WITH_GATE(_struct,_name,_parent,_reg,_mshift,_mwidth,_gate,_flags) global() argument
272 SUNXI_CCU_M_HWS(_struct,_name,_parent,_reg,_mshift,_mwidth,_flags) global() argument
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H A Dccu_mp.h34 #define SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(_struct, _name, _parents, _reg, \ argument
56 _reg, \ argument
77 #define SUNXI_CCU_MP_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
96 #define SUNXI_CCU_MP_WITH_MUX(_struct, _name, _parents, _reg, \ argument
107 #define SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(_struct, _name, _parents, _reg, \ argument
130 SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(_struct,_name,_parents,_reg,_mshift,_mwidth,_pshift,_pwidth,_muxshift,_muxwidth,_gate,_flags,_features) global() argument
150 SUNXI_CCU_MP_DATA_WITH_MUX_GATE(_struct,_name,_parents,_reg,_mshift,_mwidth,_pshift,_pwidth,_muxshift,_muxwidth,_gate,_flags) global() argument
161 SUNXI_CCU_DUALDIV_MUX_GATE(_struct,_name,_parents,_reg,_mshift,_mwidth,_pshift,_pwidth,_muxshift,_muxwidth,_gate,_flags) global() argument
173 SUNXI_CCU_MP_DATA_WITH_MUX(_struct,_name,_parents,_reg,_mshift,_mwidth,_pshift,_pwidth,_muxshift,_muxwidth,_flags) global() argument
184 SUNXI_CCU_MP_HW_WITH_MUX_GATE(_struct,_name,_parents,_reg,_mshift,_mwidth,_pshift,_pwidth,_muxshift,_muxwidth,_gate,_flags) global() argument
221 SUNXI_CCU_MP_MMC_WITH_MUX_GATE(_struct,_name,_parents,_reg,_flags) global() argument
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H A Dccu_mux.h50 _reg, _shift, _width, _gate, \ argument
66 _table, _reg, _shift, \ argument
74 _reg, _shift, _width, _gate, \ argument
80 #define SUNXI_CCU_MUX_WITH_GATE(_struct, _name, _parents, _reg, \ argument
86 #define SUNXI_CCU_MUX(_struct, _name, _parents, _reg, _shift, _width, \ argument
91 SUNXI_CCU_MUX_DATA_WITH_GATE(_struct,_name,_parents,_reg,_shift,_width,_gate,_flags) global() argument
105 SUNXI_CCU_MUX_DATA(_struct,_name,_parents,_reg,_shift,_width,_flags) global() argument
110 SUNXI_CCU_MUX_HW_WITH_GATE(_struct,_name,_parents,_reg,_shift,_width,_gate,_flags) global() argument
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H A Dccu_nm.h38 #define SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
61 #define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
86 _reg, _min_rate, \ argument
112 _parent, _reg, \ argument
142 _parent, _reg, \ argument
162 SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX_CLOSEST(_struct,_name,_parent,_reg,_min_rate,_max_rate,_nshift,_nwidth,_mshift,_mwidth,_frac_en,_frac_sel,_frac_rate_0,_frac_rate_1,_gate,_lock,_flags) global() argument
182 SUNXI_CCU_NM_WITH_GATE_LOCK(_struct,_name,_parent,_reg,_nshift,_nwidth,_mshift,_mwidth,_gate,_lock,_flags) global() argument
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/linux/arch/mips/include/asm/mach-pic32/
H A Dpic32.h14 #define PIC32_CLR(_reg) ((_reg) + 0x04) argument
15 #define PIC32_SET(_reg) ((_reg) + 0x08) argument
16 #define PIC32_INV(_reg) ((_reg) + 0x0C) argument
/linux/drivers/regulator/
H A Dmc13xxx.h55 #define MC13xxx_DEFINE(prefix, _name, _node, _reg, _vsel_reg, _voltages, _ops) \ argument
73 #define MC13xxx_FIXED_DEFINE(prefix, _name, _node, _reg, _voltages, _ops) \ argument
88 #define MC13xxx_GPO_DEFINE(prefix, _name, _node, _reg, _voltages, _ops) \ argument
103 #define MC13xxx_DEFINE_SW(_name, _node, _reg, _vsel_re argument
105 MC13xxx_DEFINE_REGU(_name,_node,_reg,_vsel_reg,_voltages,ops) global() argument
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/linux/drivers/clk/actions/
H A Dowl-gate.h27 #define OWL_GATE_HW(_reg, _bit_idx, _gate_flags) \ argument
34 #define OWL_GATE(_struct, _name, _parent, _reg, \ argument
47 #define OWL_GATE_NO_PARENT(_struct, _name, _reg, \ argument
H A Dowl-pll.h41 #define OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \ argument
55 #define OWL_PLL(_struct, _name, _parent, _reg, _bfreq, _bit_idx, \ argument
70 #define OWL_PLL_NO_PARENT(_struct, _name, _reg, _bfreq, _bit_idx, \ argument
84 #define OWL_PLL_NO_PARENT_DELAY(_struct, _name, _reg, _bfreq, _bit_idx, \ argument
H A Dowl-mux.h27 #define OWL_MUX_HW(_reg, _shift, _width) \ argument
34 #define OWL_MUX(_struct, _name, _parents, _reg, \ argument
/linux/drivers/clk/pistachio/
H A Dclk.h19 #define GATE(_id, _name, _pname, _reg, _shift) \ argument
39 #define MUX(_id, _name, _pnames, _reg, _shift) \ argument
59 #define DIV(_id, _name, _pname, _reg, _width) \ argument
69 #define DIV_F(_id, _name, _pname, _reg, _width, _div_flags) \ argument
119 #define PLL(_id, _name, _pname, _type, _reg, _rates) \ argument
130 PLL_FIXED(_id,_name,_pname,_type,_reg) global() argument
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/linux/drivers/reset/sti/
H A Dreset-stih407.c57 #define STIH407_SRST_CORE(_reg, _bit) \ argument
60 #define STIH407_SRST_SBC(_reg, _bit) \ argument
63 #define STIH407_SRST_LPM(_reg, _bit) \ argument
/linux/drivers/clk/mediatek/
H A Dclk-mt8167-apmixedsys.c22 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
42 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
77 #define DIV_ADJ_FLAG(_id, _name, _parent, _reg, _shift, _width, _flag) { \ argument
/linux/drivers/net/ethernet/amd/xgbe/
H A Dxgbe-common.h1418 #define XGMAC_IOREAD(_pdata, _reg) \ argument
1421 #define XGMAC_IOREAD_BITS(_pdata, _reg, _field) \ argument
1426 #define XGMAC_IOWRITE(_pdata, _reg, _val) \ argument
1429 #define XGMAC_IOWRITE_BITS(_pdata, _reg, _field, _val) \ argument
1442 XGMAC_MTL_IOREAD(_pdata,_n,_reg) global() argument
1446 XGMAC_MTL_IOREAD_BITS(_pdata,_n,_reg,_field) global() argument
1451 XGMAC_MTL_IOWRITE(_pdata,_n,_reg,_val) global() argument
1455 XGMAC_MTL_IOWRITE_BITS(_pdata,_n,_reg,_field,_val) global() argument
1468 XGMAC_DMA_IOREAD(_channel,_reg) global() argument
1471 XGMAC_DMA_IOREAD_BITS(_channel,_reg,_field) global() argument
1476 XGMAC_DMA_IOWRITE(_channel,_reg,_val) global() argument
1479 XGMAC_DMA_IOWRITE_BITS(_channel,_reg,_field,_val) global() argument
1526 XSIR0_IOREAD(_pdata,_reg) global() argument
1529 XSIR0_IOREAD_BITS(_pdata,_reg,_field) global() argument
1534 XSIR0_IOWRITE(_pdata,_reg,_val) global() argument
1537 XSIR0_IOWRITE_BITS(_pdata,_reg,_field,_val) global() argument
1546 XSIR1_IOREAD(_pdata,_reg) global() argument
1549 XSIR1_IOREAD_BITS(_pdata,_reg,_field) global() argument
1554 XSIR1_IOWRITE(_pdata,_reg,_val) global() argument
1557 XSIR1_IOWRITE_BITS(_pdata,_reg,_field,_val) global() argument
1569 XRXTX_IOREAD(_pdata,_reg) global() argument
1572 XRXTX_IOREAD_BITS(_pdata,_reg,_field) global() argument
1577 XRXTX_IOWRITE(_pdata,_reg,_val) global() argument
1580 XRXTX_IOWRITE_BITS(_pdata,_reg,_field,_val) global() argument
1602 XP_IOREAD(_pdata,_reg) global() argument
1605 XP_IOREAD_BITS(_pdata,_reg,_field) global() argument
1610 XP_IOWRITE(_pdata,_reg,_val) global() argument
1613 XP_IOWRITE_BITS(_pdata,_reg,_field,_val) global() argument
1635 XI2C_IOREAD(_pdata,_reg) global() argument
1638 XI2C_IOREAD_BITS(_pdata,_reg,_field) global() argument
1643 XI2C_IOWRITE(_pdata,_reg,_val) global() argument
1646 XI2C_IOWRITE_BITS(_pdata,_reg,_field,_val) global() argument
1661 XMDIO_READ(_pdata,_mmd,_reg) global() argument
1665 XMDIO_READ_BITS(_pdata,_mmd,_reg,_mask) global() argument
1668 XMDIO_WRITE(_pdata,_mmd,_reg,_val) global() argument
1672 XMDIO_WRITE_BITS(_pdata,_mmd,_reg,_mask,_val) global() argument
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/linux/drivers/dpll/zl3073x/
H A Dregs.h30 #define ZL_REG_OFFSET(_reg) FIELD_GET(ZL_REG_OFFSET_MASK, _reg) argument
31 #define ZL_REG_PAGE(_reg) FIELD_GET(ZL_REG_PAGE_MASK, _reg) argument
32 #define ZL_REG_MAX_OFFSET(_reg) FIELD_GET(ZL_REG_MAX_OFFSET_MASK, _reg) argument
33 #define ZL_REG_SIZE(_reg) FIELD_GET(ZL_REG_SIZE_MASK, _reg) argument
34 #define ZL_REG_ADDR(_reg) FIELD_GET(ZL_REG_ADDR_MASK, _reg) argument
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