1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * dwmac-sti.c - STMicroelectronics DWMAC Specific Glue layer
4 *
5 * Copyright (C) 2003-2014 STMicroelectronics (R&D) Limited
6 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
7 * Contributors: Giuseppe Cavallaro <peppe.cavallaro@st.com>
8 */
9
10 #include <linux/kernel.h>
11 #include <linux/slab.h>
12 #include <linux/platform_device.h>
13 #include <linux/stmmac.h>
14 #include <linux/phy.h>
15 #include <linux/mfd/syscon.h>
16 #include <linux/module.h>
17 #include <linux/regmap.h>
18 #include <linux/clk.h>
19 #include <linux/of.h>
20 #include <linux/of_net.h>
21
22 #include "stmmac_platform.h"
23
24 #define DWMAC_50MHZ 50000000
25
26 #define IS_PHY_IF_MODE_GBIT(iface) (phy_interface_mode_is_rgmii(iface) || \
27 iface == PHY_INTERFACE_MODE_GMII)
28
29 /* STiH4xx register definitions (STiH407/STiH410 families)
30 *
31 * Below table summarizes the clock requirement and clock sources for
32 * supported phy interface modes with link speeds.
33 * ________________________________________________
34 *| PHY_MODE | 1000 Mbit Link | 100 Mbit Link |
35 * ------------------------------------------------
36 *| MII | n/a | 25Mhz |
37 *| | | txclk |
38 * ------------------------------------------------
39 *| GMII | 125Mhz | 25Mhz |
40 *| | clk-125/txclk | txclk |
41 * ------------------------------------------------
42 *| RGMII | 125Mhz | 25Mhz |
43 *| | clk-125/txclk | clkgen |
44 *| | clkgen | |
45 * ------------------------------------------------
46 *| RMII | n/a | 25Mhz |
47 *| | |clkgen/phyclk-in |
48 * ------------------------------------------------
49 *
50 * Register Configuration
51 *-------------------------------
52 * src |BIT(8)| BIT(7)| BIT(6)|
53 *-------------------------------
54 * txclk | 0 | n/a | 1 |
55 *-------------------------------
56 * ck_125| 0 | n/a | 0 |
57 *-------------------------------
58 * phyclk| 1 | 0 | n/a |
59 *-------------------------------
60 * clkgen| 1 | 1 | n/a |
61 *-------------------------------
62 */
63
64 #define STIH4XX_RETIME_SRC_MASK GENMASK(8, 6)
65 #define STIH4XX_ETH_SEL_TX_RETIME_CLK BIT(8)
66 #define STIH4XX_ETH_SEL_INTERNAL_NOTEXT_PHYCLK BIT(7)
67 #define STIH4XX_ETH_SEL_TXCLK_NOT_CLK125 BIT(6)
68
69 #define ENMII_MASK GENMASK(5, 5)
70 #define ENMII BIT(5)
71 #define EN_MASK GENMASK(1, 1)
72 #define EN BIT(1)
73
74 /*
75 * 3 bits [4:2]
76 * 000-GMII/MII
77 * 001-RGMII
78 * 010-SGMII
79 * 100-RMII
80 */
81 #define MII_PHY_SEL_MASK GENMASK(4, 2)
82 #define ETH_PHY_SEL_RMII BIT(4)
83 #define ETH_PHY_SEL_SGMII BIT(3)
84 #define ETH_PHY_SEL_RGMII BIT(2)
85 #define ETH_PHY_SEL_GMII 0x0
86 #define ETH_PHY_SEL_MII 0x0
87
88 struct sti_dwmac {
89 phy_interface_t interface; /* MII interface */
90 bool ext_phyclk; /* Clock from external PHY */
91 u32 tx_retime_src; /* TXCLK Retiming*/
92 struct clk *clk; /* PHY clock */
93 u32 ctrl_reg; /* GMAC glue-logic control register */
94 int clk_sel_reg; /* GMAC ext clk selection register */
95 struct regmap *regmap;
96 bool gmac_en;
97 int speed;
98 void (*fix_retime_src)(void *priv, int speed, unsigned int mode);
99 };
100
101 struct sti_dwmac_of_data {
102 void (*fix_retime_src)(void *priv, int speed, unsigned int mode);
103 };
104
105 static u32 phy_intf_sels[] = {
106 [PHY_INTERFACE_MODE_MII] = ETH_PHY_SEL_MII,
107 [PHY_INTERFACE_MODE_GMII] = ETH_PHY_SEL_GMII,
108 [PHY_INTERFACE_MODE_RGMII] = ETH_PHY_SEL_RGMII,
109 [PHY_INTERFACE_MODE_RGMII_ID] = ETH_PHY_SEL_RGMII,
110 [PHY_INTERFACE_MODE_SGMII] = ETH_PHY_SEL_SGMII,
111 [PHY_INTERFACE_MODE_RMII] = ETH_PHY_SEL_RMII,
112 };
113
114 enum {
115 TX_RETIME_SRC_NA = 0,
116 TX_RETIME_SRC_TXCLK = 1,
117 TX_RETIME_SRC_CLK_125,
118 TX_RETIME_SRC_PHYCLK,
119 TX_RETIME_SRC_CLKGEN,
120 };
121
122 static u32 stih4xx_tx_retime_val[] = {
123 [TX_RETIME_SRC_TXCLK] = STIH4XX_ETH_SEL_TXCLK_NOT_CLK125,
124 [TX_RETIME_SRC_CLK_125] = 0x0,
125 [TX_RETIME_SRC_PHYCLK] = STIH4XX_ETH_SEL_TX_RETIME_CLK,
126 [TX_RETIME_SRC_CLKGEN] = STIH4XX_ETH_SEL_TX_RETIME_CLK
127 | STIH4XX_ETH_SEL_INTERNAL_NOTEXT_PHYCLK,
128 };
129
stih4xx_fix_retime_src(void * priv,int spd,unsigned int mode)130 static void stih4xx_fix_retime_src(void *priv, int spd, unsigned int mode)
131 {
132 struct sti_dwmac *dwmac = priv;
133 u32 src = dwmac->tx_retime_src;
134 u32 reg = dwmac->ctrl_reg;
135 long freq = 0;
136
137 if (dwmac->interface == PHY_INTERFACE_MODE_MII) {
138 src = TX_RETIME_SRC_TXCLK;
139 } else if (dwmac->interface == PHY_INTERFACE_MODE_RMII) {
140 if (dwmac->ext_phyclk) {
141 src = TX_RETIME_SRC_PHYCLK;
142 } else {
143 src = TX_RETIME_SRC_CLKGEN;
144 freq = DWMAC_50MHZ;
145 }
146 } else if (phy_interface_mode_is_rgmii(dwmac->interface)) {
147 /* On GiGa clk source can be either ext or from clkgen */
148 freq = rgmii_clock(spd);
149
150 if (spd != SPEED_1000 && freq > 0)
151 /* Switch to clkgen for these speeds */
152 src = TX_RETIME_SRC_CLKGEN;
153 }
154
155 if (src == TX_RETIME_SRC_CLKGEN && freq > 0)
156 clk_set_rate(dwmac->clk, freq);
157
158 regmap_update_bits(dwmac->regmap, reg, STIH4XX_RETIME_SRC_MASK,
159 stih4xx_tx_retime_val[src]);
160 }
161
sti_dwmac_set_mode(struct sti_dwmac * dwmac)162 static int sti_dwmac_set_mode(struct sti_dwmac *dwmac)
163 {
164 struct regmap *regmap = dwmac->regmap;
165 int iface = dwmac->interface;
166 u32 reg = dwmac->ctrl_reg;
167 u32 val;
168
169 if (dwmac->gmac_en)
170 regmap_update_bits(regmap, reg, EN_MASK, EN);
171
172 regmap_update_bits(regmap, reg, MII_PHY_SEL_MASK, phy_intf_sels[iface]);
173
174 val = (iface == PHY_INTERFACE_MODE_REVMII) ? 0 : ENMII;
175 regmap_update_bits(regmap, reg, ENMII_MASK, val);
176
177 dwmac->fix_retime_src(dwmac, dwmac->speed, 0);
178
179 return 0;
180 }
181
sti_dwmac_parse_data(struct sti_dwmac * dwmac,struct platform_device * pdev,struct plat_stmmacenet_data * plat_dat)182 static int sti_dwmac_parse_data(struct sti_dwmac *dwmac,
183 struct platform_device *pdev,
184 struct plat_stmmacenet_data *plat_dat)
185 {
186 struct resource *res;
187 struct device *dev = &pdev->dev;
188 struct device_node *np = dev->of_node;
189 struct regmap *regmap;
190 int err;
191
192 /* clk selection from extra syscfg register */
193 dwmac->clk_sel_reg = -ENXIO;
194 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sti-clkconf");
195 if (res)
196 dwmac->clk_sel_reg = res->start;
197
198 regmap = syscon_regmap_lookup_by_phandle_args(np, "st,syscon",
199 1, &dwmac->ctrl_reg);
200 if (IS_ERR(regmap))
201 return PTR_ERR(regmap);
202
203 dwmac->interface = plat_dat->phy_interface;
204 dwmac->regmap = regmap;
205 dwmac->gmac_en = of_property_read_bool(np, "st,gmac_en");
206 dwmac->ext_phyclk = of_property_read_bool(np, "st,ext-phyclk");
207 dwmac->tx_retime_src = TX_RETIME_SRC_NA;
208 dwmac->speed = SPEED_100;
209
210 if (IS_PHY_IF_MODE_GBIT(dwmac->interface)) {
211 const char *rs;
212
213 dwmac->tx_retime_src = TX_RETIME_SRC_CLKGEN;
214
215 err = of_property_read_string(np, "st,tx-retime-src", &rs);
216 if (err < 0) {
217 dev_warn(dev, "Use internal clock source\n");
218 } else {
219 if (!strcasecmp(rs, "clk_125"))
220 dwmac->tx_retime_src = TX_RETIME_SRC_CLK_125;
221 else if (!strcasecmp(rs, "txclk"))
222 dwmac->tx_retime_src = TX_RETIME_SRC_TXCLK;
223 }
224 dwmac->speed = SPEED_1000;
225 }
226
227 dwmac->clk = devm_clk_get(dev, "sti-ethclk");
228 if (IS_ERR(dwmac->clk)) {
229 dev_warn(dev, "No phy clock provided...\n");
230 dwmac->clk = NULL;
231 }
232
233 return 0;
234 }
235
sti_dwmac_init(struct platform_device * pdev,void * bsp_priv)236 static int sti_dwmac_init(struct platform_device *pdev, void *bsp_priv)
237 {
238 struct sti_dwmac *dwmac = bsp_priv;
239 int ret;
240
241 ret = clk_prepare_enable(dwmac->clk);
242 if (ret)
243 return ret;
244
245 ret = sti_dwmac_set_mode(dwmac);
246 if (ret)
247 clk_disable_unprepare(dwmac->clk);
248
249 return ret;
250 }
251
sti_dwmac_exit(struct platform_device * pdev,void * bsp_priv)252 static void sti_dwmac_exit(struct platform_device *pdev, void *bsp_priv)
253 {
254 struct sti_dwmac *dwmac = bsp_priv;
255
256 clk_disable_unprepare(dwmac->clk);
257 }
258
sti_dwmac_probe(struct platform_device * pdev)259 static int sti_dwmac_probe(struct platform_device *pdev)
260 {
261 struct plat_stmmacenet_data *plat_dat;
262 const struct sti_dwmac_of_data *data;
263 struct stmmac_resources stmmac_res;
264 struct sti_dwmac *dwmac;
265 int ret;
266
267 data = of_device_get_match_data(&pdev->dev);
268 if (!data) {
269 dev_err(&pdev->dev, "No OF match data provided\n");
270 return -EINVAL;
271 }
272
273 ret = stmmac_get_platform_resources(pdev, &stmmac_res);
274 if (ret)
275 return ret;
276
277 plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac);
278 if (IS_ERR(plat_dat))
279 return PTR_ERR(plat_dat);
280
281 dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL);
282 if (!dwmac)
283 return -ENOMEM;
284
285 ret = sti_dwmac_parse_data(dwmac, pdev, plat_dat);
286 if (ret) {
287 dev_err(&pdev->dev, "Unable to parse OF data\n");
288 return ret;
289 }
290
291 dwmac->fix_retime_src = data->fix_retime_src;
292
293 plat_dat->bsp_priv = dwmac;
294 plat_dat->fix_mac_speed = data->fix_retime_src;
295 plat_dat->init = sti_dwmac_init;
296 plat_dat->exit = sti_dwmac_exit;
297
298 return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res);
299 }
300
301 static const struct sti_dwmac_of_data stih4xx_dwmac_data = {
302 .fix_retime_src = stih4xx_fix_retime_src,
303 };
304
305 static const struct of_device_id sti_dwmac_match[] = {
306 { .compatible = "st,stih407-dwmac", .data = &stih4xx_dwmac_data},
307 { }
308 };
309 MODULE_DEVICE_TABLE(of, sti_dwmac_match);
310
311 static struct platform_driver sti_dwmac_driver = {
312 .probe = sti_dwmac_probe,
313 .driver = {
314 .name = "sti-dwmac",
315 .pm = &stmmac_pltfr_pm_ops,
316 .of_match_table = sti_dwmac_match,
317 },
318 };
319 module_platform_driver(sti_dwmac_driver);
320
321 MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@st.com>");
322 MODULE_DESCRIPTION("STMicroelectronics DWMAC Specific Glue layer");
323 MODULE_LICENSE("GPL");
324