1 /*
2 * AXP20x regulators driver.
3 *
4 * Copyright (C) 2013 Carlo Caione <carlo@caione.org>
5 *
6 * This file is subject to the terms and conditions of the GNU General
7 * Public License. See the file "COPYING" in the main directory of this
8 * archive for more details.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #include <linux/bitops.h>
17 #include <linux/delay.h>
18 #include <linux/err.h>
19 #include <linux/init.h>
20 #include <linux/mfd/axp20x.h>
21 #include <linux/module.h>
22 #include <linux/of.h>
23 #include <linux/platform_device.h>
24 #include <linux/regmap.h>
25 #include <linux/regulator/driver.h>
26 #include <linux/regulator/machine.h>
27 #include <linux/regulator/of_regulator.h>
28
29 #define AXP20X_GPIO0_FUNC_MASK GENMASK(3, 0)
30 #define AXP20X_GPIO1_FUNC_MASK GENMASK(3, 0)
31
32 #define AXP20X_IO_ENABLED 0x03
33 #define AXP20X_IO_DISABLED 0x07
34
35 #define AXP20X_WORKMODE_DCDC2_MASK BIT_MASK(2)
36 #define AXP20X_WORKMODE_DCDC3_MASK BIT_MASK(1)
37
38 #define AXP20X_FREQ_DCDC_MASK GENMASK(3, 0)
39
40 #define AXP20X_VBUS_IPSOUT_MGMT_MASK BIT_MASK(2)
41
42 #define AXP20X_DCDC2_V_OUT_MASK GENMASK(5, 0)
43 #define AXP20X_DCDC3_V_OUT_MASK GENMASK(7, 0)
44 #define AXP20X_LDO2_V_OUT_MASK GENMASK(7, 4)
45 #define AXP20X_LDO3_V_OUT_MASK GENMASK(6, 0)
46 #define AXP20X_LDO4_V_OUT_MASK GENMASK(3, 0)
47 #define AXP20X_LDO5_V_OUT_MASK GENMASK(7, 4)
48
49 #define AXP20X_PWR_OUT_EXTEN_MASK BIT_MASK(0)
50 #define AXP20X_PWR_OUT_DCDC3_MASK BIT_MASK(1)
51 #define AXP20X_PWR_OUT_LDO2_MASK BIT_MASK(2)
52 #define AXP20X_PWR_OUT_LDO4_MASK BIT_MASK(3)
53 #define AXP20X_PWR_OUT_DCDC2_MASK BIT_MASK(4)
54 #define AXP20X_PWR_OUT_LDO3_MASK BIT_MASK(6)
55
56 #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE_MASK BIT_MASK(0)
57 #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE(x) \
58 ((x) << 0)
59 #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE_MASK BIT_MASK(1)
60 #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE(x) \
61 ((x) << 1)
62 #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN_MASK BIT_MASK(2)
63 #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN BIT(2)
64 #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN_MASK BIT_MASK(3)
65 #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN BIT(3)
66
67 #define AXP20X_LDO4_V_OUT_1250mV_START 0x0
68 #define AXP20X_LDO4_V_OUT_1250mV_STEPS 0
69 #define AXP20X_LDO4_V_OUT_1250mV_END \
70 (AXP20X_LDO4_V_OUT_1250mV_START + AXP20X_LDO4_V_OUT_1250mV_STEPS)
71 #define AXP20X_LDO4_V_OUT_1300mV_START 0x1
72 #define AXP20X_LDO4_V_OUT_1300mV_STEPS 7
73 #define AXP20X_LDO4_V_OUT_1300mV_END \
74 (AXP20X_LDO4_V_OUT_1300mV_START + AXP20X_LDO4_V_OUT_1300mV_STEPS)
75 #define AXP20X_LDO4_V_OUT_2500mV_START 0x9
76 #define AXP20X_LDO4_V_OUT_2500mV_STEPS 0
77 #define AXP20X_LDO4_V_OUT_2500mV_END \
78 (AXP20X_LDO4_V_OUT_2500mV_START + AXP20X_LDO4_V_OUT_2500mV_STEPS)
79 #define AXP20X_LDO4_V_OUT_2700mV_START 0xa
80 #define AXP20X_LDO4_V_OUT_2700mV_STEPS 1
81 #define AXP20X_LDO4_V_OUT_2700mV_END \
82 (AXP20X_LDO4_V_OUT_2700mV_START + AXP20X_LDO4_V_OUT_2700mV_STEPS)
83 #define AXP20X_LDO4_V_OUT_3000mV_START 0xc
84 #define AXP20X_LDO4_V_OUT_3000mV_STEPS 3
85 #define AXP20X_LDO4_V_OUT_3000mV_END \
86 (AXP20X_LDO4_V_OUT_3000mV_START + AXP20X_LDO4_V_OUT_3000mV_STEPS)
87 #define AXP20X_LDO4_V_OUT_NUM_VOLTAGES 16
88
89 #define AXP22X_IO_ENABLED 0x03
90 #define AXP22X_IO_DISABLED 0x04
91
92 #define AXP22X_WORKMODE_DCDCX_MASK(x) BIT_MASK(x)
93
94 #define AXP22X_MISC_N_VBUSEN_FUNC BIT(4)
95
96 #define AXP22X_DCDC1_V_OUT_MASK GENMASK(4, 0)
97 #define AXP22X_DCDC2_V_OUT_MASK GENMASK(5, 0)
98 #define AXP22X_DCDC3_V_OUT_MASK GENMASK(5, 0)
99 #define AXP22X_DCDC4_V_OUT_MASK GENMASK(5, 0)
100 #define AXP22X_DCDC5_V_OUT_MASK GENMASK(4, 0)
101 #define AXP22X_DC5LDO_V_OUT_MASK GENMASK(2, 0)
102 #define AXP22X_ALDO1_V_OUT_MASK GENMASK(4, 0)
103 #define AXP22X_ALDO2_V_OUT_MASK GENMASK(4, 0)
104 #define AXP22X_ALDO3_V_OUT_MASK GENMASK(4, 0)
105 #define AXP22X_DLDO1_V_OUT_MASK GENMASK(4, 0)
106 #define AXP22X_DLDO2_V_OUT_MASK GENMASK(4, 0)
107 #define AXP22X_DLDO3_V_OUT_MASK GENMASK(4, 0)
108 #define AXP22X_DLDO4_V_OUT_MASK GENMASK(4, 0)
109 #define AXP22X_ELDO1_V_OUT_MASK GENMASK(4, 0)
110 #define AXP22X_ELDO2_V_OUT_MASK GENMASK(4, 0)
111 #define AXP22X_ELDO3_V_OUT_MASK GENMASK(4, 0)
112 #define AXP22X_LDO_IO0_V_OUT_MASK GENMASK(4, 0)
113 #define AXP22X_LDO_IO1_V_OUT_MASK GENMASK(4, 0)
114
115 #define AXP22X_PWR_OUT_DC5LDO_MASK BIT_MASK(0)
116 #define AXP22X_PWR_OUT_DCDC1_MASK BIT_MASK(1)
117 #define AXP22X_PWR_OUT_DCDC2_MASK BIT_MASK(2)
118 #define AXP22X_PWR_OUT_DCDC3_MASK BIT_MASK(3)
119 #define AXP22X_PWR_OUT_DCDC4_MASK BIT_MASK(4)
120 #define AXP22X_PWR_OUT_DCDC5_MASK BIT_MASK(5)
121 #define AXP22X_PWR_OUT_ALDO1_MASK BIT_MASK(6)
122 #define AXP22X_PWR_OUT_ALDO2_MASK BIT_MASK(7)
123
124 #define AXP22X_PWR_OUT_SW_MASK BIT_MASK(6)
125 #define AXP22X_PWR_OUT_DC1SW_MASK BIT_MASK(7)
126
127 #define AXP22X_PWR_OUT_ELDO1_MASK BIT_MASK(0)
128 #define AXP22X_PWR_OUT_ELDO2_MASK BIT_MASK(1)
129 #define AXP22X_PWR_OUT_ELDO3_MASK BIT_MASK(2)
130 #define AXP22X_PWR_OUT_DLDO1_MASK BIT_MASK(3)
131 #define AXP22X_PWR_OUT_DLDO2_MASK BIT_MASK(4)
132 #define AXP22X_PWR_OUT_DLDO3_MASK BIT_MASK(5)
133 #define AXP22X_PWR_OUT_DLDO4_MASK BIT_MASK(6)
134 #define AXP22X_PWR_OUT_ALDO3_MASK BIT_MASK(7)
135
136 #define AXP313A_DCDC1_NUM_VOLTAGES 107
137 #define AXP313A_DCDC23_NUM_VOLTAGES 88
138 #define AXP313A_DCDC_V_OUT_MASK GENMASK(6, 0)
139 #define AXP313A_LDO_V_OUT_MASK GENMASK(4, 0)
140
141 #define AXP717_DCDC1_NUM_VOLTAGES 88
142 #define AXP717_DCDC2_NUM_VOLTAGES 107
143 #define AXP717_DCDC3_NUM_VOLTAGES 103
144 #define AXP717_DCDC_V_OUT_MASK GENMASK(6, 0)
145 #define AXP717_LDO_V_OUT_MASK GENMASK(4, 0)
146 #define AXP717_BOOST_V_OUT_MASK GENMASK(7, 4)
147
148 #define AXP803_PWR_OUT_DCDC1_MASK BIT_MASK(0)
149 #define AXP803_PWR_OUT_DCDC2_MASK BIT_MASK(1)
150 #define AXP803_PWR_OUT_DCDC3_MASK BIT_MASK(2)
151 #define AXP803_PWR_OUT_DCDC4_MASK BIT_MASK(3)
152 #define AXP803_PWR_OUT_DCDC5_MASK BIT_MASK(4)
153 #define AXP803_PWR_OUT_DCDC6_MASK BIT_MASK(5)
154
155 #define AXP803_PWR_OUT_FLDO1_MASK BIT_MASK(2)
156 #define AXP803_PWR_OUT_FLDO2_MASK BIT_MASK(3)
157
158 #define AXP803_DCDC1_V_OUT_MASK GENMASK(4, 0)
159 #define AXP803_DCDC2_V_OUT_MASK GENMASK(6, 0)
160 #define AXP803_DCDC3_V_OUT_MASK GENMASK(6, 0)
161 #define AXP803_DCDC4_V_OUT_MASK GENMASK(6, 0)
162 #define AXP803_DCDC5_V_OUT_MASK GENMASK(6, 0)
163 #define AXP803_DCDC6_V_OUT_MASK GENMASK(6, 0)
164
165 #define AXP803_FLDO1_V_OUT_MASK GENMASK(3, 0)
166 #define AXP803_FLDO2_V_OUT_MASK GENMASK(3, 0)
167
168 #define AXP803_DCDC23_POLYPHASE_DUAL BIT(6)
169 #define AXP803_DCDC56_POLYPHASE_DUAL BIT(5)
170
171 #define AXP803_DCDC234_500mV_START 0x00
172 #define AXP803_DCDC234_500mV_STEPS 70
173 #define AXP803_DCDC234_500mV_END \
174 (AXP803_DCDC234_500mV_START + AXP803_DCDC234_500mV_STEPS)
175 #define AXP803_DCDC234_1220mV_START 0x47
176 #define AXP803_DCDC234_1220mV_STEPS 4
177 #define AXP803_DCDC234_1220mV_END \
178 (AXP803_DCDC234_1220mV_START + AXP803_DCDC234_1220mV_STEPS)
179 #define AXP803_DCDC234_NUM_VOLTAGES 76
180
181 #define AXP803_DCDC5_800mV_START 0x00
182 #define AXP803_DCDC5_800mV_STEPS 32
183 #define AXP803_DCDC5_800mV_END \
184 (AXP803_DCDC5_800mV_START + AXP803_DCDC5_800mV_STEPS)
185 #define AXP803_DCDC5_1140mV_START 0x21
186 #define AXP803_DCDC5_1140mV_STEPS 35
187 #define AXP803_DCDC5_1140mV_END \
188 (AXP803_DCDC5_1140mV_START + AXP803_DCDC5_1140mV_STEPS)
189 #define AXP803_DCDC5_NUM_VOLTAGES 69
190
191 #define AXP803_DCDC6_600mV_START 0x00
192 #define AXP803_DCDC6_600mV_STEPS 50
193 #define AXP803_DCDC6_600mV_END \
194 (AXP803_DCDC6_600mV_START + AXP803_DCDC6_600mV_STEPS)
195 #define AXP803_DCDC6_1120mV_START 0x33
196 #define AXP803_DCDC6_1120mV_STEPS 20
197 #define AXP803_DCDC6_1120mV_END \
198 (AXP803_DCDC6_1120mV_START + AXP803_DCDC6_1120mV_STEPS)
199 #define AXP803_DCDC6_NUM_VOLTAGES 72
200
201 #define AXP803_DLDO2_700mV_START 0x00
202 #define AXP803_DLDO2_700mV_STEPS 26
203 #define AXP803_DLDO2_700mV_END \
204 (AXP803_DLDO2_700mV_START + AXP803_DLDO2_700mV_STEPS)
205 #define AXP803_DLDO2_3400mV_START 0x1b
206 #define AXP803_DLDO2_3400mV_STEPS 4
207 #define AXP803_DLDO2_3400mV_END \
208 (AXP803_DLDO2_3400mV_START + AXP803_DLDO2_3400mV_STEPS)
209 #define AXP803_DLDO2_NUM_VOLTAGES 32
210
211 #define AXP806_DCDCA_V_CTRL_MASK GENMASK(6, 0)
212 #define AXP806_DCDCB_V_CTRL_MASK GENMASK(4, 0)
213 #define AXP806_DCDCC_V_CTRL_MASK GENMASK(6, 0)
214 #define AXP806_DCDCD_V_CTRL_MASK GENMASK(5, 0)
215 #define AXP806_DCDCE_V_CTRL_MASK GENMASK(4, 0)
216 #define AXP806_ALDO1_V_CTRL_MASK GENMASK(4, 0)
217 #define AXP806_ALDO2_V_CTRL_MASK GENMASK(4, 0)
218 #define AXP806_ALDO3_V_CTRL_MASK GENMASK(4, 0)
219 #define AXP806_BLDO1_V_CTRL_MASK GENMASK(3, 0)
220 #define AXP806_BLDO2_V_CTRL_MASK GENMASK(3, 0)
221 #define AXP806_BLDO3_V_CTRL_MASK GENMASK(3, 0)
222 #define AXP806_BLDO4_V_CTRL_MASK GENMASK(3, 0)
223 #define AXP806_CLDO1_V_CTRL_MASK GENMASK(4, 0)
224 #define AXP806_CLDO2_V_CTRL_MASK GENMASK(4, 0)
225 #define AXP806_CLDO3_V_CTRL_MASK GENMASK(4, 0)
226
227 #define AXP806_PWR_OUT_DCDCA_MASK BIT_MASK(0)
228 #define AXP806_PWR_OUT_DCDCB_MASK BIT_MASK(1)
229 #define AXP806_PWR_OUT_DCDCC_MASK BIT_MASK(2)
230 #define AXP806_PWR_OUT_DCDCD_MASK BIT_MASK(3)
231 #define AXP806_PWR_OUT_DCDCE_MASK BIT_MASK(4)
232 #define AXP806_PWR_OUT_ALDO1_MASK BIT_MASK(5)
233 #define AXP806_PWR_OUT_ALDO2_MASK BIT_MASK(6)
234 #define AXP806_PWR_OUT_ALDO3_MASK BIT_MASK(7)
235 #define AXP806_PWR_OUT_BLDO1_MASK BIT_MASK(0)
236 #define AXP806_PWR_OUT_BLDO2_MASK BIT_MASK(1)
237 #define AXP806_PWR_OUT_BLDO3_MASK BIT_MASK(2)
238 #define AXP806_PWR_OUT_BLDO4_MASK BIT_MASK(3)
239 #define AXP806_PWR_OUT_CLDO1_MASK BIT_MASK(4)
240 #define AXP806_PWR_OUT_CLDO2_MASK BIT_MASK(5)
241 #define AXP806_PWR_OUT_CLDO3_MASK BIT_MASK(6)
242 #define AXP806_PWR_OUT_SW_MASK BIT_MASK(7)
243
244 #define AXP806_DCDCAB_POLYPHASE_DUAL 0x40
245 #define AXP806_DCDCABC_POLYPHASE_TRI 0x80
246 #define AXP806_DCDCABC_POLYPHASE_MASK GENMASK(7, 6)
247
248 #define AXP806_DCDCDE_POLYPHASE_DUAL BIT(5)
249
250 #define AXP806_DCDCA_600mV_START 0x00
251 #define AXP806_DCDCA_600mV_STEPS 50
252 #define AXP806_DCDCA_600mV_END \
253 (AXP806_DCDCA_600mV_START + AXP806_DCDCA_600mV_STEPS)
254 #define AXP806_DCDCA_1120mV_START 0x33
255 #define AXP806_DCDCA_1120mV_STEPS 20
256 #define AXP806_DCDCA_1120mV_END \
257 (AXP806_DCDCA_1120mV_START + AXP806_DCDCA_1120mV_STEPS)
258 #define AXP806_DCDCA_NUM_VOLTAGES 72
259
260 #define AXP806_DCDCD_600mV_START 0x00
261 #define AXP806_DCDCD_600mV_STEPS 45
262 #define AXP806_DCDCD_600mV_END \
263 (AXP806_DCDCD_600mV_START + AXP806_DCDCD_600mV_STEPS)
264 #define AXP806_DCDCD_1600mV_START 0x2e
265 #define AXP806_DCDCD_1600mV_STEPS 17
266 #define AXP806_DCDCD_1600mV_END \
267 (AXP806_DCDCD_1600mV_START + AXP806_DCDCD_1600mV_STEPS)
268 #define AXP806_DCDCD_NUM_VOLTAGES 64
269
270 #define AXP809_DCDC4_600mV_START 0x00
271 #define AXP809_DCDC4_600mV_STEPS 47
272 #define AXP809_DCDC4_600mV_END \
273 (AXP809_DCDC4_600mV_START + AXP809_DCDC4_600mV_STEPS)
274 #define AXP809_DCDC4_1800mV_START 0x30
275 #define AXP809_DCDC4_1800mV_STEPS 8
276 #define AXP809_DCDC4_1800mV_END \
277 (AXP809_DCDC4_1800mV_START + AXP809_DCDC4_1800mV_STEPS)
278 #define AXP809_DCDC4_NUM_VOLTAGES 57
279
280 #define AXP813_DCDC7_V_OUT_MASK GENMASK(6, 0)
281
282 #define AXP813_PWR_OUT_DCDC7_MASK BIT_MASK(6)
283
284 #define AXP15060_DCDC1_V_CTRL_MASK GENMASK(4, 0)
285 #define AXP15060_DCDC2_V_CTRL_MASK GENMASK(6, 0)
286 #define AXP15060_DCDC3_V_CTRL_MASK GENMASK(6, 0)
287 #define AXP15060_DCDC4_V_CTRL_MASK GENMASK(6, 0)
288 #define AXP15060_DCDC5_V_CTRL_MASK GENMASK(6, 0)
289 #define AXP15060_DCDC6_V_CTRL_MASK GENMASK(4, 0)
290 #define AXP15060_ALDO1_V_CTRL_MASK GENMASK(4, 0)
291 #define AXP15060_ALDO2_V_CTRL_MASK GENMASK(4, 0)
292 #define AXP15060_ALDO3_V_CTRL_MASK GENMASK(4, 0)
293 #define AXP15060_ALDO4_V_CTRL_MASK GENMASK(4, 0)
294 #define AXP15060_ALDO5_V_CTRL_MASK GENMASK(4, 0)
295 #define AXP15060_BLDO1_V_CTRL_MASK GENMASK(4, 0)
296 #define AXP15060_BLDO2_V_CTRL_MASK GENMASK(4, 0)
297 #define AXP15060_BLDO3_V_CTRL_MASK GENMASK(4, 0)
298 #define AXP15060_BLDO4_V_CTRL_MASK GENMASK(4, 0)
299 #define AXP15060_BLDO5_V_CTRL_MASK GENMASK(4, 0)
300 #define AXP15060_CLDO1_V_CTRL_MASK GENMASK(4, 0)
301 #define AXP15060_CLDO2_V_CTRL_MASK GENMASK(4, 0)
302 #define AXP15060_CLDO3_V_CTRL_MASK GENMASK(4, 0)
303 #define AXP15060_CLDO4_V_CTRL_MASK GENMASK(5, 0)
304 #define AXP15060_CPUSLDO_V_CTRL_MASK GENMASK(3, 0)
305
306 #define AXP15060_PWR_OUT_DCDC1_MASK BIT_MASK(0)
307 #define AXP15060_PWR_OUT_DCDC2_MASK BIT_MASK(1)
308 #define AXP15060_PWR_OUT_DCDC3_MASK BIT_MASK(2)
309 #define AXP15060_PWR_OUT_DCDC4_MASK BIT_MASK(3)
310 #define AXP15060_PWR_OUT_DCDC5_MASK BIT_MASK(4)
311 #define AXP15060_PWR_OUT_DCDC6_MASK BIT_MASK(5)
312 #define AXP15060_PWR_OUT_ALDO1_MASK BIT_MASK(0)
313 #define AXP15060_PWR_OUT_ALDO2_MASK BIT_MASK(1)
314 #define AXP15060_PWR_OUT_ALDO3_MASK BIT_MASK(2)
315 #define AXP15060_PWR_OUT_ALDO4_MASK BIT_MASK(3)
316 #define AXP15060_PWR_OUT_ALDO5_MASK BIT_MASK(4)
317 #define AXP15060_PWR_OUT_BLDO1_MASK BIT_MASK(5)
318 #define AXP15060_PWR_OUT_BLDO2_MASK BIT_MASK(6)
319 #define AXP15060_PWR_OUT_BLDO3_MASK BIT_MASK(7)
320 #define AXP15060_PWR_OUT_BLDO4_MASK BIT_MASK(0)
321 #define AXP15060_PWR_OUT_BLDO5_MASK BIT_MASK(1)
322 #define AXP15060_PWR_OUT_CLDO1_MASK BIT_MASK(2)
323 #define AXP15060_PWR_OUT_CLDO2_MASK BIT_MASK(3)
324 #define AXP15060_PWR_OUT_CLDO3_MASK BIT_MASK(4)
325 #define AXP15060_PWR_OUT_CLDO4_MASK BIT_MASK(5)
326 #define AXP15060_PWR_OUT_CPUSLDO_MASK BIT_MASK(6)
327 #define AXP15060_PWR_OUT_SW_MASK BIT_MASK(7)
328
329 #define AXP15060_DCDC23_POLYPHASE_DUAL_MASK BIT_MASK(6)
330 #define AXP15060_DCDC46_POLYPHASE_DUAL_MASK BIT_MASK(7)
331
332 #define AXP15060_DCDC234_500mV_START 0x00
333 #define AXP15060_DCDC234_500mV_STEPS 70
334 #define AXP15060_DCDC234_500mV_END \
335 (AXP15060_DCDC234_500mV_START + AXP15060_DCDC234_500mV_STEPS)
336 #define AXP15060_DCDC234_1220mV_START 0x47
337 #define AXP15060_DCDC234_1220mV_STEPS 16
338 #define AXP15060_DCDC234_1220mV_END \
339 (AXP15060_DCDC234_1220mV_START + AXP15060_DCDC234_1220mV_STEPS)
340 #define AXP15060_DCDC234_NUM_VOLTAGES 88
341
342 #define AXP15060_DCDC5_800mV_START 0x00
343 #define AXP15060_DCDC5_800mV_STEPS 32
344 #define AXP15060_DCDC5_800mV_END \
345 (AXP15060_DCDC5_800mV_START + AXP15060_DCDC5_800mV_STEPS)
346 #define AXP15060_DCDC5_1140mV_START 0x21
347 #define AXP15060_DCDC5_1140mV_STEPS 35
348 #define AXP15060_DCDC5_1140mV_END \
349 (AXP15060_DCDC5_1140mV_START + AXP15060_DCDC5_1140mV_STEPS)
350 #define AXP15060_DCDC5_NUM_VOLTAGES 69
351
352 #define AXP_DESC_IO(_family, _id, _match, _supply, _min, _max, _step, _vreg, \
353 _vmask, _ereg, _emask, _enable_val, _disable_val) \
354 [_family##_##_id] = { \
355 .name = (_match), \
356 .supply_name = (_supply), \
357 .of_match = of_match_ptr(_match), \
358 .regulators_node = of_match_ptr("regulators"), \
359 .type = REGULATOR_VOLTAGE, \
360 .id = _family##_##_id, \
361 .n_voltages = (((_max) - (_min)) / (_step) + 1), \
362 .owner = THIS_MODULE, \
363 .min_uV = (_min) * 1000, \
364 .uV_step = (_step) * 1000, \
365 .vsel_reg = (_vreg), \
366 .vsel_mask = (_vmask), \
367 .enable_reg = (_ereg), \
368 .enable_mask = (_emask), \
369 .enable_val = (_enable_val), \
370 .disable_val = (_disable_val), \
371 .ops = &axp20x_ops, \
372 }
373
374 #define AXP_DESC(_family, _id, _match, _supply, _min, _max, _step, _vreg, \
375 _vmask, _ereg, _emask) \
376 [_family##_##_id] = { \
377 .name = (_match), \
378 .supply_name = (_supply), \
379 .of_match = of_match_ptr(_match), \
380 .regulators_node = of_match_ptr("regulators"), \
381 .type = REGULATOR_VOLTAGE, \
382 .id = _family##_##_id, \
383 .n_voltages = (((_max) - (_min)) / (_step) + 1), \
384 .owner = THIS_MODULE, \
385 .min_uV = (_min) * 1000, \
386 .uV_step = (_step) * 1000, \
387 .vsel_reg = (_vreg), \
388 .vsel_mask = (_vmask), \
389 .enable_reg = (_ereg), \
390 .enable_mask = (_emask), \
391 .ops = &axp20x_ops, \
392 }
393
394 #define AXP_DESC_SW(_family, _id, _match, _supply, _ereg, _emask) \
395 [_family##_##_id] = { \
396 .name = (_match), \
397 .supply_name = (_supply), \
398 .of_match = of_match_ptr(_match), \
399 .regulators_node = of_match_ptr("regulators"), \
400 .type = REGULATOR_VOLTAGE, \
401 .id = _family##_##_id, \
402 .owner = THIS_MODULE, \
403 .enable_reg = (_ereg), \
404 .enable_mask = (_emask), \
405 .ops = &axp20x_ops_sw, \
406 }
407
408 #define AXP_DESC_FIXED(_family, _id, _match, _supply, _volt) \
409 [_family##_##_id] = { \
410 .name = (_match), \
411 .supply_name = (_supply), \
412 .of_match = of_match_ptr(_match), \
413 .regulators_node = of_match_ptr("regulators"), \
414 .type = REGULATOR_VOLTAGE, \
415 .id = _family##_##_id, \
416 .n_voltages = 1, \
417 .owner = THIS_MODULE, \
418 .min_uV = (_volt) * 1000, \
419 .ops = &axp20x_ops_fixed \
420 }
421
422 #define AXP_DESC_RANGES_DELAY(_family, _id, _match, _supply, _ranges, _n_voltages, \
423 _vreg, _vmask, _ereg, _emask, _ramp_delay) \
424 [_family##_##_id] = { \
425 .name = (_match), \
426 .supply_name = (_supply), \
427 .of_match = of_match_ptr(_match), \
428 .regulators_node = of_match_ptr("regulators"), \
429 .type = REGULATOR_VOLTAGE, \
430 .id = _family##_##_id, \
431 .n_voltages = (_n_voltages), \
432 .owner = THIS_MODULE, \
433 .vsel_reg = (_vreg), \
434 .vsel_mask = (_vmask), \
435 .enable_reg = (_ereg), \
436 .enable_mask = (_emask), \
437 .linear_ranges = (_ranges), \
438 .n_linear_ranges = ARRAY_SIZE(_ranges), \
439 .ramp_delay = (_ramp_delay), \
440 .ops = &axp20x_ops_range, \
441 }
442
443 #define AXP_DESC_RANGES(_family, _id, _match, _supply, _ranges, _n_voltages, \
444 _vreg, _vmask, _ereg, _emask) \
445 AXP_DESC_RANGES_DELAY(_family, _id, _match, _supply, _ranges, \
446 _n_voltages, _vreg, _vmask, _ereg, _emask, 0)
447
448 static const int axp209_dcdc2_ldo3_slew_rates[] = {
449 1600,
450 800,
451 };
452
axp20x_set_ramp_delay(struct regulator_dev * rdev,int ramp)453 static int axp20x_set_ramp_delay(struct regulator_dev *rdev, int ramp)
454 {
455 struct axp20x_dev *axp20x = rdev_get_drvdata(rdev);
456 int id = rdev_get_id(rdev);
457 u8 reg, mask, enable, cfg = 0xff;
458 const int *slew_rates;
459 int rate_count = 0;
460
461 switch (axp20x->variant) {
462 case AXP209_ID:
463 if (id == AXP20X_DCDC2) {
464 slew_rates = axp209_dcdc2_ldo3_slew_rates;
465 rate_count = ARRAY_SIZE(axp209_dcdc2_ldo3_slew_rates);
466 reg = AXP20X_DCDC2_LDO3_V_RAMP;
467 mask = AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE_MASK |
468 AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN_MASK;
469 enable = (ramp > 0) ?
470 AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN : 0;
471 break;
472 }
473
474 if (id == AXP20X_LDO3) {
475 slew_rates = axp209_dcdc2_ldo3_slew_rates;
476 rate_count = ARRAY_SIZE(axp209_dcdc2_ldo3_slew_rates);
477 reg = AXP20X_DCDC2_LDO3_V_RAMP;
478 mask = AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE_MASK |
479 AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN_MASK;
480 enable = (ramp > 0) ?
481 AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN : 0;
482 break;
483 }
484
485 if (rate_count > 0)
486 break;
487
488 fallthrough;
489 default:
490 /* Not supported for this regulator */
491 return -ENOTSUPP;
492 }
493
494 if (ramp == 0) {
495 cfg = enable;
496 } else {
497 int i;
498
499 for (i = 0; i < rate_count; i++) {
500 if (ramp > slew_rates[i])
501 break;
502
503 if (id == AXP20X_DCDC2)
504 cfg = AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE(i);
505 else
506 cfg = AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE(i);
507 }
508
509 if (cfg == 0xff) {
510 dev_err(axp20x->dev, "unsupported ramp value %d", ramp);
511 return -EINVAL;
512 }
513
514 cfg |= enable;
515 }
516
517 return regmap_update_bits(axp20x->regmap, reg, mask, cfg);
518 }
519
axp20x_regulator_enable_regmap(struct regulator_dev * rdev)520 static int axp20x_regulator_enable_regmap(struct regulator_dev *rdev)
521 {
522 struct axp20x_dev *axp20x = rdev_get_drvdata(rdev);
523 int id = rdev_get_id(rdev);
524
525 switch (axp20x->variant) {
526 case AXP209_ID:
527 if ((id == AXP20X_LDO3) &&
528 rdev->constraints && rdev->constraints->soft_start) {
529 int v_out;
530 int ret;
531
532 /*
533 * On some boards, the LDO3 can be overloaded when
534 * turning on, causing the entire PMIC to shutdown
535 * without warning. Turning it on at the minimal voltage
536 * and then setting the voltage to the requested value
537 * works reliably.
538 */
539 if (regulator_is_enabled_regmap(rdev))
540 break;
541
542 v_out = regulator_get_voltage_sel_regmap(rdev);
543 if (v_out < 0)
544 return v_out;
545
546 if (v_out == 0)
547 break;
548
549 ret = regulator_set_voltage_sel_regmap(rdev, 0x00);
550 /*
551 * A small pause is needed between
552 * setting the voltage and enabling the LDO to give the
553 * internal state machine time to process the request.
554 */
555 usleep_range(1000, 5000);
556 ret |= regulator_enable_regmap(rdev);
557 ret |= regulator_set_voltage_sel_regmap(rdev, v_out);
558
559 return ret;
560 }
561 break;
562 default:
563 /* No quirks */
564 break;
565 }
566
567 return regulator_enable_regmap(rdev);
568 };
569
570 static const struct regulator_ops axp20x_ops_fixed = {
571 .list_voltage = regulator_list_voltage_linear,
572 };
573
574 static const struct regulator_ops axp20x_ops_range = {
575 .set_voltage_sel = regulator_set_voltage_sel_regmap,
576 .get_voltage_sel = regulator_get_voltage_sel_regmap,
577 .list_voltage = regulator_list_voltage_linear_range,
578 .enable = regulator_enable_regmap,
579 .disable = regulator_disable_regmap,
580 .is_enabled = regulator_is_enabled_regmap,
581 };
582
583 static const struct regulator_ops axp20x_ops = {
584 .set_voltage_sel = regulator_set_voltage_sel_regmap,
585 .get_voltage_sel = regulator_get_voltage_sel_regmap,
586 .list_voltage = regulator_list_voltage_linear,
587 .enable = axp20x_regulator_enable_regmap,
588 .disable = regulator_disable_regmap,
589 .is_enabled = regulator_is_enabled_regmap,
590 .set_ramp_delay = axp20x_set_ramp_delay,
591 };
592
593 static const struct regulator_ops axp20x_ops_sw = {
594 .enable = regulator_enable_regmap,
595 .disable = regulator_disable_regmap,
596 .is_enabled = regulator_is_enabled_regmap,
597 };
598
599 static const struct linear_range axp20x_ldo4_ranges[] = {
600 REGULATOR_LINEAR_RANGE(1250000,
601 AXP20X_LDO4_V_OUT_1250mV_START,
602 AXP20X_LDO4_V_OUT_1250mV_END,
603 0),
604 REGULATOR_LINEAR_RANGE(1300000,
605 AXP20X_LDO4_V_OUT_1300mV_START,
606 AXP20X_LDO4_V_OUT_1300mV_END,
607 100000),
608 REGULATOR_LINEAR_RANGE(2500000,
609 AXP20X_LDO4_V_OUT_2500mV_START,
610 AXP20X_LDO4_V_OUT_2500mV_END,
611 0),
612 REGULATOR_LINEAR_RANGE(2700000,
613 AXP20X_LDO4_V_OUT_2700mV_START,
614 AXP20X_LDO4_V_OUT_2700mV_END,
615 100000),
616 REGULATOR_LINEAR_RANGE(3000000,
617 AXP20X_LDO4_V_OUT_3000mV_START,
618 AXP20X_LDO4_V_OUT_3000mV_END,
619 100000),
620 };
621
622 static const struct regulator_desc axp20x_regulators[] = {
623 AXP_DESC(AXP20X, DCDC2, "dcdc2", "vin2", 700, 2275, 25,
624 AXP20X_DCDC2_V_OUT, AXP20X_DCDC2_V_OUT_MASK,
625 AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_DCDC2_MASK),
626 AXP_DESC(AXP20X, DCDC3, "dcdc3", "vin3", 700, 3500, 25,
627 AXP20X_DCDC3_V_OUT, AXP20X_DCDC3_V_OUT_MASK,
628 AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_DCDC3_MASK),
629 AXP_DESC_FIXED(AXP20X, LDO1, "ldo1", "acin", 1300),
630 AXP_DESC(AXP20X, LDO2, "ldo2", "ldo24in", 1800, 3300, 100,
631 AXP20X_LDO24_V_OUT, AXP20X_LDO2_V_OUT_MASK,
632 AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_LDO2_MASK),
633 AXP_DESC(AXP20X, LDO3, "ldo3", "ldo3in", 700, 3500, 25,
634 AXP20X_LDO3_V_OUT, AXP20X_LDO3_V_OUT_MASK,
635 AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_LDO3_MASK),
636 AXP_DESC_RANGES(AXP20X, LDO4, "ldo4", "ldo24in",
637 axp20x_ldo4_ranges, AXP20X_LDO4_V_OUT_NUM_VOLTAGES,
638 AXP20X_LDO24_V_OUT, AXP20X_LDO4_V_OUT_MASK,
639 AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_LDO4_MASK),
640 AXP_DESC_IO(AXP20X, LDO5, "ldo5", "ldo5in", 1800, 3300, 100,
641 AXP20X_LDO5_V_OUT, AXP20X_LDO5_V_OUT_MASK,
642 AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
643 AXP20X_IO_ENABLED, AXP20X_IO_DISABLED),
644 };
645
646 static const struct regulator_desc axp22x_regulators[] = {
647 AXP_DESC(AXP22X, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,
648 AXP22X_DCDC1_V_OUT, AXP22X_DCDC1_V_OUT_MASK,
649 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC1_MASK),
650 AXP_DESC(AXP22X, DCDC2, "dcdc2", "vin2", 600, 1540, 20,
651 AXP22X_DCDC2_V_OUT, AXP22X_DCDC2_V_OUT_MASK,
652 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC2_MASK),
653 AXP_DESC(AXP22X, DCDC3, "dcdc3", "vin3", 600, 1860, 20,
654 AXP22X_DCDC3_V_OUT, AXP22X_DCDC3_V_OUT_MASK,
655 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC3_MASK),
656 AXP_DESC(AXP22X, DCDC4, "dcdc4", "vin4", 600, 1540, 20,
657 AXP22X_DCDC4_V_OUT, AXP22X_DCDC4_V_OUT_MASK,
658 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC4_MASK),
659 AXP_DESC(AXP22X, DCDC5, "dcdc5", "vin5", 1000, 2550, 50,
660 AXP22X_DCDC5_V_OUT, AXP22X_DCDC5_V_OUT_MASK,
661 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC5_MASK),
662 /* secondary switchable output of DCDC1 */
663 AXP_DESC_SW(AXP22X, DC1SW, "dc1sw", NULL,
664 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK),
665 /* LDO regulator internally chained to DCDC5 */
666 AXP_DESC(AXP22X, DC5LDO, "dc5ldo", NULL, 700, 1400, 100,
667 AXP22X_DC5LDO_V_OUT, AXP22X_DC5LDO_V_OUT_MASK,
668 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DC5LDO_MASK),
669 AXP_DESC(AXP22X, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
670 AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK,
671 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO1_MASK),
672 AXP_DESC(AXP22X, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
673 AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK,
674 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO2_MASK),
675 AXP_DESC(AXP22X, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
676 AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK,
677 AXP22X_PWR_OUT_CTRL3, AXP22X_PWR_OUT_ALDO3_MASK),
678 AXP_DESC(AXP22X, DLDO1, "dldo1", "dldoin", 700, 3300, 100,
679 AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK,
680 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK),
681 AXP_DESC(AXP22X, DLDO2, "dldo2", "dldoin", 700, 3300, 100,
682 AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK,
683 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK),
684 AXP_DESC(AXP22X, DLDO3, "dldo3", "dldoin", 700, 3300, 100,
685 AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK,
686 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO3_MASK),
687 AXP_DESC(AXP22X, DLDO4, "dldo4", "dldoin", 700, 3300, 100,
688 AXP22X_DLDO4_V_OUT, AXP22X_DLDO4_V_OUT_MASK,
689 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO4_MASK),
690 AXP_DESC(AXP22X, ELDO1, "eldo1", "eldoin", 700, 3300, 100,
691 AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK,
692 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK),
693 AXP_DESC(AXP22X, ELDO2, "eldo2", "eldoin", 700, 3300, 100,
694 AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK,
695 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK),
696 AXP_DESC(AXP22X, ELDO3, "eldo3", "eldoin", 700, 3300, 100,
697 AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK,
698 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK),
699 /* Note the datasheet only guarantees reliable operation up to
700 * 3.3V, this needs to be enforced via dts provided constraints */
701 AXP_DESC_IO(AXP22X, LDO_IO0, "ldo_io0", "ips", 700, 3800, 100,
702 AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK,
703 AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
704 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
705 /* Note the datasheet only guarantees reliable operation up to
706 * 3.3V, this needs to be enforced via dts provided constraints */
707 AXP_DESC_IO(AXP22X, LDO_IO1, "ldo_io1", "ips", 700, 3800, 100,
708 AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK,
709 AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK,
710 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
711 AXP_DESC_FIXED(AXP22X, RTC_LDO, "rtc_ldo", "ips", 3000),
712 };
713
714 static const struct regulator_desc axp22x_drivevbus_regulator = {
715 .name = "drivevbus",
716 .supply_name = "drivevbus",
717 .of_match = of_match_ptr("drivevbus"),
718 .regulators_node = of_match_ptr("regulators"),
719 .type = REGULATOR_VOLTAGE,
720 .owner = THIS_MODULE,
721 .enable_reg = AXP20X_VBUS_IPSOUT_MGMT,
722 .enable_mask = AXP20X_VBUS_IPSOUT_MGMT_MASK,
723 .ops = &axp20x_ops_sw,
724 };
725
726 static const struct linear_range axp313a_dcdc1_ranges[] = {
727 REGULATOR_LINEAR_RANGE(500000, 0, 70, 10000),
728 REGULATOR_LINEAR_RANGE(1220000, 71, 87, 20000),
729 REGULATOR_LINEAR_RANGE(1600000, 88, 106, 100000),
730 };
731
732 static const struct linear_range axp313a_dcdc2_ranges[] = {
733 REGULATOR_LINEAR_RANGE(500000, 0, 70, 10000),
734 REGULATOR_LINEAR_RANGE(1220000, 71, 87, 20000),
735 };
736
737 /*
738 * This is deviating from the datasheet. The values here are taken from the
739 * BSP driver and have been confirmed by measurements.
740 */
741 static const struct linear_range axp313a_dcdc3_ranges[] = {
742 REGULATOR_LINEAR_RANGE(500000, 0, 70, 10000),
743 REGULATOR_LINEAR_RANGE(1220000, 71, 102, 20000),
744 };
745
746 static const struct regulator_desc axp313a_regulators[] = {
747 AXP_DESC_RANGES(AXP313A, DCDC1, "dcdc1", "vin1",
748 axp313a_dcdc1_ranges, AXP313A_DCDC1_NUM_VOLTAGES,
749 AXP313A_DCDC1_CONTROL, AXP313A_DCDC_V_OUT_MASK,
750 AXP313A_OUTPUT_CONTROL, BIT(0)),
751 AXP_DESC_RANGES(AXP313A, DCDC2, "dcdc2", "vin2",
752 axp313a_dcdc2_ranges, AXP313A_DCDC23_NUM_VOLTAGES,
753 AXP313A_DCDC2_CONTROL, AXP313A_DCDC_V_OUT_MASK,
754 AXP313A_OUTPUT_CONTROL, BIT(1)),
755 AXP_DESC_RANGES(AXP313A, DCDC3, "dcdc3", "vin3",
756 axp313a_dcdc3_ranges, AXP313A_DCDC23_NUM_VOLTAGES,
757 AXP313A_DCDC3_CONTROL, AXP313A_DCDC_V_OUT_MASK,
758 AXP313A_OUTPUT_CONTROL, BIT(2)),
759 AXP_DESC(AXP313A, ALDO1, "aldo1", "vin1", 500, 3500, 100,
760 AXP313A_ALDO1_CONTROL, AXP313A_LDO_V_OUT_MASK,
761 AXP313A_OUTPUT_CONTROL, BIT(3)),
762 AXP_DESC(AXP313A, DLDO1, "dldo1", "vin1", 500, 3500, 100,
763 AXP313A_DLDO1_CONTROL, AXP313A_LDO_V_OUT_MASK,
764 AXP313A_OUTPUT_CONTROL, BIT(4)),
765 AXP_DESC_FIXED(AXP313A, RTC_LDO, "rtc-ldo", "vin1", 1800),
766 };
767
768 static const struct linear_range axp717_dcdc1_ranges[] = {
769 REGULATOR_LINEAR_RANGE(500000, 0, 70, 10000),
770 REGULATOR_LINEAR_RANGE(1220000, 71, 87, 20000),
771 };
772
773 /*
774 * The manual says that the last voltage is 3.4V, encoded as 0b1101011 (107),
775 * but every other method proves that this is wrong, so it's really 106 that
776 * programs the final 3.4V.
777 */
778 static const struct linear_range axp717_dcdc2_ranges[] = {
779 REGULATOR_LINEAR_RANGE(500000, 0, 70, 10000),
780 REGULATOR_LINEAR_RANGE(1220000, 71, 87, 20000),
781 REGULATOR_LINEAR_RANGE(1600000, 88, 106, 100000),
782 };
783
784 static const struct linear_range axp717_dcdc3_ranges[] = {
785 REGULATOR_LINEAR_RANGE(500000, 0, 70, 10000),
786 REGULATOR_LINEAR_RANGE(1220000, 71, 102, 20000),
787 };
788
789 static const struct regulator_desc axp717_regulators[] = {
790 AXP_DESC_RANGES_DELAY(AXP717, DCDC1, "dcdc1", "vin1",
791 axp717_dcdc1_ranges, AXP717_DCDC1_NUM_VOLTAGES,
792 AXP717_DCDC1_CONTROL, AXP717_DCDC_V_OUT_MASK,
793 AXP717_DCDC_OUTPUT_CONTROL, BIT(0), 640),
794 AXP_DESC_RANGES_DELAY(AXP717, DCDC2, "dcdc2", "vin2",
795 axp717_dcdc2_ranges, AXP717_DCDC2_NUM_VOLTAGES,
796 AXP717_DCDC2_CONTROL, AXP717_DCDC_V_OUT_MASK,
797 AXP717_DCDC_OUTPUT_CONTROL, BIT(1), 640),
798 AXP_DESC_RANGES_DELAY(AXP717, DCDC3, "dcdc3", "vin3",
799 axp717_dcdc3_ranges, AXP717_DCDC3_NUM_VOLTAGES,
800 AXP717_DCDC3_CONTROL, AXP717_DCDC_V_OUT_MASK,
801 AXP717_DCDC_OUTPUT_CONTROL, BIT(2), 640),
802 AXP_DESC(AXP717, DCDC4, "dcdc4", "vin4", 1000, 3700, 100,
803 AXP717_DCDC4_CONTROL, AXP717_DCDC_V_OUT_MASK,
804 AXP717_DCDC_OUTPUT_CONTROL, BIT(3)),
805 AXP_DESC(AXP717, ALDO1, "aldo1", "aldoin", 500, 3500, 100,
806 AXP717_ALDO1_CONTROL, AXP717_LDO_V_OUT_MASK,
807 AXP717_LDO0_OUTPUT_CONTROL, BIT(0)),
808 AXP_DESC(AXP717, ALDO2, "aldo2", "aldoin", 500, 3500, 100,
809 AXP717_ALDO2_CONTROL, AXP717_LDO_V_OUT_MASK,
810 AXP717_LDO0_OUTPUT_CONTROL, BIT(1)),
811 AXP_DESC(AXP717, ALDO3, "aldo3", "aldoin", 500, 3500, 100,
812 AXP717_ALDO3_CONTROL, AXP717_LDO_V_OUT_MASK,
813 AXP717_LDO0_OUTPUT_CONTROL, BIT(2)),
814 AXP_DESC(AXP717, ALDO4, "aldo4", "aldoin", 500, 3500, 100,
815 AXP717_ALDO4_CONTROL, AXP717_LDO_V_OUT_MASK,
816 AXP717_LDO0_OUTPUT_CONTROL, BIT(3)),
817 AXP_DESC(AXP717, BLDO1, "bldo1", "bldoin", 500, 3500, 100,
818 AXP717_BLDO1_CONTROL, AXP717_LDO_V_OUT_MASK,
819 AXP717_LDO0_OUTPUT_CONTROL, BIT(4)),
820 AXP_DESC(AXP717, BLDO2, "bldo2", "bldoin", 500, 3500, 100,
821 AXP717_BLDO2_CONTROL, AXP717_LDO_V_OUT_MASK,
822 AXP717_LDO0_OUTPUT_CONTROL, BIT(5)),
823 AXP_DESC(AXP717, BLDO3, "bldo3", "bldoin", 500, 3500, 100,
824 AXP717_BLDO3_CONTROL, AXP717_LDO_V_OUT_MASK,
825 AXP717_LDO0_OUTPUT_CONTROL, BIT(6)),
826 AXP_DESC(AXP717, BLDO4, "bldo4", "bldoin", 500, 3500, 100,
827 AXP717_BLDO4_CONTROL, AXP717_LDO_V_OUT_MASK,
828 AXP717_LDO0_OUTPUT_CONTROL, BIT(7)),
829 AXP_DESC(AXP717, CLDO1, "cldo1", "cldoin", 500, 3500, 100,
830 AXP717_CLDO1_CONTROL, AXP717_LDO_V_OUT_MASK,
831 AXP717_LDO1_OUTPUT_CONTROL, BIT(0)),
832 AXP_DESC(AXP717, CLDO2, "cldo2", "cldoin", 500, 3500, 100,
833 AXP717_CLDO2_CONTROL, AXP717_LDO_V_OUT_MASK,
834 AXP717_LDO1_OUTPUT_CONTROL, BIT(1)),
835 AXP_DESC(AXP717, CLDO3, "cldo3", "cldoin", 500, 3500, 100,
836 AXP717_CLDO3_CONTROL, AXP717_LDO_V_OUT_MASK,
837 AXP717_LDO1_OUTPUT_CONTROL, BIT(2)),
838 AXP_DESC(AXP717, CLDO4, "cldo4", "cldoin", 500, 3500, 100,
839 AXP717_CLDO4_CONTROL, AXP717_LDO_V_OUT_MASK,
840 AXP717_LDO1_OUTPUT_CONTROL, BIT(3)),
841 AXP_DESC(AXP717, CPUSLDO, "cpusldo", "vin1", 500, 1400, 50,
842 AXP717_CPUSLDO_CONTROL, AXP717_LDO_V_OUT_MASK,
843 AXP717_LDO1_OUTPUT_CONTROL, BIT(4)),
844 AXP_DESC(AXP717, BOOST, "boost", "vin1", 4550, 5510, 64,
845 AXP717_BOOST_CONTROL, AXP717_BOOST_V_OUT_MASK,
846 AXP717_MODULE_EN_CONTROL_2, BIT(4)),
847 };
848
849 /* DCDC ranges shared with AXP813 */
850 static const struct linear_range axp803_dcdc234_ranges[] = {
851 REGULATOR_LINEAR_RANGE(500000,
852 AXP803_DCDC234_500mV_START,
853 AXP803_DCDC234_500mV_END,
854 10000),
855 REGULATOR_LINEAR_RANGE(1220000,
856 AXP803_DCDC234_1220mV_START,
857 AXP803_DCDC234_1220mV_END,
858 20000),
859 };
860
861 static const struct linear_range axp803_dcdc5_ranges[] = {
862 REGULATOR_LINEAR_RANGE(800000,
863 AXP803_DCDC5_800mV_START,
864 AXP803_DCDC5_800mV_END,
865 10000),
866 REGULATOR_LINEAR_RANGE(1140000,
867 AXP803_DCDC5_1140mV_START,
868 AXP803_DCDC5_1140mV_END,
869 20000),
870 };
871
872 static const struct linear_range axp803_dcdc6_ranges[] = {
873 REGULATOR_LINEAR_RANGE(600000,
874 AXP803_DCDC6_600mV_START,
875 AXP803_DCDC6_600mV_END,
876 10000),
877 REGULATOR_LINEAR_RANGE(1120000,
878 AXP803_DCDC6_1120mV_START,
879 AXP803_DCDC6_1120mV_END,
880 20000),
881 };
882
883 /* AXP806's CLDO2 and AXP809's DLDO1 share the same range */
884 static const struct linear_range axp803_dldo2_ranges[] = {
885 REGULATOR_LINEAR_RANGE(700000,
886 AXP803_DLDO2_700mV_START,
887 AXP803_DLDO2_700mV_END,
888 100000),
889 REGULATOR_LINEAR_RANGE(3400000,
890 AXP803_DLDO2_3400mV_START,
891 AXP803_DLDO2_3400mV_END,
892 200000),
893 };
894
895 static const struct regulator_desc axp803_regulators[] = {
896 AXP_DESC(AXP803, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,
897 AXP803_DCDC1_V_OUT, AXP803_DCDC1_V_OUT_MASK,
898 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC1_MASK),
899 AXP_DESC_RANGES(AXP803, DCDC2, "dcdc2", "vin2",
900 axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
901 AXP803_DCDC2_V_OUT, AXP803_DCDC2_V_OUT_MASK,
902 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC2_MASK),
903 AXP_DESC_RANGES(AXP803, DCDC3, "dcdc3", "vin3",
904 axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
905 AXP803_DCDC3_V_OUT, AXP803_DCDC3_V_OUT_MASK,
906 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC3_MASK),
907 AXP_DESC_RANGES(AXP803, DCDC4, "dcdc4", "vin4",
908 axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
909 AXP803_DCDC4_V_OUT, AXP803_DCDC4_V_OUT_MASK,
910 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC4_MASK),
911 AXP_DESC_RANGES(AXP803, DCDC5, "dcdc5", "vin5",
912 axp803_dcdc5_ranges, AXP803_DCDC5_NUM_VOLTAGES,
913 AXP803_DCDC5_V_OUT, AXP803_DCDC5_V_OUT_MASK,
914 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC5_MASK),
915 AXP_DESC_RANGES(AXP803, DCDC6, "dcdc6", "vin6",
916 axp803_dcdc6_ranges, AXP803_DCDC6_NUM_VOLTAGES,
917 AXP803_DCDC6_V_OUT, AXP803_DCDC6_V_OUT_MASK,
918 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC6_MASK),
919 /* secondary switchable output of DCDC1 */
920 AXP_DESC_SW(AXP803, DC1SW, "dc1sw", NULL,
921 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK),
922 AXP_DESC(AXP803, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
923 AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK,
924 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO1_MASK),
925 AXP_DESC(AXP803, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
926 AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK,
927 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO2_MASK),
928 AXP_DESC(AXP803, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
929 AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK,
930 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO3_MASK),
931 AXP_DESC(AXP803, DLDO1, "dldo1", "dldoin", 700, 3300, 100,
932 AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK,
933 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK),
934 AXP_DESC_RANGES(AXP803, DLDO2, "dldo2", "dldoin",
935 axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES,
936 AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK,
937 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK),
938 AXP_DESC(AXP803, DLDO3, "dldo3", "dldoin", 700, 3300, 100,
939 AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK,
940 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO3_MASK),
941 AXP_DESC(AXP803, DLDO4, "dldo4", "dldoin", 700, 3300, 100,
942 AXP22X_DLDO4_V_OUT, AXP22X_DLDO4_V_OUT_MASK,
943 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO4_MASK),
944 AXP_DESC(AXP803, ELDO1, "eldo1", "eldoin", 700, 1900, 50,
945 AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK,
946 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK),
947 AXP_DESC(AXP803, ELDO2, "eldo2", "eldoin", 700, 1900, 50,
948 AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK,
949 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK),
950 AXP_DESC(AXP803, ELDO3, "eldo3", "eldoin", 700, 1900, 50,
951 AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK,
952 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK),
953 AXP_DESC(AXP803, FLDO1, "fldo1", "fldoin", 700, 1450, 50,
954 AXP803_FLDO1_V_OUT, AXP803_FLDO1_V_OUT_MASK,
955 AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO1_MASK),
956 AXP_DESC(AXP803, FLDO2, "fldo2", "fldoin", 700, 1450, 50,
957 AXP803_FLDO2_V_OUT, AXP803_FLDO2_V_OUT_MASK,
958 AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO2_MASK),
959 AXP_DESC_IO(AXP803, LDO_IO0, "ldo-io0", "ips", 700, 3300, 100,
960 AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK,
961 AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
962 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
963 AXP_DESC_IO(AXP803, LDO_IO1, "ldo-io1", "ips", 700, 3300, 100,
964 AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK,
965 AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK,
966 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
967 AXP_DESC_FIXED(AXP803, RTC_LDO, "rtc-ldo", "ips", 3000),
968 };
969
970 static const struct linear_range axp806_dcdca_ranges[] = {
971 REGULATOR_LINEAR_RANGE(600000,
972 AXP806_DCDCA_600mV_START,
973 AXP806_DCDCA_600mV_END,
974 10000),
975 REGULATOR_LINEAR_RANGE(1120000,
976 AXP806_DCDCA_1120mV_START,
977 AXP806_DCDCA_1120mV_END,
978 20000),
979 };
980
981 static const struct linear_range axp806_dcdcd_ranges[] = {
982 REGULATOR_LINEAR_RANGE(600000,
983 AXP806_DCDCD_600mV_START,
984 AXP806_DCDCD_600mV_END,
985 20000),
986 REGULATOR_LINEAR_RANGE(1600000,
987 AXP806_DCDCD_1600mV_START,
988 AXP806_DCDCD_1600mV_END,
989 100000),
990 };
991
992 static const struct regulator_desc axp806_regulators[] = {
993 AXP_DESC_RANGES(AXP806, DCDCA, "dcdca", "vina",
994 axp806_dcdca_ranges, AXP806_DCDCA_NUM_VOLTAGES,
995 AXP806_DCDCA_V_CTRL, AXP806_DCDCA_V_CTRL_MASK,
996 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCA_MASK),
997 AXP_DESC(AXP806, DCDCB, "dcdcb", "vinb", 1000, 2550, 50,
998 AXP806_DCDCB_V_CTRL, AXP806_DCDCB_V_CTRL_MASK,
999 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCB_MASK),
1000 AXP_DESC_RANGES(AXP806, DCDCC, "dcdcc", "vinc",
1001 axp806_dcdca_ranges, AXP806_DCDCA_NUM_VOLTAGES,
1002 AXP806_DCDCC_V_CTRL, AXP806_DCDCC_V_CTRL_MASK,
1003 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCC_MASK),
1004 AXP_DESC_RANGES(AXP806, DCDCD, "dcdcd", "vind",
1005 axp806_dcdcd_ranges, AXP806_DCDCD_NUM_VOLTAGES,
1006 AXP806_DCDCD_V_CTRL, AXP806_DCDCD_V_CTRL_MASK,
1007 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCD_MASK),
1008 AXP_DESC(AXP806, DCDCE, "dcdce", "vine", 1100, 3400, 100,
1009 AXP806_DCDCE_V_CTRL, AXP806_DCDCE_V_CTRL_MASK,
1010 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCE_MASK),
1011 AXP_DESC(AXP806, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
1012 AXP806_ALDO1_V_CTRL, AXP806_ALDO1_V_CTRL_MASK,
1013 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_ALDO1_MASK),
1014 AXP_DESC(AXP806, ALDO2, "aldo2", "aldoin", 700, 3400, 100,
1015 AXP806_ALDO2_V_CTRL, AXP806_ALDO2_V_CTRL_MASK,
1016 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_ALDO2_MASK),
1017 AXP_DESC(AXP806, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
1018 AXP806_ALDO3_V_CTRL, AXP806_ALDO3_V_CTRL_MASK,
1019 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_ALDO3_MASK),
1020 AXP_DESC(AXP806, BLDO1, "bldo1", "bldoin", 700, 1900, 100,
1021 AXP806_BLDO1_V_CTRL, AXP806_BLDO1_V_CTRL_MASK,
1022 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO1_MASK),
1023 AXP_DESC(AXP806, BLDO2, "bldo2", "bldoin", 700, 1900, 100,
1024 AXP806_BLDO2_V_CTRL, AXP806_BLDO2_V_CTRL_MASK,
1025 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO2_MASK),
1026 AXP_DESC(AXP806, BLDO3, "bldo3", "bldoin", 700, 1900, 100,
1027 AXP806_BLDO3_V_CTRL, AXP806_BLDO3_V_CTRL_MASK,
1028 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO3_MASK),
1029 AXP_DESC(AXP806, BLDO4, "bldo4", "bldoin", 700, 1900, 100,
1030 AXP806_BLDO4_V_CTRL, AXP806_BLDO4_V_CTRL_MASK,
1031 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO4_MASK),
1032 AXP_DESC(AXP806, CLDO1, "cldo1", "cldoin", 700, 3300, 100,
1033 AXP806_CLDO1_V_CTRL, AXP806_CLDO1_V_CTRL_MASK,
1034 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_CLDO1_MASK),
1035 AXP_DESC_RANGES(AXP806, CLDO2, "cldo2", "cldoin",
1036 axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES,
1037 AXP806_CLDO2_V_CTRL, AXP806_CLDO2_V_CTRL_MASK,
1038 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_CLDO2_MASK),
1039 AXP_DESC(AXP806, CLDO3, "cldo3", "cldoin", 700, 3300, 100,
1040 AXP806_CLDO3_V_CTRL, AXP806_CLDO3_V_CTRL_MASK,
1041 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_CLDO3_MASK),
1042 AXP_DESC_SW(AXP806, SW, "sw", "swin",
1043 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_SW_MASK),
1044 };
1045
1046 static const struct linear_range axp809_dcdc4_ranges[] = {
1047 REGULATOR_LINEAR_RANGE(600000,
1048 AXP809_DCDC4_600mV_START,
1049 AXP809_DCDC4_600mV_END,
1050 20000),
1051 REGULATOR_LINEAR_RANGE(1800000,
1052 AXP809_DCDC4_1800mV_START,
1053 AXP809_DCDC4_1800mV_END,
1054 100000),
1055 };
1056
1057 static const struct regulator_desc axp809_regulators[] = {
1058 AXP_DESC(AXP809, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,
1059 AXP22X_DCDC1_V_OUT, AXP22X_DCDC1_V_OUT_MASK,
1060 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC1_MASK),
1061 AXP_DESC(AXP809, DCDC2, "dcdc2", "vin2", 600, 1540, 20,
1062 AXP22X_DCDC2_V_OUT, AXP22X_DCDC2_V_OUT_MASK,
1063 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC2_MASK),
1064 AXP_DESC(AXP809, DCDC3, "dcdc3", "vin3", 600, 1860, 20,
1065 AXP22X_DCDC3_V_OUT, AXP22X_DCDC3_V_OUT_MASK,
1066 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC3_MASK),
1067 AXP_DESC_RANGES(AXP809, DCDC4, "dcdc4", "vin4",
1068 axp809_dcdc4_ranges, AXP809_DCDC4_NUM_VOLTAGES,
1069 AXP22X_DCDC4_V_OUT, AXP22X_DCDC4_V_OUT_MASK,
1070 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC4_MASK),
1071 AXP_DESC(AXP809, DCDC5, "dcdc5", "vin5", 1000, 2550, 50,
1072 AXP22X_DCDC5_V_OUT, AXP22X_DCDC5_V_OUT_MASK,
1073 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC5_MASK),
1074 /* secondary switchable output of DCDC1 */
1075 AXP_DESC_SW(AXP809, DC1SW, "dc1sw", NULL,
1076 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK),
1077 /* LDO regulator internally chained to DCDC5 */
1078 AXP_DESC(AXP809, DC5LDO, "dc5ldo", NULL, 700, 1400, 100,
1079 AXP22X_DC5LDO_V_OUT, AXP22X_DC5LDO_V_OUT_MASK,
1080 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DC5LDO_MASK),
1081 AXP_DESC(AXP809, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
1082 AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK,
1083 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO1_MASK),
1084 AXP_DESC(AXP809, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
1085 AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK,
1086 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO2_MASK),
1087 AXP_DESC(AXP809, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
1088 AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK,
1089 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ALDO3_MASK),
1090 AXP_DESC_RANGES(AXP809, DLDO1, "dldo1", "dldoin",
1091 axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES,
1092 AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK,
1093 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK),
1094 AXP_DESC(AXP809, DLDO2, "dldo2", "dldoin", 700, 3300, 100,
1095 AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK,
1096 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK),
1097 AXP_DESC(AXP809, ELDO1, "eldo1", "eldoin", 700, 3300, 100,
1098 AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK,
1099 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK),
1100 AXP_DESC(AXP809, ELDO2, "eldo2", "eldoin", 700, 3300, 100,
1101 AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK,
1102 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK),
1103 AXP_DESC(AXP809, ELDO3, "eldo3", "eldoin", 700, 3300, 100,
1104 AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK,
1105 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK),
1106 /*
1107 * Note the datasheet only guarantees reliable operation up to
1108 * 3.3V, this needs to be enforced via dts provided constraints
1109 */
1110 AXP_DESC_IO(AXP809, LDO_IO0, "ldo_io0", "ips", 700, 3800, 100,
1111 AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK,
1112 AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
1113 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
1114 /*
1115 * Note the datasheet only guarantees reliable operation up to
1116 * 3.3V, this needs to be enforced via dts provided constraints
1117 */
1118 AXP_DESC_IO(AXP809, LDO_IO1, "ldo_io1", "ips", 700, 3800, 100,
1119 AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK,
1120 AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK,
1121 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
1122 AXP_DESC_FIXED(AXP809, RTC_LDO, "rtc_ldo", "ips", 1800),
1123 AXP_DESC_SW(AXP809, SW, "sw", "swin",
1124 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_SW_MASK),
1125 };
1126
1127 static const struct regulator_desc axp813_regulators[] = {
1128 AXP_DESC(AXP813, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,
1129 AXP803_DCDC1_V_OUT, AXP803_DCDC1_V_OUT_MASK,
1130 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC1_MASK),
1131 AXP_DESC_RANGES(AXP813, DCDC2, "dcdc2", "vin2",
1132 axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
1133 AXP803_DCDC2_V_OUT, AXP803_DCDC2_V_OUT_MASK,
1134 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC2_MASK),
1135 AXP_DESC_RANGES(AXP813, DCDC3, "dcdc3", "vin3",
1136 axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
1137 AXP803_DCDC3_V_OUT, AXP803_DCDC3_V_OUT_MASK,
1138 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC3_MASK),
1139 AXP_DESC_RANGES(AXP813, DCDC4, "dcdc4", "vin4",
1140 axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
1141 AXP803_DCDC4_V_OUT, AXP803_DCDC4_V_OUT_MASK,
1142 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC4_MASK),
1143 AXP_DESC_RANGES(AXP813, DCDC5, "dcdc5", "vin5",
1144 axp803_dcdc5_ranges, AXP803_DCDC5_NUM_VOLTAGES,
1145 AXP803_DCDC5_V_OUT, AXP803_DCDC5_V_OUT_MASK,
1146 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC5_MASK),
1147 AXP_DESC_RANGES(AXP813, DCDC6, "dcdc6", "vin6",
1148 axp803_dcdc6_ranges, AXP803_DCDC6_NUM_VOLTAGES,
1149 AXP803_DCDC6_V_OUT, AXP803_DCDC6_V_OUT_MASK,
1150 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC6_MASK),
1151 AXP_DESC_RANGES(AXP813, DCDC7, "dcdc7", "vin7",
1152 axp803_dcdc6_ranges, AXP803_DCDC6_NUM_VOLTAGES,
1153 AXP813_DCDC7_V_OUT, AXP813_DCDC7_V_OUT_MASK,
1154 AXP22X_PWR_OUT_CTRL1, AXP813_PWR_OUT_DCDC7_MASK),
1155 AXP_DESC(AXP813, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
1156 AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK,
1157 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO1_MASK),
1158 AXP_DESC(AXP813, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
1159 AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK,
1160 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO2_MASK),
1161 AXP_DESC(AXP813, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
1162 AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK,
1163 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO3_MASK),
1164 AXP_DESC(AXP813, DLDO1, "dldo1", "dldoin", 700, 3300, 100,
1165 AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK,
1166 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK),
1167 AXP_DESC_RANGES(AXP813, DLDO2, "dldo2", "dldoin",
1168 axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES,
1169 AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK,
1170 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK),
1171 AXP_DESC(AXP813, DLDO3, "dldo3", "dldoin", 700, 3300, 100,
1172 AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK,
1173 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO3_MASK),
1174 AXP_DESC(AXP813, DLDO4, "dldo4", "dldoin", 700, 3300, 100,
1175 AXP22X_DLDO4_V_OUT, AXP22X_DLDO4_V_OUT_MASK,
1176 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO4_MASK),
1177 AXP_DESC(AXP813, ELDO1, "eldo1", "eldoin", 700, 1900, 50,
1178 AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK,
1179 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK),
1180 AXP_DESC(AXP813, ELDO2, "eldo2", "eldoin", 700, 1900, 50,
1181 AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK,
1182 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK),
1183 AXP_DESC(AXP813, ELDO3, "eldo3", "eldoin", 700, 1900, 50,
1184 AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK,
1185 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK),
1186 /* to do / check ... */
1187 AXP_DESC(AXP813, FLDO1, "fldo1", "fldoin", 700, 1450, 50,
1188 AXP803_FLDO1_V_OUT, AXP803_FLDO1_V_OUT_MASK,
1189 AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO1_MASK),
1190 AXP_DESC(AXP813, FLDO2, "fldo2", "fldoin", 700, 1450, 50,
1191 AXP803_FLDO2_V_OUT, AXP803_FLDO2_V_OUT_MASK,
1192 AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO2_MASK),
1193 /*
1194 * TODO: FLDO3 = {DCDC5, FLDOIN} / 2
1195 *
1196 * This means FLDO3 effectively switches supplies at runtime,
1197 * something the regulator subsystem does not support.
1198 */
1199 AXP_DESC_FIXED(AXP813, RTC_LDO, "rtc-ldo", "ips", 1800),
1200 AXP_DESC_IO(AXP813, LDO_IO0, "ldo-io0", "ips", 700, 3300, 100,
1201 AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK,
1202 AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
1203 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
1204 AXP_DESC_IO(AXP813, LDO_IO1, "ldo-io1", "ips", 700, 3300, 100,
1205 AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK,
1206 AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK,
1207 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
1208 AXP_DESC_SW(AXP813, SW, "sw", "swin",
1209 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK),
1210 };
1211
1212 static const struct linear_range axp15060_dcdc234_ranges[] = {
1213 REGULATOR_LINEAR_RANGE(500000,
1214 AXP15060_DCDC234_500mV_START,
1215 AXP15060_DCDC234_500mV_END,
1216 10000),
1217 REGULATOR_LINEAR_RANGE(1220000,
1218 AXP15060_DCDC234_1220mV_START,
1219 AXP15060_DCDC234_1220mV_END,
1220 20000),
1221 };
1222
1223 static const struct linear_range axp15060_dcdc5_ranges[] = {
1224 REGULATOR_LINEAR_RANGE(800000,
1225 AXP15060_DCDC5_800mV_START,
1226 AXP15060_DCDC5_800mV_END,
1227 10000),
1228 REGULATOR_LINEAR_RANGE(1140000,
1229 AXP15060_DCDC5_1140mV_START,
1230 AXP15060_DCDC5_1140mV_END,
1231 20000),
1232 };
1233
1234 static const struct regulator_desc axp15060_regulators[] = {
1235 AXP_DESC(AXP15060, DCDC1, "dcdc1", "vin1", 1500, 3400, 100,
1236 AXP15060_DCDC1_V_CTRL, AXP15060_DCDC1_V_CTRL_MASK,
1237 AXP15060_PWR_OUT_CTRL1, AXP15060_PWR_OUT_DCDC1_MASK),
1238 AXP_DESC_RANGES(AXP15060, DCDC2, "dcdc2", "vin2",
1239 axp15060_dcdc234_ranges, AXP15060_DCDC234_NUM_VOLTAGES,
1240 AXP15060_DCDC2_V_CTRL, AXP15060_DCDC2_V_CTRL_MASK,
1241 AXP15060_PWR_OUT_CTRL1, AXP15060_PWR_OUT_DCDC2_MASK),
1242 AXP_DESC_RANGES(AXP15060, DCDC3, "dcdc3", "vin3",
1243 axp15060_dcdc234_ranges, AXP15060_DCDC234_NUM_VOLTAGES,
1244 AXP15060_DCDC3_V_CTRL, AXP15060_DCDC3_V_CTRL_MASK,
1245 AXP15060_PWR_OUT_CTRL1, AXP15060_PWR_OUT_DCDC3_MASK),
1246 AXP_DESC_RANGES(AXP15060, DCDC4, "dcdc4", "vin4",
1247 axp15060_dcdc234_ranges, AXP15060_DCDC234_NUM_VOLTAGES,
1248 AXP15060_DCDC4_V_CTRL, AXP15060_DCDC4_V_CTRL_MASK,
1249 AXP15060_PWR_OUT_CTRL1, AXP15060_PWR_OUT_DCDC4_MASK),
1250 AXP_DESC_RANGES(AXP15060, DCDC5, "dcdc5", "vin5",
1251 axp15060_dcdc5_ranges, AXP15060_DCDC5_NUM_VOLTAGES,
1252 AXP15060_DCDC5_V_CTRL, AXP15060_DCDC5_V_CTRL_MASK,
1253 AXP15060_PWR_OUT_CTRL1, AXP15060_PWR_OUT_DCDC5_MASK),
1254 AXP_DESC(AXP15060, DCDC6, "dcdc6", "vin6", 500, 3400, 100,
1255 AXP15060_DCDC6_V_CTRL, AXP15060_DCDC6_V_CTRL_MASK,
1256 AXP15060_PWR_OUT_CTRL1, AXP15060_PWR_OUT_DCDC6_MASK),
1257 AXP_DESC(AXP15060, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
1258 AXP15060_ALDO1_V_CTRL, AXP15060_ALDO1_V_CTRL_MASK,
1259 AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_ALDO1_MASK),
1260 AXP_DESC(AXP15060, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
1261 AXP15060_ALDO2_V_CTRL, AXP15060_ALDO2_V_CTRL_MASK,
1262 AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_ALDO2_MASK),
1263 AXP_DESC(AXP15060, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
1264 AXP15060_ALDO3_V_CTRL, AXP15060_ALDO3_V_CTRL_MASK,
1265 AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_ALDO3_MASK),
1266 AXP_DESC(AXP15060, ALDO4, "aldo4", "aldoin", 700, 3300, 100,
1267 AXP15060_ALDO4_V_CTRL, AXP15060_ALDO4_V_CTRL_MASK,
1268 AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_ALDO4_MASK),
1269 AXP_DESC(AXP15060, ALDO5, "aldo5", "aldoin", 700, 3300, 100,
1270 AXP15060_ALDO5_V_CTRL, AXP15060_ALDO5_V_CTRL_MASK,
1271 AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_ALDO5_MASK),
1272 AXP_DESC(AXP15060, BLDO1, "bldo1", "bldoin", 700, 3300, 100,
1273 AXP15060_BLDO1_V_CTRL, AXP15060_BLDO1_V_CTRL_MASK,
1274 AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_BLDO1_MASK),
1275 AXP_DESC(AXP15060, BLDO2, "bldo2", "bldoin", 700, 3300, 100,
1276 AXP15060_BLDO2_V_CTRL, AXP15060_BLDO2_V_CTRL_MASK,
1277 AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_BLDO2_MASK),
1278 AXP_DESC(AXP15060, BLDO3, "bldo3", "bldoin", 700, 3300, 100,
1279 AXP15060_BLDO3_V_CTRL, AXP15060_BLDO3_V_CTRL_MASK,
1280 AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_BLDO3_MASK),
1281 AXP_DESC(AXP15060, BLDO4, "bldo4", "bldoin", 700, 3300, 100,
1282 AXP15060_BLDO4_V_CTRL, AXP15060_BLDO4_V_CTRL_MASK,
1283 AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_BLDO4_MASK),
1284 AXP_DESC(AXP15060, BLDO5, "bldo5", "bldoin", 700, 3300, 100,
1285 AXP15060_BLDO5_V_CTRL, AXP15060_BLDO5_V_CTRL_MASK,
1286 AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_BLDO5_MASK),
1287 AXP_DESC(AXP15060, CLDO1, "cldo1", "cldoin", 700, 3300, 100,
1288 AXP15060_CLDO1_V_CTRL, AXP15060_CLDO1_V_CTRL_MASK,
1289 AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_CLDO1_MASK),
1290 AXP_DESC(AXP15060, CLDO2, "cldo2", "cldoin", 700, 3300, 100,
1291 AXP15060_CLDO2_V_CTRL, AXP15060_CLDO2_V_CTRL_MASK,
1292 AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_CLDO2_MASK),
1293 AXP_DESC(AXP15060, CLDO3, "cldo3", "cldoin", 700, 3300, 100,
1294 AXP15060_CLDO3_V_CTRL, AXP15060_CLDO3_V_CTRL_MASK,
1295 AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_CLDO3_MASK),
1296 AXP_DESC(AXP15060, CLDO4, "cldo4", "cldoin", 700, 4200, 100,
1297 AXP15060_CLDO4_V_CTRL, AXP15060_CLDO4_V_CTRL_MASK,
1298 AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_CLDO4_MASK),
1299 /* Supply comes from DCDC5 */
1300 AXP_DESC(AXP15060, CPUSLDO, "cpusldo", NULL, 700, 1400, 50,
1301 AXP15060_CPUSLDO_V_CTRL, AXP15060_CPUSLDO_V_CTRL_MASK,
1302 AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_CPUSLDO_MASK),
1303 /* Supply comes from DCDC1 */
1304 AXP_DESC_SW(AXP15060, SW, "sw", NULL,
1305 AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_SW_MASK),
1306 /* Supply comes from ALDO1 */
1307 AXP_DESC_FIXED(AXP15060, RTC_LDO, "rtc-ldo", NULL, 1800),
1308 };
1309
axp20x_set_dcdc_freq(struct platform_device * pdev,u32 dcdcfreq)1310 static int axp20x_set_dcdc_freq(struct platform_device *pdev, u32 dcdcfreq)
1311 {
1312 struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
1313 unsigned int reg = AXP20X_DCDC_FREQ;
1314 u32 min, max, def, step;
1315
1316 switch (axp20x->variant) {
1317 case AXP202_ID:
1318 case AXP209_ID:
1319 min = 750;
1320 max = 1875;
1321 def = 1500;
1322 step = 75;
1323 break;
1324 case AXP803_ID:
1325 case AXP813_ID:
1326 /*
1327 * AXP803/AXP813 DCDC work frequency setting has the same
1328 * range and step as AXP22X, but at a different register.
1329 * (See include/linux/mfd/axp20x.h)
1330 */
1331 reg = AXP803_DCDC_FREQ_CTRL;
1332 fallthrough; /* to the check below */
1333 case AXP806_ID:
1334 /*
1335 * AXP806 also have DCDC work frequency setting register at a
1336 * different position.
1337 */
1338 if (axp20x->variant == AXP806_ID)
1339 reg = AXP806_DCDC_FREQ_CTRL;
1340 fallthrough;
1341 case AXP221_ID:
1342 case AXP223_ID:
1343 case AXP809_ID:
1344 min = 1800;
1345 max = 4050;
1346 def = 3000;
1347 step = 150;
1348 break;
1349 case AXP313A_ID:
1350 case AXP323_ID:
1351 case AXP717_ID:
1352 case AXP15060_ID:
1353 /* The DCDC PWM frequency seems to be fixed to 3 MHz. */
1354 if (dcdcfreq != 0) {
1355 dev_err(&pdev->dev,
1356 "DCDC frequency on this PMIC is fixed to 3 MHz.\n");
1357 return -EINVAL;
1358 }
1359
1360 return 0;
1361 default:
1362 dev_err(&pdev->dev,
1363 "Setting DCDC frequency for unsupported AXP variant\n");
1364 return -EINVAL;
1365 }
1366
1367 if (dcdcfreq == 0)
1368 dcdcfreq = def;
1369
1370 if (dcdcfreq < min) {
1371 dcdcfreq = min;
1372 dev_warn(&pdev->dev, "DCDC frequency too low. Set to %ukHz\n",
1373 min);
1374 }
1375
1376 if (dcdcfreq > max) {
1377 dcdcfreq = max;
1378 dev_warn(&pdev->dev, "DCDC frequency too high. Set to %ukHz\n",
1379 max);
1380 }
1381
1382 dcdcfreq = (dcdcfreq - min) / step;
1383
1384 return regmap_update_bits(axp20x->regmap, reg,
1385 AXP20X_FREQ_DCDC_MASK, dcdcfreq);
1386 }
1387
axp20x_regulator_parse_dt(struct platform_device * pdev)1388 static int axp20x_regulator_parse_dt(struct platform_device *pdev)
1389 {
1390 struct device_node *np, *regulators;
1391 int ret = 0;
1392 u32 dcdcfreq = 0;
1393
1394 np = of_node_get(pdev->dev.parent->of_node);
1395 if (!np)
1396 return 0;
1397
1398 regulators = of_get_child_by_name(np, "regulators");
1399 if (!regulators) {
1400 dev_warn(&pdev->dev, "regulators node not found\n");
1401 } else {
1402 of_property_read_u32(regulators, "x-powers,dcdc-freq", &dcdcfreq);
1403 ret = axp20x_set_dcdc_freq(pdev, dcdcfreq);
1404 if (ret < 0) {
1405 dev_err(&pdev->dev, "Error setting dcdc frequency: %d\n", ret);
1406 }
1407 of_node_put(regulators);
1408 }
1409
1410 of_node_put(np);
1411 return ret;
1412 }
1413
axp20x_set_dcdc_workmode(struct regulator_dev * rdev,int id,u32 workmode)1414 static int axp20x_set_dcdc_workmode(struct regulator_dev *rdev, int id, u32 workmode)
1415 {
1416 struct axp20x_dev *axp20x = rdev_get_drvdata(rdev);
1417 unsigned int reg = AXP20X_DCDC_MODE;
1418 unsigned int mask;
1419
1420 switch (axp20x->variant) {
1421 case AXP202_ID:
1422 case AXP209_ID:
1423 if ((id != AXP20X_DCDC2) && (id != AXP20X_DCDC3))
1424 return -EINVAL;
1425
1426 mask = AXP20X_WORKMODE_DCDC2_MASK;
1427 if (id == AXP20X_DCDC3)
1428 mask = AXP20X_WORKMODE_DCDC3_MASK;
1429
1430 workmode <<= ffs(mask) - 1;
1431 break;
1432
1433 case AXP806_ID:
1434 /*
1435 * AXP806 DCDC regulator IDs have the same range as AXP22X.
1436 * (See include/linux/mfd/axp20x.h)
1437 */
1438 reg = AXP806_DCDC_MODE_CTRL2;
1439 fallthrough; /* to the check below */
1440 case AXP221_ID:
1441 case AXP223_ID:
1442 case AXP809_ID:
1443 if (id < AXP22X_DCDC1 || id > AXP22X_DCDC5)
1444 return -EINVAL;
1445
1446 mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP22X_DCDC1);
1447 workmode <<= id - AXP22X_DCDC1;
1448 break;
1449
1450 case AXP803_ID:
1451 if (id < AXP803_DCDC1 || id > AXP803_DCDC6)
1452 return -EINVAL;
1453
1454 mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP803_DCDC1);
1455 workmode <<= id - AXP803_DCDC1;
1456 break;
1457
1458 case AXP813_ID:
1459 if (id < AXP813_DCDC1 || id > AXP813_DCDC7)
1460 return -EINVAL;
1461
1462 mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP813_DCDC1);
1463 workmode <<= id - AXP813_DCDC1;
1464 break;
1465
1466 case AXP15060_ID:
1467 reg = AXP15060_DCDC_MODE_CTRL2;
1468 if (id < AXP15060_DCDC1 || id > AXP15060_DCDC6)
1469 return -EINVAL;
1470
1471 mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP15060_DCDC1);
1472 workmode <<= id - AXP15060_DCDC1;
1473 break;
1474
1475 default:
1476 /* should not happen */
1477 WARN_ON(1);
1478 return -EINVAL;
1479 }
1480
1481 return regmap_update_bits(rdev->regmap, reg, mask, workmode);
1482 }
1483
1484 /*
1485 * This function checks whether a regulator is part of a poly-phase
1486 * output setup based on the registers settings. Returns true if it is.
1487 */
axp20x_is_polyphase_slave(struct axp20x_dev * axp20x,int id)1488 static bool axp20x_is_polyphase_slave(struct axp20x_dev *axp20x, int id)
1489 {
1490 u32 reg = 0;
1491
1492 /*
1493 * Currently in our supported AXP variants, only AXP803, AXP806,
1494 * AXP813 and AXP15060 have polyphase regulators.
1495 */
1496 switch (axp20x->variant) {
1497 case AXP803_ID:
1498 case AXP813_ID:
1499 regmap_read(axp20x->regmap, AXP803_POLYPHASE_CTRL, ®);
1500
1501 switch (id) {
1502 case AXP803_DCDC3:
1503 return !!(reg & AXP803_DCDC23_POLYPHASE_DUAL);
1504 case AXP803_DCDC6:
1505 return !!(reg & AXP803_DCDC56_POLYPHASE_DUAL);
1506 }
1507 break;
1508
1509 case AXP806_ID:
1510 regmap_read(axp20x->regmap, AXP806_DCDC_MODE_CTRL2, ®);
1511
1512 switch (id) {
1513 case AXP806_DCDCB:
1514 return (((reg & AXP806_DCDCABC_POLYPHASE_MASK) ==
1515 AXP806_DCDCAB_POLYPHASE_DUAL) ||
1516 ((reg & AXP806_DCDCABC_POLYPHASE_MASK) ==
1517 AXP806_DCDCABC_POLYPHASE_TRI));
1518 case AXP806_DCDCC:
1519 return ((reg & AXP806_DCDCABC_POLYPHASE_MASK) ==
1520 AXP806_DCDCABC_POLYPHASE_TRI);
1521 case AXP806_DCDCE:
1522 return !!(reg & AXP806_DCDCDE_POLYPHASE_DUAL);
1523 }
1524 break;
1525
1526 case AXP15060_ID:
1527 regmap_read(axp20x->regmap, AXP15060_DCDC_MODE_CTRL1, ®);
1528
1529 switch (id) {
1530 case AXP15060_DCDC3:
1531 return !!(reg & AXP15060_DCDC23_POLYPHASE_DUAL_MASK);
1532 case AXP15060_DCDC6:
1533 return !!(reg & AXP15060_DCDC46_POLYPHASE_DUAL_MASK);
1534 }
1535 break;
1536
1537 case AXP323_ID:
1538 regmap_read(axp20x->regmap, AXP323_DCDC_MODE_CTRL2, ®);
1539
1540 switch (id) {
1541 case AXP313A_DCDC2:
1542 return !!(reg & BIT(1));
1543 }
1544 break;
1545
1546 default:
1547 return false;
1548 }
1549
1550 return false;
1551 }
1552
axp20x_regulator_probe(struct platform_device * pdev)1553 static int axp20x_regulator_probe(struct platform_device *pdev)
1554 {
1555 struct regulator_dev *rdev;
1556 struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
1557 const struct regulator_desc *regulators;
1558 struct regulator_config config = {
1559 .dev = pdev->dev.parent,
1560 .regmap = axp20x->regmap,
1561 .driver_data = axp20x,
1562 };
1563 int ret, i, nregulators;
1564 u32 workmode;
1565 const char *dcdc1_name = axp22x_regulators[AXP22X_DCDC1].name;
1566 const char *dcdc5_name = axp22x_regulators[AXP22X_DCDC5].name;
1567 const char *aldo1_name = axp15060_regulators[AXP15060_ALDO1].name;
1568 bool drivevbus = false;
1569
1570 switch (axp20x->variant) {
1571 case AXP202_ID:
1572 case AXP209_ID:
1573 regulators = axp20x_regulators;
1574 nregulators = AXP20X_REG_ID_MAX;
1575 break;
1576 case AXP221_ID:
1577 case AXP223_ID:
1578 regulators = axp22x_regulators;
1579 nregulators = AXP22X_REG_ID_MAX;
1580 drivevbus = of_property_read_bool(pdev->dev.parent->of_node,
1581 "x-powers,drive-vbus-en");
1582 break;
1583 case AXP313A_ID:
1584 case AXP323_ID:
1585 regulators = axp313a_regulators;
1586 nregulators = AXP313A_REG_ID_MAX;
1587 break;
1588 case AXP717_ID:
1589 regulators = axp717_regulators;
1590 nregulators = AXP717_REG_ID_MAX;
1591 break;
1592 case AXP803_ID:
1593 regulators = axp803_regulators;
1594 nregulators = AXP803_REG_ID_MAX;
1595 drivevbus = of_property_read_bool(pdev->dev.parent->of_node,
1596 "x-powers,drive-vbus-en");
1597 break;
1598 case AXP806_ID:
1599 regulators = axp806_regulators;
1600 nregulators = AXP806_REG_ID_MAX;
1601 break;
1602 case AXP809_ID:
1603 regulators = axp809_regulators;
1604 nregulators = AXP809_REG_ID_MAX;
1605 break;
1606 case AXP813_ID:
1607 regulators = axp813_regulators;
1608 nregulators = AXP813_REG_ID_MAX;
1609 drivevbus = of_property_read_bool(pdev->dev.parent->of_node,
1610 "x-powers,drive-vbus-en");
1611 break;
1612 case AXP15060_ID:
1613 regulators = axp15060_regulators;
1614 nregulators = AXP15060_REG_ID_MAX;
1615 break;
1616 default:
1617 dev_err(&pdev->dev, "Unsupported AXP variant: %d\n",
1618 axp20x->variant);
1619 return -EINVAL;
1620 }
1621
1622 /* This only sets the dcdc freq. Ignore any errors */
1623 axp20x_regulator_parse_dt(pdev);
1624
1625 for (i = 0; i < nregulators; i++) {
1626 const struct regulator_desc *desc = ®ulators[i];
1627 struct regulator_desc *new_desc;
1628
1629 /*
1630 * If this regulator is a slave in a poly-phase setup,
1631 * skip it, as its controls are bound to the master
1632 * regulator and won't work.
1633 */
1634 if (axp20x_is_polyphase_slave(axp20x, i))
1635 continue;
1636
1637 /* Support for AXP813's FLDO3 is not implemented */
1638 if (axp20x->variant == AXP813_ID && i == AXP813_FLDO3)
1639 continue;
1640
1641 /*
1642 * Regulators DC1SW, DC5LDO and RTCLDO on AXP15060 are
1643 * connected internally, so we have to handle their supply
1644 * names separately.
1645 *
1646 * We always register the regulators in proper sequence,
1647 * so the supply names are correctly read. See the last
1648 * part of this loop to see where we save the DT defined
1649 * name.
1650 */
1651 if ((regulators == axp22x_regulators && i == AXP22X_DC1SW) ||
1652 (regulators == axp803_regulators && i == AXP803_DC1SW) ||
1653 (regulators == axp809_regulators && i == AXP809_DC1SW) ||
1654 (regulators == axp15060_regulators && i == AXP15060_SW)) {
1655 new_desc = devm_kzalloc(&pdev->dev, sizeof(*desc),
1656 GFP_KERNEL);
1657 if (!new_desc)
1658 return -ENOMEM;
1659
1660 *new_desc = regulators[i];
1661 new_desc->supply_name = dcdc1_name;
1662 desc = new_desc;
1663 }
1664
1665 if ((regulators == axp22x_regulators && i == AXP22X_DC5LDO) ||
1666 (regulators == axp809_regulators && i == AXP809_DC5LDO) ||
1667 (regulators == axp15060_regulators && i == AXP15060_CPUSLDO)) {
1668 new_desc = devm_kzalloc(&pdev->dev, sizeof(*desc),
1669 GFP_KERNEL);
1670 if (!new_desc)
1671 return -ENOMEM;
1672
1673 *new_desc = regulators[i];
1674 new_desc->supply_name = dcdc5_name;
1675 desc = new_desc;
1676 }
1677
1678
1679 if (regulators == axp15060_regulators && i == AXP15060_RTC_LDO) {
1680 new_desc = devm_kzalloc(&pdev->dev, sizeof(*desc),
1681 GFP_KERNEL);
1682 if (!new_desc)
1683 return -ENOMEM;
1684
1685 *new_desc = regulators[i];
1686 new_desc->supply_name = aldo1_name;
1687 desc = new_desc;
1688 }
1689
1690 rdev = devm_regulator_register(&pdev->dev, desc, &config);
1691 if (IS_ERR(rdev)) {
1692 dev_err(&pdev->dev, "Failed to register %s\n",
1693 regulators[i].name);
1694
1695 return PTR_ERR(rdev);
1696 }
1697
1698 ret = of_property_read_u32(rdev->dev.of_node,
1699 "x-powers,dcdc-workmode",
1700 &workmode);
1701 if (!ret) {
1702 if (axp20x_set_dcdc_workmode(rdev, i, workmode))
1703 dev_err(&pdev->dev, "Failed to set workmode on %s\n",
1704 rdev->desc->name);
1705 }
1706
1707 /*
1708 * Save AXP22X DCDC1 / DCDC5 / AXP15060 ALDO1 regulator names for later.
1709 */
1710 if ((regulators == axp22x_regulators && i == AXP22X_DCDC1) ||
1711 (regulators == axp809_regulators && i == AXP809_DCDC1) ||
1712 (regulators == axp15060_regulators && i == AXP15060_DCDC1))
1713 of_property_read_string(rdev->dev.of_node,
1714 "regulator-name",
1715 &dcdc1_name);
1716
1717 if ((regulators == axp22x_regulators && i == AXP22X_DCDC5) ||
1718 (regulators == axp809_regulators && i == AXP809_DCDC5) ||
1719 (regulators == axp15060_regulators && i == AXP15060_DCDC5))
1720 of_property_read_string(rdev->dev.of_node,
1721 "regulator-name",
1722 &dcdc5_name);
1723
1724 if (regulators == axp15060_regulators && i == AXP15060_ALDO1)
1725 of_property_read_string(rdev->dev.of_node,
1726 "regulator-name",
1727 &aldo1_name);
1728 }
1729
1730 if (drivevbus) {
1731 /* Change N_VBUSEN sense pin to DRIVEVBUS output pin */
1732 regmap_update_bits(axp20x->regmap, AXP20X_OVER_TMP,
1733 AXP22X_MISC_N_VBUSEN_FUNC, 0);
1734 rdev = devm_regulator_register(&pdev->dev,
1735 &axp22x_drivevbus_regulator,
1736 &config);
1737 if (IS_ERR(rdev)) {
1738 dev_err(&pdev->dev, "Failed to register drivevbus\n");
1739 return PTR_ERR(rdev);
1740 }
1741 }
1742
1743 return 0;
1744 }
1745
1746 static struct platform_driver axp20x_regulator_driver = {
1747 .probe = axp20x_regulator_probe,
1748 .driver = {
1749 .name = "axp20x-regulator",
1750 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1751 },
1752 };
1753
1754 module_platform_driver(axp20x_regulator_driver);
1755
1756 MODULE_LICENSE("GPL v2");
1757 MODULE_AUTHOR("Carlo Caione <carlo@caione.org>");
1758 MODULE_DESCRIPTION("Regulator Driver for AXP20X PMIC");
1759 MODULE_ALIAS("platform:axp20x-regulator");
1760