1 /*
2 * Copyright (C) 2015-2020 Advanced Micro Devices, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #ifndef __AMDGPU_DM_H__
27 #define __AMDGPU_DM_H__
28
29 #include <drm/display/drm_dp_mst_helper.h>
30 #include <drm/drm_atomic.h>
31 #include <drm/drm_connector.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_plane.h>
34 #include "link_service_types.h"
35 #include <drm/drm_writeback.h>
36
37 /*
38 * This file contains the definition for amdgpu_display_manager
39 * and its API for amdgpu driver's use.
40 * This component provides all the display related functionality
41 * and this is the only component that calls DAL API.
42 * The API contained here intended for amdgpu driver use.
43 * The API that is called directly from KMS framework is located
44 * in amdgpu_dm_kms.h file
45 */
46
47 #define AMDGPU_DM_MAX_DISPLAY_INDEX 31
48
49 #define AMDGPU_DM_MAX_CRTC 6
50
51 #define AMDGPU_DM_MAX_NUM_EDP 2
52
53 #define AMDGPU_DMUB_NOTIFICATION_MAX 8
54
55 #define HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID 0x00001A
56 #define AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE 0x40
57 #define HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3 0x3
58
59 #define AMDGPU_HDR_MULT_DEFAULT (0x100000000LL)
60
61 /*
62 #include "include/amdgpu_dal_power_if.h"
63 #include "amdgpu_dm_irq.h"
64 */
65
66 #include "irq_types.h"
67 #include "signal_types.h"
68 #include "amdgpu_dm_crc.h"
69 #include "mod_info_packet.h"
70 struct aux_payload;
71 struct set_config_cmd_payload;
72 enum aux_return_code_type;
73 enum set_config_status;
74
75 /* Forward declarations */
76 struct amdgpu_device;
77 struct amdgpu_crtc;
78 struct drm_device;
79 struct dc;
80 struct amdgpu_bo;
81 struct dmub_srv;
82 struct dc_plane_state;
83 struct dmub_notification;
84 struct dmub_cmd_fused_request;
85
86 struct amd_vsdb_block {
87 unsigned char ieee_id[3];
88 unsigned char version;
89 unsigned char feature_caps;
90 };
91
92 struct common_irq_params {
93 struct amdgpu_device *adev;
94 enum dc_irq_source irq_src;
95 atomic64_t previous_timestamp;
96 };
97
98 /**
99 * struct dm_compressor_info - Buffer info used by frame buffer compression
100 * @cpu_addr: MMIO cpu addr
101 * @bo_ptr: Pointer to the buffer object
102 * @gpu_addr: MMIO gpu addr
103 */
104 struct dm_compressor_info {
105 void *cpu_addr;
106 struct amdgpu_bo *bo_ptr;
107 uint64_t gpu_addr;
108 };
109
110 typedef void (*dmub_notify_interrupt_callback_t)(struct amdgpu_device *adev, struct dmub_notification *notify);
111
112 /**
113 * struct dmub_hpd_work - Handle time consuming work in low priority outbox IRQ
114 *
115 * @handle_hpd_work: Work to be executed in a separate thread to handle hpd_low_irq
116 * @dmub_notify: notification for callback function
117 * @adev: amdgpu_device pointer
118 */
119 struct dmub_hpd_work {
120 struct work_struct handle_hpd_work;
121 struct dmub_notification *dmub_notify;
122 struct amdgpu_device *adev;
123 };
124
125 /**
126 * struct vblank_control_work - Work data for vblank control
127 * @work: Kernel work data for the work event
128 * @dm: amdgpu display manager device
129 * @acrtc: amdgpu CRTC instance for which the event has occurred
130 * @stream: DC stream for which the event has occurred
131 * @enable: true if enabling vblank
132 */
133 struct vblank_control_work {
134 struct work_struct work;
135 struct amdgpu_display_manager *dm;
136 struct amdgpu_crtc *acrtc;
137 struct dc_stream_state *stream;
138 bool enable;
139 };
140
141 /**
142 * struct idle_workqueue - Work data for periodic action in idle
143 * @work: Kernel work data for the work event
144 * @dm: amdgpu display manager device
145 * @enable: true if idle worker is enabled
146 * @running: true if idle worker is running
147 */
148 struct idle_workqueue {
149 struct work_struct work;
150 struct amdgpu_display_manager *dm;
151 bool enable;
152 bool running;
153 };
154
155 #define MAX_LUMINANCE_DATA_POINTS 99
156
157 /**
158 * struct amdgpu_dm_luminance_data - Custom luminance data
159 * @luminance: Luminance in percent
160 * @input_signal: Input signal in range 0-255
161 */
162 struct amdgpu_dm_luminance_data {
163 u8 luminance;
164 u8 input_signal;
165 } __packed;
166
167 /**
168 * struct amdgpu_dm_backlight_caps - Information about backlight
169 *
170 * Describe the backlight support for ACPI or eDP AUX.
171 */
172 struct amdgpu_dm_backlight_caps {
173 /**
174 * @ext_caps: Keep the data struct with all the information about the
175 * display support for HDR.
176 */
177 union dpcd_sink_ext_caps *ext_caps;
178 /**
179 * @aux_min_input_signal: Min brightness value supported by the display
180 */
181 u32 aux_min_input_signal;
182 /**
183 * @aux_max_input_signal: Max brightness value supported by the display
184 * in nits.
185 */
186 u32 aux_max_input_signal;
187 /**
188 * @min_input_signal: minimum possible input in range 0-255.
189 */
190 int min_input_signal;
191 /**
192 * @max_input_signal: maximum possible input in range 0-255.
193 */
194 int max_input_signal;
195 /**
196 * @caps_valid: true if these values are from the ACPI interface.
197 */
198 bool caps_valid;
199 /**
200 * @aux_support: Describes if the display supports AUX backlight.
201 */
202 bool aux_support;
203 /**
204 * @ac_level: the default brightness if booted on AC
205 */
206 u8 ac_level;
207 /**
208 * @dc_level: the default brightness if booted on DC
209 */
210 u8 dc_level;
211 /**
212 * @data_points: the number of custom luminance data points
213 */
214 u8 data_points;
215 /**
216 * @luminance_data: custom luminance data
217 */
218 struct amdgpu_dm_luminance_data luminance_data[MAX_LUMINANCE_DATA_POINTS];
219 };
220
221 /**
222 * struct dal_allocation - Tracks mapped FB memory for SMU communication
223 * @list: list of dal allocations
224 * @bo: GPU buffer object
225 * @cpu_ptr: CPU virtual address of the GPU buffer object
226 * @gpu_addr: GPU virtual address of the GPU buffer object
227 */
228 struct dal_allocation {
229 struct list_head list;
230 struct amdgpu_bo *bo;
231 void *cpu_ptr;
232 u64 gpu_addr;
233 };
234
235 /**
236 * struct hpd_rx_irq_offload_work_queue - Work queue to handle hpd_rx_irq
237 * offload work
238 */
239 struct hpd_rx_irq_offload_work_queue {
240 /**
241 * @wq: workqueue structure to queue offload work.
242 */
243 struct workqueue_struct *wq;
244 /**
245 * @offload_lock: To protect fields of offload work queue.
246 */
247 spinlock_t offload_lock;
248 /**
249 * @is_handling_link_loss: Used to prevent inserting link loss event when
250 * we're handling link loss
251 */
252 bool is_handling_link_loss;
253 /**
254 * @is_handling_mst_msg_rdy_event: Used to prevent inserting mst message
255 * ready event when we're already handling mst message ready event
256 */
257 bool is_handling_mst_msg_rdy_event;
258 /**
259 * @aconnector: The aconnector that this work queue is attached to
260 */
261 struct amdgpu_dm_connector *aconnector;
262 };
263
264 /**
265 * struct hpd_rx_irq_offload_work - hpd_rx_irq offload work structure
266 */
267 struct hpd_rx_irq_offload_work {
268 /**
269 * @work: offload work
270 */
271 struct work_struct work;
272 /**
273 * @data: reference irq data which is used while handling offload work
274 */
275 union hpd_irq_data data;
276 /**
277 * @offload_wq: offload work queue that this work is queued to
278 */
279 struct hpd_rx_irq_offload_work_queue *offload_wq;
280 /**
281 * @adev: amdgpu_device pointer
282 */
283 struct amdgpu_device *adev;
284 };
285
286 /**
287 * struct amdgpu_display_manager - Central amdgpu display manager device
288 *
289 * @dc: Display Core control structure
290 * @adev: AMDGPU base driver structure
291 * @ddev: DRM base driver structure
292 * @display_indexes_num: Max number of display streams supported
293 * @irq_handler_list_table_lock: Synchronizes access to IRQ tables
294 * @backlight_dev: Backlight control device
295 * @backlight_link: Link on which to control backlight
296 * @backlight_caps: Capabilities of the backlight device
297 * @freesync_module: Module handling freesync calculations
298 * @hdcp_workqueue: AMDGPU content protection queue
299 * @fw_dmcu: Reference to DMCU firmware
300 * @dmcu_fw_version: Version of the DMCU firmware
301 * @soc_bounding_box: SOC bounding box values provided by gpu_info FW
302 * @cached_state: Caches device atomic state for suspend/resume
303 * @cached_dc_state: Cached state of content streams
304 * @compressor: Frame buffer compression buffer. See &struct dm_compressor_info
305 * @force_timing_sync: set via debugfs. When set, indicates that all connected
306 * displays will be forced to synchronize.
307 * @dmcub_trace_event_en: enable dmcub trace events
308 * @dmub_outbox_params: DMUB Outbox parameters
309 * @num_of_edps: number of backlight eDPs
310 * @disable_hpd_irq: disables all HPD and HPD RX interrupt handling in the
311 * driver when true
312 * @dmub_aux_transfer_done: struct completion used to indicate when DMUB
313 * transfers are done
314 * @delayed_hpd_wq: work queue used to delay DMUB HPD work
315 */
316 struct amdgpu_display_manager {
317
318 struct dc *dc;
319
320 /**
321 * @dmub_srv:
322 *
323 * DMUB service, used for controlling the DMUB on hardware
324 * that supports it. The pointer to the dmub_srv will be
325 * NULL on hardware that does not support it.
326 */
327 struct dmub_srv *dmub_srv;
328
329 /**
330 * @dmub_notify:
331 *
332 * Notification from DMUB.
333 */
334
335 struct dmub_notification *dmub_notify;
336
337 /**
338 * @dmub_callback:
339 *
340 * Callback functions to handle notification from DMUB.
341 */
342
343 dmub_notify_interrupt_callback_t dmub_callback[AMDGPU_DMUB_NOTIFICATION_MAX];
344
345 /**
346 * @dmub_thread_offload:
347 *
348 * Flag to indicate if callback is offload.
349 */
350
351 bool dmub_thread_offload[AMDGPU_DMUB_NOTIFICATION_MAX];
352
353 /**
354 * @dmub_fb_info:
355 *
356 * Framebuffer regions for the DMUB.
357 */
358 struct dmub_srv_fb_info *dmub_fb_info;
359
360 /**
361 * @dmub_fw:
362 *
363 * DMUB firmware, required on hardware that has DMUB support.
364 */
365 const struct firmware *dmub_fw;
366
367 /**
368 * @dmub_bo:
369 *
370 * Buffer object for the DMUB.
371 */
372 struct amdgpu_bo *dmub_bo;
373
374 /**
375 * @dmub_bo_gpu_addr:
376 *
377 * GPU virtual address for the DMUB buffer object.
378 */
379 u64 dmub_bo_gpu_addr;
380
381 /**
382 * @dmub_bo_cpu_addr:
383 *
384 * CPU address for the DMUB buffer object.
385 */
386 void *dmub_bo_cpu_addr;
387
388 /**
389 * @dmcub_fw_version:
390 *
391 * DMCUB firmware version.
392 */
393 uint32_t dmcub_fw_version;
394
395 /**
396 * @cgs_device:
397 *
398 * The Common Graphics Services device. It provides an interface for
399 * accessing registers.
400 */
401 struct cgs_device *cgs_device;
402
403 struct amdgpu_device *adev;
404 struct drm_device *ddev;
405 u16 display_indexes_num;
406
407 /**
408 * @atomic_obj:
409 *
410 * In combination with &dm_atomic_state it helps manage
411 * global atomic state that doesn't map cleanly into existing
412 * drm resources, like &dc_context.
413 */
414 struct drm_private_obj atomic_obj;
415
416 /**
417 * @dc_lock:
418 *
419 * Guards access to DC functions that can issue register write
420 * sequences.
421 */
422 struct mutex dc_lock;
423
424 /**
425 * @audio_lock:
426 *
427 * Guards access to audio instance changes.
428 */
429 struct mutex audio_lock;
430
431 /**
432 * @audio_component:
433 *
434 * Used to notify ELD changes to sound driver.
435 */
436 struct drm_audio_component *audio_component;
437
438 /**
439 * @audio_registered:
440 *
441 * True if the audio component has been registered
442 * successfully, false otherwise.
443 */
444 bool audio_registered;
445
446 /**
447 * @irq_handler_list_low_tab:
448 *
449 * Low priority IRQ handler table.
450 *
451 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ
452 * source. Low priority IRQ handlers are deferred to a workqueue to be
453 * processed. Hence, they can sleep.
454 *
455 * Note that handlers are called in the same order as they were
456 * registered (FIFO).
457 */
458 struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER];
459
460 /**
461 * @irq_handler_list_high_tab:
462 *
463 * High priority IRQ handler table.
464 *
465 * It is a n*m table, same as &irq_handler_list_low_tab. However,
466 * handlers in this table are not deferred and are called immediately.
467 */
468 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER];
469
470 /**
471 * @pflip_params:
472 *
473 * Page flip IRQ parameters, passed to registered handlers when
474 * triggered.
475 */
476 struct common_irq_params
477 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1];
478
479 /**
480 * @vblank_params:
481 *
482 * Vertical blanking IRQ parameters, passed to registered handlers when
483 * triggered.
484 */
485 struct common_irq_params
486 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1];
487
488 /**
489 * @vline0_params:
490 *
491 * OTG vertical interrupt0 IRQ parameters, passed to registered
492 * handlers when triggered.
493 */
494 struct common_irq_params
495 vline0_params[DC_IRQ_SOURCE_DC6_VLINE0 - DC_IRQ_SOURCE_DC1_VLINE0 + 1];
496
497 /**
498 * @vupdate_params:
499 *
500 * Vertical update IRQ parameters, passed to registered handlers when
501 * triggered.
502 */
503 struct common_irq_params
504 vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1];
505
506 /**
507 * @dmub_trace_params:
508 *
509 * DMUB trace event IRQ parameters, passed to registered handlers when
510 * triggered.
511 */
512 struct common_irq_params
513 dmub_trace_params[1];
514
515 struct common_irq_params
516 dmub_outbox_params[1];
517
518 spinlock_t irq_handler_list_table_lock;
519
520 struct backlight_device *backlight_dev[AMDGPU_DM_MAX_NUM_EDP];
521
522 const struct dc_link *backlight_link[AMDGPU_DM_MAX_NUM_EDP];
523
524 uint8_t num_of_edps;
525
526 struct amdgpu_dm_backlight_caps backlight_caps[AMDGPU_DM_MAX_NUM_EDP];
527
528 struct mod_freesync *freesync_module;
529 struct hdcp_workqueue *hdcp_workqueue;
530
531 /**
532 * @vblank_control_workqueue:
533 *
534 * Deferred work for vblank control events.
535 */
536 struct workqueue_struct *vblank_control_workqueue;
537
538 /**
539 * @idle_workqueue:
540 *
541 * Periodic work for idle events.
542 */
543 struct idle_workqueue *idle_workqueue;
544
545 struct drm_atomic_state *cached_state;
546 struct dc_state *cached_dc_state;
547
548 struct dm_compressor_info compressor;
549
550 const struct firmware *fw_dmcu;
551 uint32_t dmcu_fw_version;
552 /**
553 * @soc_bounding_box:
554 *
555 * gpu_info FW provided soc bounding box struct or 0 if not
556 * available in FW
557 */
558 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
559
560 /**
561 * @active_vblank_irq_count:
562 *
563 * number of currently active vblank irqs
564 */
565 uint32_t active_vblank_irq_count;
566
567 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
568 /**
569 * @secure_display_ctx:
570 *
571 * Store secure display relevant info. e.g. the ROI information
572 * , the work_struct to command dmub, etc.
573 */
574 struct secure_display_context secure_display_ctx;
575 #endif
576 /**
577 * @hpd_rx_offload_wq:
578 *
579 * Work queue to offload works of hpd_rx_irq
580 */
581 struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq;
582 /**
583 * @mst_encoders:
584 *
585 * fake encoders used for DP MST.
586 */
587 struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC];
588 bool force_timing_sync;
589 bool disable_hpd_irq;
590 bool dmcub_trace_event_en;
591 /**
592 * @da_list:
593 *
594 * DAL fb memory allocation list, for communication with SMU.
595 */
596 struct list_head da_list;
597 struct completion dmub_aux_transfer_done;
598 struct workqueue_struct *delayed_hpd_wq;
599
600 /**
601 * @brightness:
602 *
603 * cached backlight values.
604 */
605 u32 brightness[AMDGPU_DM_MAX_NUM_EDP];
606 /**
607 * @actual_brightness:
608 *
609 * last successfully applied backlight values.
610 */
611 u32 actual_brightness[AMDGPU_DM_MAX_NUM_EDP];
612
613 /**
614 * @aux_hpd_discon_quirk:
615 *
616 * quirk for hpd discon while aux is on-going.
617 * occurred on certain intel platform
618 */
619 bool aux_hpd_discon_quirk;
620
621 /**
622 * @edp0_on_dp1_quirk:
623 *
624 * quirk for platforms that put edp0 on DP1.
625 */
626 bool edp0_on_dp1_quirk;
627
628 /**
629 * @dpia_aux_lock:
630 *
631 * Guards access to DPIA AUX
632 */
633 struct mutex dpia_aux_lock;
634
635 /**
636 * @bb_from_dmub:
637 *
638 * Bounding box data read from dmub during early initialization for DCN4+
639 * Data is stored as a byte array that should be casted to the appropriate bb struct
640 */
641 void *bb_from_dmub;
642
643 /**
644 * @oem_i2c:
645 *
646 * OEM i2c bus
647 */
648 struct amdgpu_i2c_adapter *oem_i2c;
649
650 /**
651 * @fused_io:
652 *
653 * dmub fused io interface
654 */
655 struct fused_io_sync {
656 struct completion replied;
657 char reply_data[0x40]; // Cannot include dmub_cmd here
658 } fused_io[8];
659 };
660
661 enum dsc_clock_force_state {
662 DSC_CLK_FORCE_DEFAULT = 0,
663 DSC_CLK_FORCE_ENABLE,
664 DSC_CLK_FORCE_DISABLE,
665 };
666
667 struct dsc_preferred_settings {
668 enum dsc_clock_force_state dsc_force_enable;
669 uint32_t dsc_num_slices_v;
670 uint32_t dsc_num_slices_h;
671 uint32_t dsc_bits_per_pixel;
672 bool dsc_force_disable_passthrough;
673 };
674
675 enum mst_progress_status {
676 MST_STATUS_DEFAULT = 0,
677 MST_PROBE = BIT(0),
678 MST_REMOTE_EDID = BIT(1),
679 MST_ALLOCATE_NEW_PAYLOAD = BIT(2),
680 MST_CLEAR_ALLOCATED_PAYLOAD = BIT(3),
681 };
682
683 /**
684 * struct amdgpu_hdmi_vsdb_info - Keep track of the VSDB info
685 *
686 * AMDGPU supports FreeSync over HDMI by using the VSDB section, and this
687 * struct is useful to keep track of the display-specific information about
688 * FreeSync.
689 */
690 struct amdgpu_hdmi_vsdb_info {
691 /**
692 * @amd_vsdb_version: Vendor Specific Data Block Version, should be
693 * used to determine which Vendor Specific InfoFrame (VSIF) to send.
694 */
695 unsigned int amd_vsdb_version;
696
697 /**
698 * @freesync_supported: FreeSync Supported.
699 */
700 bool freesync_supported;
701
702 /**
703 * @min_refresh_rate_hz: FreeSync Minimum Refresh Rate in Hz.
704 */
705 unsigned int min_refresh_rate_hz;
706
707 /**
708 * @max_refresh_rate_hz: FreeSync Maximum Refresh Rate in Hz
709 */
710 unsigned int max_refresh_rate_hz;
711
712 /**
713 * @replay_mode: Replay supported
714 */
715 bool replay_mode;
716 };
717
718 struct amdgpu_dm_connector {
719
720 struct drm_connector base;
721 uint32_t connector_id;
722 int bl_idx;
723
724 struct cec_notifier *notifier;
725
726 /* we need to mind the EDID between detect
727 and get modes due to analog/digital/tvencoder */
728 const struct drm_edid *drm_edid;
729
730 /* shared with amdgpu */
731 struct amdgpu_hpd hpd;
732
733 /* number of modes generated from EDID at 'dc_sink' */
734 int num_modes;
735
736 /* The 'old' sink - before an HPD.
737 * The 'current' sink is in dc_link->sink. */
738 struct dc_sink *dc_sink;
739 struct dc_link *dc_link;
740
741 /**
742 * @dc_em_sink: Reference to the emulated (virtual) sink.
743 */
744 struct dc_sink *dc_em_sink;
745
746 /* DM only */
747 struct drm_dp_mst_topology_mgr mst_mgr;
748 struct amdgpu_dm_dp_aux dm_dp_aux;
749 struct drm_dp_mst_port *mst_output_port;
750 struct amdgpu_dm_connector *mst_root;
751 struct drm_dp_aux *dsc_aux;
752 uint32_t mst_local_bw;
753 uint16_t vc_full_pbn;
754 struct mutex handle_mst_msg_ready;
755
756 /* TODO see if we can merge with ddc_bus or make a dm_connector */
757 struct amdgpu_i2c_adapter *i2c;
758
759 /* Monitor range limits */
760 /**
761 * @min_vfreq: Minimal frequency supported by the display in Hz. This
762 * value is set to zero when there is no FreeSync support.
763 */
764 int min_vfreq;
765
766 /**
767 * @max_vfreq: Maximum frequency supported by the display in Hz. This
768 * value is set to zero when there is no FreeSync support.
769 */
770 int max_vfreq ;
771
772 /* Audio instance - protected by audio_lock. */
773 int audio_inst;
774
775 struct mutex hpd_lock;
776
777 bool fake_enable;
778 bool force_yuv420_output;
779 struct dsc_preferred_settings dsc_settings;
780 union dp_downstream_port_present mst_downstream_port_present;
781 /* Cached display modes */
782 struct drm_display_mode freesync_vid_base;
783
784 int sr_skip_count;
785 bool disallow_edp_enter_psr;
786
787 /* Record progress status of mst*/
788 uint8_t mst_status;
789
790 /* Automated testing */
791 bool timing_changed;
792 struct dc_crtc_timing *timing_requested;
793
794 /* Adaptive Sync */
795 bool pack_sdp_v1_3;
796 enum adaptive_sync_type as_type;
797 struct amdgpu_hdmi_vsdb_info vsdb_info;
798 };
799
amdgpu_dm_set_mst_status(uint8_t * status,uint8_t flags,bool set)800 static inline void amdgpu_dm_set_mst_status(uint8_t *status,
801 uint8_t flags, bool set)
802 {
803 if (set)
804 *status |= flags;
805 else
806 *status &= ~flags;
807 }
808
809 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base)
810
811 struct amdgpu_dm_wb_connector {
812 struct drm_writeback_connector base;
813 struct dc_link *link;
814 };
815
816 #define to_amdgpu_dm_wb_connector(x) container_of(x, struct amdgpu_dm_wb_connector, base)
817
818 extern const struct amdgpu_ip_block_version dm_ip_block;
819
820 /* enum amdgpu_transfer_function: pre-defined transfer function supported by AMD.
821 *
822 * It includes standardized transfer functions and pure power functions. The
823 * transfer function coefficients are available at modules/color/color_gamma.c
824 */
825 enum amdgpu_transfer_function {
826 AMDGPU_TRANSFER_FUNCTION_DEFAULT,
827 AMDGPU_TRANSFER_FUNCTION_SRGB_EOTF,
828 AMDGPU_TRANSFER_FUNCTION_BT709_INV_OETF,
829 AMDGPU_TRANSFER_FUNCTION_PQ_EOTF,
830 AMDGPU_TRANSFER_FUNCTION_IDENTITY,
831 AMDGPU_TRANSFER_FUNCTION_GAMMA22_EOTF,
832 AMDGPU_TRANSFER_FUNCTION_GAMMA24_EOTF,
833 AMDGPU_TRANSFER_FUNCTION_GAMMA26_EOTF,
834 AMDGPU_TRANSFER_FUNCTION_SRGB_INV_EOTF,
835 AMDGPU_TRANSFER_FUNCTION_BT709_OETF,
836 AMDGPU_TRANSFER_FUNCTION_PQ_INV_EOTF,
837 AMDGPU_TRANSFER_FUNCTION_GAMMA22_INV_EOTF,
838 AMDGPU_TRANSFER_FUNCTION_GAMMA24_INV_EOTF,
839 AMDGPU_TRANSFER_FUNCTION_GAMMA26_INV_EOTF,
840 AMDGPU_TRANSFER_FUNCTION_COUNT
841 };
842
843 struct dm_plane_state {
844 struct drm_plane_state base;
845 struct dc_plane_state *dc_state;
846
847 /* Plane color mgmt */
848 /**
849 * @degamma_lut:
850 *
851 * 1D LUT for mapping framebuffer/plane pixel data before sampling or
852 * blending operations. It's usually applied to linearize input space.
853 * The blob (if not NULL) is an array of &struct drm_color_lut.
854 */
855 struct drm_property_blob *degamma_lut;
856 /**
857 * @degamma_tf:
858 *
859 * Predefined transfer function to tell DC driver the input space to
860 * linearize.
861 */
862 enum amdgpu_transfer_function degamma_tf;
863 /**
864 * @hdr_mult:
865 *
866 * Multiplier to 'gain' the plane. When PQ is decoded using the fixed
867 * func transfer function to the internal FP16 fb, 1.0 -> 80 nits (on
868 * AMD at least). When sRGB is decoded, 1.0 -> 1.0, obviously.
869 * Therefore, 1.0 multiplier = 80 nits for SDR content. So if you
870 * want, 203 nits for SDR content, pass in (203.0 / 80.0). Format is
871 * S31.32 sign-magnitude.
872 *
873 * HDR multiplier can wide range beyond [0.0, 1.0]. This means that PQ
874 * TF is needed for any subsequent linear-to-non-linear transforms.
875 */
876 __u64 hdr_mult;
877 /**
878 * @ctm:
879 *
880 * Color transformation matrix. The blob (if not NULL) is a &struct
881 * drm_color_ctm_3x4.
882 */
883 struct drm_property_blob *ctm;
884 /**
885 * @shaper_lut: shaper lookup table blob. The blob (if not NULL) is an
886 * array of &struct drm_color_lut.
887 */
888 struct drm_property_blob *shaper_lut;
889 /**
890 * @shaper_tf:
891 *
892 * Predefined transfer function to delinearize color space.
893 */
894 enum amdgpu_transfer_function shaper_tf;
895 /**
896 * @lut3d: 3D lookup table blob. The blob (if not NULL) is an array of
897 * &struct drm_color_lut.
898 */
899 struct drm_property_blob *lut3d;
900 /**
901 * @blend_lut: blend lut lookup table blob. The blob (if not NULL) is an
902 * array of &struct drm_color_lut.
903 */
904 struct drm_property_blob *blend_lut;
905 /**
906 * @blend_tf:
907 *
908 * Pre-defined transfer function for converting plane pixel data before
909 * applying blend LUT.
910 */
911 enum amdgpu_transfer_function blend_tf;
912 };
913
914 enum amdgpu_dm_cursor_mode {
915 DM_CURSOR_NATIVE_MODE = 0,
916 DM_CURSOR_OVERLAY_MODE,
917 };
918
919 struct dm_crtc_state {
920 struct drm_crtc_state base;
921 struct dc_stream_state *stream;
922
923 bool cm_has_degamma;
924 bool cm_is_degamma_srgb;
925
926 bool mpo_requested;
927
928 int update_type;
929 int active_planes;
930
931 int crc_skip_count;
932
933 bool freesync_vrr_info_changed;
934
935 bool dsc_force_changed;
936 bool vrr_supported;
937 struct mod_freesync_config freesync_config;
938 struct dc_info_packet vrr_infopacket;
939
940 int abm_level;
941
942 /**
943 * @regamma_tf:
944 *
945 * Pre-defined transfer function for converting internal FB -> wire
946 * encoding.
947 */
948 enum amdgpu_transfer_function regamma_tf;
949
950 enum amdgpu_dm_cursor_mode cursor_mode;
951 };
952
953 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base)
954
955 struct dm_atomic_state {
956 struct drm_private_state base;
957
958 struct dc_state *context;
959 };
960
961 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base)
962
963 struct dm_connector_state {
964 struct drm_connector_state base;
965
966 enum amdgpu_rmx_type scaling;
967 uint8_t underscan_vborder;
968 uint8_t underscan_hborder;
969 bool underscan_enable;
970 bool freesync_capable;
971 bool update_hdcp;
972 uint8_t abm_level;
973 int vcpi_slots;
974 uint64_t pbn;
975 };
976
977 #define to_dm_connector_state(x)\
978 container_of((x), struct dm_connector_state, base)
979
980 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector);
981 struct drm_connector_state *
982 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector);
983 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
984 struct drm_connector_state *state,
985 struct drm_property *property,
986 uint64_t val);
987
988 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
989 const struct drm_connector_state *state,
990 struct drm_property *property,
991 uint64_t *val);
992
993 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev);
994
995 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
996 struct amdgpu_dm_connector *aconnector,
997 int connector_type,
998 struct dc_link *link,
999 int link_index);
1000
1001 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
1002 const struct drm_display_mode *mode);
1003
1004 void dm_restore_drm_connector_state(struct drm_device *dev,
1005 struct drm_connector *connector);
1006
1007 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
1008 const struct drm_edid *drm_edid);
1009
1010 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev);
1011
1012 /* 3D LUT max size is 17x17x17 (4913 entries) */
1013 #define MAX_COLOR_3DLUT_SIZE 17
1014 #define MAX_COLOR_3DLUT_BITDEPTH 12
1015 int amdgpu_dm_verify_lut3d_size(struct amdgpu_device *adev,
1016 struct drm_plane_state *plane_state);
1017 /* 1D LUT size */
1018 #define MAX_COLOR_LUT_ENTRIES 4096
1019 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */
1020 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256
1021
1022 void amdgpu_dm_init_color_mod(void);
1023 int amdgpu_dm_create_color_properties(struct amdgpu_device *adev);
1024 int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state);
1025 int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc);
1026 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,
1027 struct drm_plane_state *plane_state,
1028 struct dc_plane_state *dc_plane_state);
1029
1030 void amdgpu_dm_update_connector_after_detect(
1031 struct amdgpu_dm_connector *aconnector);
1032
1033 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs;
1034
1035 int amdgpu_dm_process_dmub_aux_transfer_sync(struct dc_context *ctx, unsigned int link_index,
1036 struct aux_payload *payload, enum aux_return_code_type *operation_result);
1037
1038 bool amdgpu_dm_execute_fused_io(
1039 struct amdgpu_device *dev,
1040 struct dc_link *link,
1041 union dmub_rb_cmd *commands,
1042 uint8_t count,
1043 uint32_t timeout_us
1044 );
1045
1046 int amdgpu_dm_process_dmub_set_config_sync(struct dc_context *ctx, unsigned int link_index,
1047 struct set_config_cmd_payload *payload, enum set_config_status *operation_result);
1048
1049 struct dc_stream_state *
1050 create_validate_stream_for_sink(struct drm_connector *connector,
1051 const struct drm_display_mode *drm_mode,
1052 const struct dm_connector_state *dm_state,
1053 const struct dc_stream_state *old_stream);
1054
1055 int dm_atomic_get_state(struct drm_atomic_state *state,
1056 struct dm_atomic_state **dm_state);
1057
1058 struct drm_connector *
1059 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
1060 struct drm_crtc *crtc);
1061
1062 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth);
1063 struct idle_workqueue *idle_create_workqueue(struct amdgpu_device *adev);
1064
1065 void *dm_allocate_gpu_mem(struct amdgpu_device *adev,
1066 enum dc_gpu_mem_alloc_type type,
1067 size_t size,
1068 long long *addr);
1069 void dm_free_gpu_mem(struct amdgpu_device *adev,
1070 enum dc_gpu_mem_alloc_type type,
1071 void *addr);
1072
1073 bool amdgpu_dm_is_headless(struct amdgpu_device *adev);
1074
1075 void hdmi_cec_set_edid(struct amdgpu_dm_connector *aconnector);
1076 void hdmi_cec_unset_edid(struct amdgpu_dm_connector *aconnector);
1077 int amdgpu_dm_initialize_hdmi_connector(struct amdgpu_dm_connector *aconnector);
1078
1079 void retrieve_dmi_info(struct amdgpu_display_manager *dm);
1080
1081 #endif /* __AMDGPU_DM_H__ */
1082