| /src/sys/contrib/dev/mediatek/mt76/ |
| H A D | mmio.c | 28 writel(val, dev->mmio.regs + offset); in mt76_mmio_wr()
30 writel(val, (u8 *)dev->mmio.regs + offset); in mt76_mmio_wr()
48 writel(get_unaligned_le32(data + i), in mt76_mmio_write_copy()
51 writel(get_unaligned_le32((const u8 *)data + i), in mt76_mmio_write_copy()
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| H A D | dma.h | 70 writel(_val, &(_q)->regs->_field); \
105 writel(_val, &(_q)->regs->_field); \
112 #define Q_WRITE(_q, _field, _val) writel(_val, &(_q)->regs->_field)
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| /src/contrib/ofed/libcxgb4/ |
| H A D | t4.h | 60 #define writel(v, a) do { *((volatile u32 *)(a)) = cpu_to_pci32(v); } while (0) macro
488 writel(QID_V(wq->sq.bar2_qid) | PIDX_T5_V(inc), in t4_ring_sq_db()
522 writel(QID_V(wq->sq.qid & wq->qid_mask) | PIDX_V(inc), wq->sq.udb); in t4_ring_sq_db()
537 writel(QID_V(wq->rq.bar2_qid) | PIDX_T5_V(inc), in t4_ring_rq_db()
546 writel(QID_V(wq->rq.qid & wq->qid_mask) | PIDX_V(inc), wq->rq.udb); in t4_ring_rq_db()
601 writel(val, cq->ugts); in t4_arm_cq()
606 writel(val, cq->ugts); in t4_arm_cq()
639 writel(val, cq->ugts); in t4_hwcq_consume()
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| /src/sys/compat/linuxkpi/common/include/linux/ |
| H A D | io.h | 197 #undef writel
199 writel(uint32_t v, volatile void *addr) in writel() function
205 #define writel(v, addr) writel(v, addr) macro
384 writel(v, addr); in iowrite32()
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| H A D | iosys-map.h | 144 uint32_t: writel(val, addr), \
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| /src/sys/dev/cxgbe/iw_cxgbe/ |
| H A D | t4.h | 495 writel(V_PIDX_T5(inc) | V_QID(wq->sq.bar2_qid), in t4_ring_sq_db()
519 writel(V_PIDX_T5(inc) | V_QID(wq->rq.bar2_qid), in t4_ring_rq_db()
570 writel(val | V_INGRESSQID(cq->bar2_qid), in write_gts()
586 writel(val | V_INGRESSQID(cq->bar2_qid), in t4_arm_cq()
591 writel(val | V_INGRESSQID(cq->bar2_qid), in t4_arm_cq()
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| /src/sys/dev/mana/ |
| H A D | shm_channel.c | 279 writel((char *)sc->base + i * SMC_BASIC_UNIT, *dword++); in mana_smc_setup_hwc()
319 writel((char *)sc->base + SMC_LAST_DWORD * SMC_BASIC_UNIT, in mana_smc_teardown_hwc()
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| /src/sys/contrib/device-tree/Bindings/ |
| H A D | common-properties.txt | 17 unconditionally (e.g. readl/writel). Use this if you know the
20 endianness of the kernel binary (e.g. LE vmlinux -> readl/writel,
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| /src/usr.sbin/lpr/common_source/ |
| H A D | startdaemon.c | 83 if (writel(s, "\1", pp->printer, "\n", (char *)0) <= 0) { in startdaemon()
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| H A D | net.c | 260 writel(int strm, ...) in writel() function
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| H A D | lp.h | 315 ssize_t writel(int _strm, ...);
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| /src/sys/dev/irdma/ |
| H A D | icrdma_hw.c | 110 writel(val, dev->hw_regs[IRDMA_GLINT_DYN_CTL] + idx); in icrdma_ena_irq()
121 writel(0, dev->hw_regs[IRDMA_GLINT_DYN_CTL] + idx); in icrdma_disable_irq()
141 writel(reg_val, dev->hw_regs[IRDMA_GLINT_CEQCTL] + ceq_id); in icrdma_cfg_ceq()
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| H A D | osdep.h | 193 #define db_wr32(value, a) writel((value), (a))
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| H A D | irdma_ctrl.c | 3170 writel(0, cqp->dev->hw_regs[IRDMA_CQPTAIL]); in irdma_sc_cqp_init()
3171 writel(0, cqp->dev->hw_regs[IRDMA_CQPDB]); in irdma_sc_cqp_init()
3172 writel(0, cqp->dev->hw_regs[IRDMA_CCQPSTATUS]); in irdma_sc_cqp_init()
3257 writel(p1, cqp->dev->hw_regs[IRDMA_CCQPHIGH]); in irdma_sc_cqp_create()
3258 writel(p2, cqp->dev->hw_regs[IRDMA_CCQPLOW]); in irdma_sc_cqp_create()
3349 writel(0, cqp->dev->hw_regs[IRDMA_CCQPHIGH]); in irdma_sc_cqp_destroy()
3350 writel(0, cqp->dev->hw_regs[IRDMA_CCQPLOW]); in irdma_sc_cqp_destroy()
4044 writel(0, dev->hw_regs[IRDMA_PFINT_AEQCTL]); in irdma_sc_aeq_destroy()
5397 writel(reg_val, dev->hw_regs[IRDMA_PFINT_AEQCTL]); in irdma_cfg_aeq()
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| /src/sys/dev/hptmv/ |
| H A D | mv.c | 63 writel((void *)((ULONG_PTR)base + offset), val); in MV_REG_WRITE_DWORD()
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| /src/sys/dev/mlx4/mlx4_core/ |
| H A D | mlx4_reset.c | 119 writel(MLX4_RESET_VALUE, reset + MLX4_RESET_OFFSET); in mlx4_reset()
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| /src/sys/dev/mthca/ |
| H A D | mthca_eq.c | 216 writel(eqn_mask, dev->eq_regs.arbel.eq_arm); in arbel_eq_req_not()
398 writel(dev->eq_table.clr_mask, dev->eq_table.clr_int); in mthca_tavor_interrupt()
404 writel(ecr, dev->eq_regs.tavor.ecr_base + in mthca_tavor_interrupt()
438 writel(dev->eq_table.clr_mask, dev->eq_table.clr_int); in mthca_arbel_interrupt()
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| H A D | mthca_reset.c | 169 writel(MTHCA_RESET_VALUE, reset); in mthca_reset()
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| /src/sys/dev/bnxt/bnxt_re/ |
| H A D | qplib_rcfw.c | 282 writel(cmdq_prod, cmdq->cmdq_mbox.prod); in __send_message_no_waiter()
283 writel(RCFW_CMDQ_TRIG_VAL, cmdq->cmdq_mbox.db); in __send_message_no_waiter()
383 writel(cmdq_prod, cmdq->cmdq_mbox.prod); in __send_message()
384 writel(RCFW_CMDQ_TRIG_VAL, cmdq->cmdq_mbox.db); in __send_message()
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| /src/sys/contrib/dev/mediatek/mt76/mt7915/ |
| H A D | pci.c | 98 writel(hif_idx | MT_PCIE_RECOG_ID_SEM, in mt7915_pci_init_hif2()
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| /src/sys/dev/aq/ |
| H A D | aq_hw.h | 45 #define AQ_WRITE_REG(hw, reg, value) writel(((hw)->hw_addr + (reg)), htole32(value))
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| /src/sys/contrib/dev/mediatek/mt76/mt7996/ |
| H A D | pci.c | 87 writel(hif_idx | MT_PCIE_RECOG_ID_SEM, in mt7996_pci_init_hif2()
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| /src/sys/contrib/dev/athk/ath11k/ |
| H A D | mhi.c | 318 writel(val, addr); in ath11k_mhi_op_write_reg()
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| /src/sys/contrib/dev/athk/ath12k/ |
| H A D | mhi.c | 350 writel(val, addr); in ath12k_mhi_op_write_reg()
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| /src/sys/i386/include/ |
| H A D | cpufunc.h | 49 #define writel(va, d) (*(volatile uint32_t *) (va) = (d)) macro
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