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Searched refs:uart_getreg (Results 1 – 10 of 10) sorted by relevance

/src/sys/arm/freescale/vybrid/ !
H A Dvf_uart.c156 while (!(uart_getreg(bas, UART_S1) & UART_S1_TDRE)) in vf_uart_putc()
167 usr1 = uart_getreg(bas, UART_S1); in vf_uart_rxready()
182 while (!(uart_getreg(bas, UART_S1) & UART_S1_RDRF)) in vf_uart_getc()
185 c = uart_getreg(bas, UART_D); in vf_uart_getc()
218 reg = uart_getreg(bas, UART_C2); in uart_reinit()
227 reg = uart_getreg(bas, UART_BDH); in uart_reinit()
235 reg = uart_getreg(bas, UART_C4); in uart_reinit()
240 reg = uart_getreg(bas, UART_C2); in uart_reinit()
302 reg = uart_getreg(bas, UART_C2); in vf_uart_bus_attach()
374 usr1 = uart_getreg(bas, UART_S1); in vf_uart_bus_ipend()
[all …]
/src/sys/dev/uart/ !
H A Duart_dev_ns8250.c154 iir = uart_getreg(bas, REG_IIR); in ns8250_clrint()
158 lsr = uart_getreg(bas, REG_LSR); in ns8250_clrint()
160 (void)uart_getreg(bas, REG_DATA); in ns8250_clrint()
162 (void)uart_getreg(bas, REG_DATA); in ns8250_clrint()
164 (void)uart_getreg(bas, REG_MSR); in ns8250_clrint()
166 iir = uart_getreg(bas, REG_IIR); in ns8250_clrint()
176 lcr = uart_getreg(bas, REG_LCR); in ns8250_get_divisor()
179 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); in ns8250_get_divisor()
238 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) in ns8250_drain()
260 while (limit && (uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { in ns8250_drain()
[all …]
H A Duart_dev_mvebu.c175 ctrl = uart_getreg(bas, UART_CTRL); in uart_mvebu_param()
203 ccr = uart_getreg(bas, UART_CCR); in uart_mvebu_param()
228 uart_setreg(bas, UART_CTRL, uart_getreg(bas, UART_CTRL) & in uart_mvebu_init()
238 while (uart_getreg(bas, UART_STAT) & STAT_TX_FIFO_FULL) in uart_mvebu_putc()
246 if (uart_getreg(bas, UART_STAT) & STAT_RX_RDY) in uart_mvebu_rxready()
257 while (!(uart_getreg(bas, UART_STAT) & STAT_RX_RDY)) in uart_mvebu_getc()
260 c = uart_getreg(bas, UART_RBR) & 0xff; in uart_mvebu_getc()
331 ctrl = uart_getreg(bas, UART_CTRL); in uart_mvebu_bus_attach()
361 ctrl = uart_getreg(bas, UART_CTRL); in uart_mvebu_bus_flush()
407 ctrl = uart_getreg(bas, UART_CTRL); in uart_mvebu_bus_ioctl()
[all …]
H A Duart_dev_msm.c233 if (!(uart_getreg(bas, UART_DM_SR) & UART_DM_SR_TXEMT)) { in msm_putc()
234 while ((uart_getreg(bas, UART_DM_ISR) & UART_DM_TX_READY) == 0 in msm_putc()
243 while ((uart_getreg(bas, UART_DM_SR) & UART_DM_SR_TXRDY) == 0) in msm_putc()
255 return ((uart_getreg(bas, UART_DM_SR) & UART_DM_SR_RXRDY) == in msm_rxready()
267 while ((uart_getreg(bas, UART_DM_SR) & UART_DM_SR_RXRDY) != in msm_getc()
272 if (uart_getreg(bas, UART_DM_SR) & UART_DM_SR_UART_OVERRUN) in msm_getc()
276 c = uart_getreg(bas, UART_DM_RF(0)); in msm_getc()
412 while (uart_getreg(bas, UART_DM_SR) & UART_DM_SR_RXRDY) { in msm_bus_receive()
420 c = uart_getreg(bas, UART_DM_RF(0)); in msm_bus_receive()
H A Duart_dev_z8530.c68 return (uart_getreg(bas, REG_CTRL)); in uart_getmreg()
230 while (!(uart_getreg(bas, REG_CTRL) & BES_TXE)) in z8530_putc()
240 return ((uart_getreg(bas, REG_CTRL) & BES_RXA) != 0 ? 1 : 0); in z8530_rxready()
250 while (!(uart_getreg(bas, REG_CTRL) & BES_RXA)) { in z8530_getc()
256 c = uart_getreg(bas, REG_DATA); in z8530_getc()
543 xc = uart_getreg(bas, REG_DATA); in z8530_bus_receive()
561 (void)uart_getreg(bas, REG_DATA); in z8530_bus_receive()
H A Duart_dev_ti8250.c84 while (uart_getreg(&sc->sc_bas, SYSS_REG) & SYSS_STATUS_RESETDONE) in ti8250_bus_probe()
H A Duart.h56 uart_getreg(struct uart_bas *bas, int reg) in uart_getreg() function
/src/sys/riscv/sifive/ !
H A Dsifive_uart.c127 while ((uart_getreg(bas, SFUART_TXDATA) & SFUART_TXDATA_FULL) in sfuart_putc()
144 return ((uart_getreg(bas, SFUART_IRQ_PENDING) & in sfuart_rxready()
155 while (((c = uart_getreg(bas, SFUART_RXDATA)) & in sfuart_getc()
266 reg = uart_getreg(bas, SFUART_TXDATA); in sfuart_bus_flush()
272 reg = uart_getreg(bas, SFUART_RXDATA); in sfuart_bus_flush()
337 reg = uart_getreg(bas, SFUART_DIV); in sfuart_bus_ioctl()
367 reg = uart_getreg(bas, SFUART_IRQ_PENDING); in sfuart_bus_ipend()
368 ie = uart_getreg(bas, SFUART_IRQ_ENABLE); in sfuart_bus_ipend()
404 reg = uart_getreg(bas, SFUART_TXCTRL); in sfuart_bus_param()
432 reg = uart_getreg(bas, SFUART_RXDATA); in sfuart_bus_receive()
[all …]
/src/sys/arm/nvidia/ !
H A Dtegra_uart.c80 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; in tegra_uart_attach()
100 ier = uart_getreg(bas, REG_IER); in tegra_uart_grab()
103 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0) in tegra_uart_grab()
/src/sys/arm64/apple/ !
H A Dexynos_uart.c243 uart_setreg(bas, SSCOM_UCON, uart_getreg(bas, SSCOM_UCON) | in exynos4210_init_common()
247 uart_setreg(bas, SSCOM_UCON, uart_getreg(bas, SSCOM_UCON) | in exynos4210_init_common()
328 return (uart_getreg(bas, SSCOM_URXH)); in exynos4210_getc()
454 uart_rx_put(sc, uart_getreg(&sc->sc_bas, SSCOM_URXH)); in exynos4210_bus_receive()