| /src/sys/dev/cxgb/common/ |
| H A D | cxgb_mc5.c | 95 t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_CMD, cmd); in mc5_cmd_write()
102 t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_DATA0, v1); in dbgi_wr_data3()
103 t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_DATA1, v2); in dbgi_wr_data3()
104 t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_DATA2, v3); in dbgi_wr_data3()
121 t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_ADDR0, addr_lo); in mc5_write()
183 t3_write_reg(adap, A_MC5_DB_RSP_LATENCY, in init_idt52100()
185 t3_write_reg(adap, A_MC5_DB_PART_ID_INDEX, 2); in init_idt52100()
191 t3_write_reg(adap, A_MC5_DB_POPEN_DATA_WR_CMD, IDT_CMD_WRITE); in init_idt52100()
192 t3_write_reg(adap, A_MC5_DB_POPEN_MASK_WR_CMD, IDT_CMD_WRITE); in init_idt52100()
193 t3_write_reg(adap, A_MC5_DB_AOPEN_SRCH_CMD, IDT_CMD_SEARCH); in init_idt52100()
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| H A D | cxgb_t3_hw.c | 85 t3_write_reg(adapter, p->reg_addr + offset, p->val); in t3_write_regs()
104 t3_write_reg(adapter, addr, v | val); in t3_set_reg_field()
125 t3_write_reg(adap, addr_reg, start_idx); in t3_read_indirect()
162 t3_write_reg(adap, mc7->offset + A_MC7_BD_ADDR, in t3_mc7_bd_read()
164 t3_write_reg(adap, mc7->offset + A_MC7_BD_OP, 0); in t3_mc7_bd_read()
210 t3_write_reg(adapter, A_I2C_OP, in t3_i2c_read8()
234 t3_write_reg(adapter, A_I2C_DATA, V_I2C_DATA(val)); in t3_i2c_write8()
235 t3_write_reg(adapter, A_I2C_OP, in t3_i2c_write8()
253 t3_write_reg(adap, A_MI1_CFG, val); in mi1_init()
272 t3_write_reg(adapter, A_MI1_ADDR, addr); in t3_mi1_read()
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| H A D | cxgb_xgmac.c | 76 t3_write_reg(adap, ctrl, adap->params.vpd.xauicfg[macidx(mac)] | in xaui_serdes_reset()
162 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, F_MAC_RESET_); in t3_mac_init()
190 t3_write_reg(adap, A_XGM_RX_MAX_PKT_SIZE + oft, in t3_mac_init()
199 t3_write_reg(adap, A_XGM_TX_CTRL + oft, F_TXEN); in t3_mac_init()
200 t3_write_reg(adap, A_XGM_RX_CTRL + oft, F_RXEN); in t3_mac_init()
208 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, val); in t3_mac_init()
241 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, F_MAC_RESET_); in t3_mac_reset()
245 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CFG_CH0 + idx); in t3_mac_reset()
251 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CFG_CH0 + idx); in t3_mac_reset()
252 t3_write_reg(adap, A_TP_PIO_DATA, 0xc0000011); in t3_mac_reset()
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| /src/sys/dev/cxgb/ |
| H A D | cxgb_sge.c | 445 t3_write_reg(adap, A_SG_CONTROL, ctrl); in t3_sge_init()
446 t3_write_reg(adap, A_SG_EGR_RCQ_DRB_THRSH, V_HIRCQDRBTHRSH(512) | in t3_sge_init()
448 t3_write_reg(adap, A_SG_TIMER_TICK, core_ticks_per_usec(adap) / 10); in t3_sge_init()
449 t3_write_reg(adap, A_SG_CMDQ_CREDIT_TH, V_THRESHOLD(32) | in t3_sge_init()
451 t3_write_reg(adap, A_SG_HI_DRB_HI_THRSH, in t3_sge_init()
453 t3_write_reg(adap, A_SG_HI_DRB_LO_THRSH, 256); in t3_sge_init()
454 t3_write_reg(adap, A_SG_LO_DRB_HI_THRSH, 1000); in t3_sge_init()
455 t3_write_reg(adap, A_SG_LO_DRB_LO_THRSH, 256); in t3_sge_init()
456 t3_write_reg(adap, A_SG_OCO_BASE, V_BASE1(0xfff)); in t3_sge_init()
457 t3_write_reg(adap, A_SG_DRB_PRI_THRESH, 63 * 1024); in t3_sge_init()
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| H A D | cxgb_main.c | 1124 t3_write_reg(sc, A_XGM_TX_CTRL, 0); in t3_fatal_err()
1125 t3_write_reg(sc, A_XGM_RX_CTRL, 0); in t3_fatal_err()
1126 t3_write_reg(sc, XGM_REG(A_XGM_TX_CTRL, 1), 0); in t3_fatal_err()
1127 t3_write_reg(sc, XGM_REG(A_XGM_RX_CTRL, 1), 0); in t3_fatal_err()
1565 t3_write_reg(sc, A_ULPRX_TDDP_PSZ, V_HPZ0(PAGE_SHIFT - 12)); in cxgb_up()
1587 t3_write_reg(sc, A_TP_INT_CAUSE, F_CMCACHEPERR | F_ARPLUTPERR); in cxgb_up()
1588 t3_write_reg(sc, A_TP_INT_ENABLE, 0x7fbfffff); in cxgb_up()
2221 t3_write_reg(sc, A_PL_INT_ENABLE0, 0); in cxgb_async_intr()
2372 t3_write_reg(sc, A_SG_RSPQ_FL_STATUS, v); in cxgb_tick_handler()
2373 t3_write_reg(sc, A_SG_INT_CAUSE, cause); in cxgb_tick_handler()
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| H A D | cxgb_adapter.h | 435 t3_write_reg(adapter_t *adapter, uint32_t reg_addr, uint32_t val) in t3_write_reg() function
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