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/src/sys/dev/cpufreq/
H A Dichss.c61 struct cf_setting sets[2]; /* Only two settings. */ member
97 static int ichss_settings(device_t dev, struct cf_setting *sets,
272 sc->sets[0].freq = CPUFREQ_VAL_UNKNOWN; in ichss_attach()
273 sc->sets[0].volts = CPUFREQ_VAL_UNKNOWN; in ichss_attach()
274 sc->sets[0].power = CPUFREQ_VAL_UNKNOWN; in ichss_attach()
275 sc->sets[0].lat = 1000; in ichss_attach()
276 sc->sets[0].dev = dev; in ichss_attach()
277 sc->sets[1] = sc->sets[0]; in ichss_attach()
291 ichss_settings(device_t dev, struct cf_setting *sets, int *count) in ichss_settings() argument
297 if (sets == NULL || count == NULL) in ichss_settings()
[all …]
/src/sys/contrib/device-tree/src/arm64/amd/
H A Damd-seattle-cpus.dtsi51 i-cache-sets = <256>;
54 d-cache-sets = <256>;
67 i-cache-sets = <256>;
70 d-cache-sets = <256>;
82 i-cache-sets = <256>;
85 d-cache-sets = <256>;
97 i-cache-sets = <256>;
100 d-cache-sets = <256>;
112 i-cache-sets = <256>;
115 d-cache-sets = <256>;
[all …]
/src/sys/contrib/device-tree/src/arm64/amazon/
H A Dalpine-v3.dtsi30 d-cache-sets = <256>;
33 i-cache-sets = <256>;
44 d-cache-sets = <256>;
47 i-cache-sets = <256>;
58 d-cache-sets = <256>;
61 i-cache-sets = <256>;
72 d-cache-sets = <256>;
75 i-cache-sets = <256>;
86 d-cache-sets = <256>;
89 i-cache-sets = <256>;
[all …]
/src/sys/x86/cpufreq/
H A Dsmist.c73 struct cf_setting sets[2]; /* Only two settings. */ member
82 static int smist_settings(device_t dev, struct cf_setting *sets,
393 sc->sets[0].freq = CPUFREQ_VAL_UNKNOWN; in smist_attach()
394 sc->sets[0].volts = CPUFREQ_VAL_UNKNOWN; in smist_attach()
395 sc->sets[0].power = CPUFREQ_VAL_UNKNOWN; in smist_attach()
396 sc->sets[0].lat = 1000; in smist_attach()
397 sc->sets[0].dev = dev; in smist_attach()
398 sc->sets[1] = sc->sets[0]; in smist_attach()
413 smist_settings(device_t dev, struct cf_setting *sets, int *count) in smist_settings() argument
419 if (sets == NULL || count == NULL) in smist_settings()
[all …]
/src/sys/contrib/device-tree/src/riscv/sophgo/
H A Dsg2042-cpus.dtsi269 i-cache-sets = <512>;
272 d-cache-sets = <512>;
296 i-cache-sets = <512>;
299 d-cache-sets = <512>;
323 i-cache-sets = <512>;
326 d-cache-sets = <512>;
350 i-cache-sets = <512>;
353 d-cache-sets = <512>;
377 i-cache-sets = <512>;
380 d-cache-sets = <512>;
[all …]
H A Dsg2044-cpus.dtsi20 i-cache-sets = <512>;
23 d-cache-sets = <512>;
56 i-cache-sets = <512>;
59 d-cache-sets = <512>;
92 i-cache-sets = <512>;
95 d-cache-sets = <512>;
128 i-cache-sets = <512>;
131 d-cache-sets = <512>;
164 i-cache-sets = <512>;
167 d-cache-sets = <512>;
[all …]
/src/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-j784s4.dtsi65 i-cache-sets = <256>;
68 d-cache-sets = <256>;
79 i-cache-sets = <256>;
82 d-cache-sets = <256>;
93 i-cache-sets = <256>;
96 d-cache-sets = <256>;
107 i-cache-sets = <256>;
110 d-cache-sets = <256>;
121 i-cache-sets = <256>;
124 d-cache-sets = <256>;
[all …]
H A Dk3-am654.dtsi43 i-cache-sets = <256>;
46 d-cache-sets = <128>;
57 i-cache-sets = <256>;
60 d-cache-sets = <128>;
71 i-cache-sets = <256>;
74 d-cache-sets = <128>;
85 i-cache-sets = <256>;
88 d-cache-sets = <128>;
99 cache-sets = <512>;
109 cache-sets = <512>;
H A Dk3-j742s2.dtsi47 i-cache-sets = <256>;
50 d-cache-sets = <256>;
61 i-cache-sets = <256>;
64 d-cache-sets = <256>;
75 i-cache-sets = <256>;
78 d-cache-sets = <256>;
89 i-cache-sets = <256>;
92 d-cache-sets = <256>;
H A Dk3-am62a7.dtsi46 i-cache-sets = <256>;
49 d-cache-sets = <128>;
63 i-cache-sets = <256>;
66 d-cache-sets = <128>;
80 i-cache-sets = <256>;
83 d-cache-sets = <128>;
97 i-cache-sets = <256>;
100 d-cache-sets = <128>;
157 cache-sets = <512>;
/src/release/packages/
H A Dgenerate-ucl.lua182 sets = obj["annotations"]["set"] or "base"
192 sets = "lib32-dbg"
194 sets = "lib32"
201 sets = "devel"
204 elseif sets == "tests" then
205 sets = sets
211 for set in sets:gmatch("[^,]+") do
214 sets = table.concat(newsets, ",")
217 obj["annotations"]["set"] = sets
/src/sys/powerpc/cpufreq/
H A Ddfs.c46 static int dfs_settings(device_t dev, struct cf_setting *sets, int *count);
138 dfs_settings(device_t dev, struct cf_setting *sets, int *count) in dfs_settings() argument
145 if (sets == NULL || count == NULL) in dfs_settings()
151 memset(sets, CPUFREQ_VAL_UNKNOWN, sizeof(*sets) * states); in dfs_settings()
153 sets[0].freq = 10000; sets[0].dev = dev; in dfs_settings()
154 sets[1].freq = 5000; sets[1].dev = dev; in dfs_settings()
156 sets[2].freq = 2500; in dfs_settings()
157 sets[2].dev = dev; in dfs_settings()
H A Dpmufreq.c54 static int pmufreq_settings(device_t dev, struct cf_setting *sets, int *count);
145 pmufreq_settings(device_t dev, struct cf_setting *sets, int *count) in pmufreq_settings() argument
150 if (sets == NULL || count == NULL) in pmufreq_settings()
156 memset(sets, CPUFREQ_VAL_UNKNOWN, sizeof(*sets) * 2); in pmufreq_settings()
158 sets[0].freq = sc->maxfreq; sets[0].dev = dev; in pmufreq_settings()
159 sets[1].freq = sc->minfreq; sets[1].dev = dev; in pmufreq_settings()
161 sets[0].lat = INT_MAX; in pmufreq_settings()
162 sets[1].lat = INT_MAX; in pmufreq_settings()
H A Dpcr.c49 static int pcr_settings(device_t dev, struct cf_setting *sets, int *count);
234 pcr_settings(device_t dev, struct cf_setting *sets, int *count) in pcr_settings() argument
239 if (sets == NULL || count == NULL) in pcr_settings()
245 memset(sets, CPUFREQ_VAL_UNKNOWN, sizeof(*sets) * sc->nmodes); in pcr_settings()
247 sets[0].freq = 10000; sets[0].dev = dev; in pcr_settings()
248 sets[1].freq = 5000; sets[1].dev = dev; in pcr_settings()
250 sets[2].freq = 2500; in pcr_settings()
251 sets[2].dev = dev; in pcr_settings()
H A Dpmcr.c87 static int pmcr_settings(device_t dev, struct cf_setting *sets, int *count);
156 pmcr_settings(device_t dev, struct cf_setting *sets, int *count) in pmcr_settings() argument
160 if (sets == NULL || count == NULL) in pmcr_settings()
166 memset(sets, CPUFREQ_VAL_UNKNOWN, sizeof(*sets) * npstates); in pmcr_settings()
169 sets[i].freq = pstate_freqs[i]; in pmcr_settings()
170 sets[i].spec[0] = pstate_ids[i]; in pmcr_settings()
171 sets[i].spec[1] = i; in pmcr_settings()
172 sets[i].dev = dev; in pmcr_settings()
/src/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx943.dtsi38 i-cache-sets = <128>;
41 d-cache-sets = <128>;
56 i-cache-sets = <128>;
59 d-cache-sets = <128>;
74 i-cache-sets = <128>;
77 d-cache-sets = <128>;
92 i-cache-sets = <128>;
95 d-cache-sets = <128>;
103 cache-sets = <256>;
113 cache-sets = <256>;
[all …]
/src/sys/contrib/device-tree/src/arm64/marvell/
H A Darmada-ap806-quad.dtsi24 i-cache-sets = <256>;
27 d-cache-sets = <256>;
39 i-cache-sets = <256>;
42 d-cache-sets = <256>;
54 i-cache-sets = <256>;
57 d-cache-sets = <256>;
69 i-cache-sets = <256>;
72 d-cache-sets = <256>;
80 cache-sets = <512>;
89 cache-sets = <512>;
H A Darmada-ap807-quad.dtsi24 i-cache-sets = <256>;
27 d-cache-sets = <256>;
39 i-cache-sets = <256>;
42 d-cache-sets = <256>;
54 i-cache-sets = <256>;
57 d-cache-sets = <256>;
69 i-cache-sets = <256>;
72 d-cache-sets = <256>;
80 cache-sets = <512>;
89 cache-sets = <512>;
/src/sys/contrib/device-tree/src/arm64/arm/
H A Djuno-r1.dts95 i-cache-sets = <256>;
98 d-cache-sets = <256>;
112 i-cache-sets = <256>;
115 d-cache-sets = <256>;
129 i-cache-sets = <256>;
132 d-cache-sets = <128>;
146 i-cache-sets = <256>;
149 d-cache-sets = <128>;
163 i-cache-sets = <256>;
166 d-cache-sets = <128>;
[all …]
H A Djuno.dts94 i-cache-sets = <256>;
97 d-cache-sets = <256>;
112 i-cache-sets = <256>;
115 d-cache-sets = <256>;
130 i-cache-sets = <256>;
133 d-cache-sets = <128>;
148 i-cache-sets = <256>;
151 d-cache-sets = <128>;
166 i-cache-sets = <256>;
169 d-cache-sets = <128>;
[all …]
H A Djuno-r2.dts95 i-cache-sets = <256>;
98 d-cache-sets = <256>;
113 i-cache-sets = <256>;
116 d-cache-sets = <256>;
131 i-cache-sets = <256>;
134 d-cache-sets = <128>;
149 i-cache-sets = <256>;
152 d-cache-sets = <128>;
167 i-cache-sets = <256>;
170 d-cache-sets = <128>;
[all …]
/src/sys/contrib/device-tree/src/riscv/sifive/
H A Dfu540-c000.dtsi29 i-cache-sets = <128>;
46 d-cache-sets = <64>;
48 d-tlb-sets = <1>;
52 i-cache-sets = <64>;
54 i-tlb-sets = <1>;
73 d-cache-sets = <64>;
75 d-tlb-sets = <1>;
79 i-cache-sets = <64>;
81 i-tlb-sets = <1>;
100 d-cache-sets = <64>;
[all …]
/src/sys/contrib/device-tree/src/arm/broadcom/
H A Dbcm2836.dtsi43 /* Source for d/i-cache-line-size and d/i-cache-sets
58 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
61 i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
72 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
75 i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
86 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
89 i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
100 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
103 i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
107 /* Source for cache-line-size + cache-sets
[all …]
H A Dbcm2837.dtsi42 /* Source for d/i-cache-line-size and d/i-cache-sets
57 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
60 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
72 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
75 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
87 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
90 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
102 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
105 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
109 /* Source for cache-line-size + cache-sets
[all …]
/src/lib/libc/regex/
H A Dregfree.c68 if (g->sets != NULL) { in regfree()
70 free(g->sets[i].ranges); in regfree()
71 free(g->sets[i].wides); in regfree()
72 free(g->sets[i].types); in regfree()
74 free((char *)g->sets); in regfree()

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