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Searched refs:setRegClass (Results 1 – 25 of 41) sorted by relevance

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/src/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVBuiltins.cpp411 MIRBuilder.getMRI()->setRegClass(ResultRegister, &SPIRV::IDRegClass); in buildBoolRegister()
547 MRI->setRegClass(CLScopeRegister, &SPIRV::IDRegClass); in buildScopeReg()
567 MRI->setRegClass(SemanticsRegister, &SPIRV::IDRegClass); in buildMemSemanticsReg()
586 MRI->setRegClass(ArgReg, &SPIRV::IDRegClass);
602 MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass); in buildAtomicInitInst()
603 MIRBuilder.getMRI()->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass); in buildAtomicInitInst()
619 MIRBuilder.getMRI()->setRegClass(PtrRegister, &SPIRV::IDRegClass); in buildAtomicLoadInst()
626 MIRBuilder.getMRI()->setRegClass(ScopeRegister, &SPIRV::IDRegClass); in buildAtomicLoadInst()
634 MIRBuilder.getMRI()->setRegClass(MemSemanticsReg, &SPIRV::IDRegClass); in buildAtomicLoadInst()
661 MIRBuilder.getMRI()->setRegClass(PtrRegister, &SPIRV::IDRegClass); in buildAtomicStoreInst()
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H A DSPIRVPostLegalizer.cpp105 MRI.setRegClass(ResVReg, &SPIRV::IDRegClass); in processNewInstrs()
127 MRI.setRegClass(ResVReg, &SPIRV::IDRegClass); in processNewInstrs()
141 MRI.setRegClass(ResVReg, MRI.getType(ResVReg).isVector() in processNewInstrs()
H A DSPIRVPreLegalizer.cpp118 MRI.setRegClass(Reg, RC); in addConstantsToTrack()
290 MRI.setRegClass(Reg, &SPIRV::IDRegClass); in propagateSPIRVType()
361 MRI.setRegClass(IdReg, DstClass); in createNewIdReg()
382 MRI.setRegClass(NewReg, RC); in insertAssignInstr()
384 MRI.setRegClass(NewReg, &SPIRV::IDRegClass); in insertAssignInstr()
385 MRI.setRegClass(Reg, &SPIRV::IDRegClass); in insertAssignInstr()
599 MRI.setRegClass(DstReg, &SPIRV::IDRegClass); in processInstrsWithTypeFolding()
627 MRI.setRegClass(AsmTargetReg, &SPIRV::IDRegClass); in insertInlineAsmProcess()
647 MRI.setRegClass(AsmReg, &SPIRV::IDRegClass); in insertInlineAsmProcess()
690 MRI.setRegClass(DefReg, &SPIRV::IDRegClass); in insertInlineAsmProcess()
H A DSPIRVGlobalRegistry.cpp78 MRI.setRegClass(Res, &SPIRV::TYPERegClass); in createTypeVReg()
84 MRI.setRegClass(Res, &SPIRV::TYPERegClass); in createTypeVReg()
180 CurMF->getRegInfo().setRegClass(Res, &SPIRV::IDRegClass); in getOrCreateConstIntReg()
217 CurMF->getRegInfo().setRegClass(Res, &SPIRV::IDRegClass); in getOrCreateConstFloatReg()
314 MF.getRegInfo().setRegClass(Res, &SPIRV::IDRegClass); in buildConstantInt()
357 MF.getRegInfo().setRegClass(Res, &SPIRV::IDRegClass); in buildConstantFP()
414 CurMF->getRegInfo().setRegClass(SpvVecConst, &SPIRV::IDRegClass); in getOrCreateCompositeOrNull()
516 CurMF->getRegInfo().setRegClass(SpvVecConst, &SPIRV::IDRegClass); in getOrCreateIntCompositeOrNull()
568 CurMF->getRegInfo().setRegClass(Res, &SPIRV::IDRegClass); in getOrCreateConstNullPtr()
1442 CurMF->getRegInfo().setRegClass(Res, &SPIRV::IDRegClass); in getOrCreateUndef()
H A DSPIRVCallLowering.cpp375 MRI->setRegClass(FuncVReg, &SPIRV::IDRegClass); in lowerFormalArguments()
406 MRI->setRegClass(VRegs[i][0], &SPIRV::IDRegClass); in lowerFormalArguments()
561 MRI->setRegClass(Reg, &SPIRV::IDRegClass); in lowerCall()
H A DSPIRVISelLowering.cpp128 MRI->setRegClass(NewReg, &SPIRV::IDRegClass); in doInsertBitcast()
/src/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUGlobalISelDivergenceLowering.cpp98 MRI->setRegClass(DstReg, ST->getBoolRC()); in markAsLaneMask()
187 MRI->setRegClass(Copy.getReg(0), ST->getBoolRC()); in constrainAsLaneMask()
H A DSIFixSGPRCopies.cpp247 MRI.setRegClass(DstReg, TRI->getEquivalentSGPRClass(MRI.getRegClass(DstReg))); in tryChangeVGPRtoSGPRinCopy()
299 MRI.setRegClass(DstReg, DstRC); in foldVGPRCopyIntoRegSequence()
821 MRI->setRegClass(PHIRes, TRI->getEquivalentAGPRClass(RC0)); in processPHINode()
H A DAMDGPURegisterBankInfo.cpp941 MRI.setRegClass(CondReg, WaveRC); in executeInWaterfallLoop()
2569 MRI.setRegClass(DstReg, &AMDGPU::SGPR_64RegClass); in applyMappingImpl()
2570 MRI.setRegClass(SrcReg0, &AMDGPU::SGPR_64RegClass); in applyMappingImpl()
2571 MRI.setRegClass(SrcReg1, &AMDGPU::SGPR_64RegClass); in applyMappingImpl()
2584 MRI.setRegClass(Op0L, &AMDGPU::VGPR_32RegClass); in applyMappingImpl()
2590 MRI.setRegClass(Op1L, &AMDGPU::VGPR_32RegClass); in applyMappingImpl()
2600 MRI.setRegClass(Zero64, &AMDGPU::VReg_64RegClass); in applyMappingImpl()
2602 MRI.setRegClass(CarryOut, &AMDGPU::VReg_64RegClass); in applyMappingImpl()
H A DSIFoldOperands.cpp2064 MRI->setRegClass(DefReg, TRI->getEquivalentAGPRClass(RC)); in tryFoldLoad()
2066 MRI->setRegClass(DefReg, RC); in tryFoldLoad()
2072 MRI->setRegClass(Reg, TRI->getEquivalentAGPRClass(MRI->getRegClass(Reg))); in tryFoldLoad()
H A DSILowerI1Copies.cpp813 MRI->setRegClass(DstReg, ST->getBoolRC()); in markAsLaneMask()
H A DAMDGPULegalizerInfo.cpp2217 MRI.setRegClass(Dst, &AMDGPU::SReg_64RegClass); in getSegmentAperture()
2887 B.getMRI()->setRegClass(PCReg, &AMDGPU::SReg_64RegClass); in buildPCRelGlobalAddress()
2909 MRI.setRegClass(AddrLo, &AMDGPU::SReg_32RegClass); in buildAbsGlobalAddress()
2922 MRI.setRegClass(AddrHi, &AMDGPU::SReg_32RegClass); in buildAbsGlobalAddress()
2935 MRI.setRegClass(AddrDst, &AMDGPU::SReg_64RegClass); in buildAbsGlobalAddress()
7221 MRI.setRegClass(Def, TRI->getWaveMaskRegClass()); in legalizeIntrinsic()
7222 MRI.setRegClass(Use, TRI->getWaveMaskRegClass()); in legalizeIntrinsic()
7257 MRI.setRegClass(Reg, TRI->getWaveMaskRegClass()); in legalizeIntrinsic()
/src/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineRegisterInfo.cpp59 MachineRegisterInfo::setRegClass(Register Reg, const TargetRegisterClass *RC) { in setRegClass() function in MachineRegisterInfo
81 MRI.setRegClass(Reg, NewRC); in constrainRegClass()
143 setRegClass(Reg, NewRC); in recomputeRegClass()
H A DRegisterBankInfo.cpp148 MRI.setRegClass(Reg, &RC); in constrainGenericRegister()
H A DTailDuplicator.cpp434 MRI->setRegClass(VI->second.Reg, ConstrRC); in duplicateInstruction()
/src/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DInlineAsmLowering.cpp364 Flag.setRegClass(RC->getID()); in lowerInlineAsm()
515 Flag.setRegClass(RC->getID()); in lowerInlineAsm()
H A DInstructionSelect.cpp180 MRI.setRegClass(SrcReg, DstRC); in runOnMachineFunction()
/src/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp411 MRI.setRegClass(Addr.Base.Reg, &PPC::G8RC_and_G8RC_NOX0RegClass); in PPCComputeAddress()
1314 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass); in SelectBinaryIntOp()
1318 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass); in SelectBinaryIntOp()
1331 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass); in SelectBinaryIntOp()
1340 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass); in SelectBinaryIntOp()
2429 MRI.setRegClass(Op0, &PPC::GPRC_and_GPRC_NOR0RegClass); in fastEmitInst_ri()
2431 MRI.setRegClass(Op0, &PPC::G8RC_and_G8RC_NOX0RegClass); in fastEmitInst_ri()
/src/contrib/llvm-project/llvm/include/llvm/IR/
H A DInlineAsm.h400 void setRegClass(unsigned RC) { in setRegClass() function
/src/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp1504 MRI.setRegClass(Reg, &SystemZ::FP32BitRegClass); in foldMemoryOperandImpl()
1506 MRI.setRegClass(Reg, &SystemZ::FP64BitRegClass); in foldMemoryOperandImpl()
1508 MRI.setRegClass(Reg, &SystemZ::VF128BitRegClass); in foldMemoryOperandImpl()
1596 MRI->setRegClass(DstReg, FPRC); in foldMemoryOperandImpl()
1597 MRI->setRegClass(RegMO.getReg(), FPRC); in foldMemoryOperandImpl()
/src/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp305 Flag.setRegClass(SP::IntPairRegClassID); in tryInlineAsm()
/src/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelDAGToDAG.cpp261 Flag.setRegClass(CSKY::GPRPairRegClassID); in selectInlineAsm()
/src/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64LegalizerInfo.cpp1479 MRI.setRegClass(ADRP.getReg(0), &AArch64::GPR64RegClass); in legalizeSmallCMGlobalValue()
1501 MRI.setRegClass(ADRP.getReg(0), &AArch64::GPR64RegClass); in legalizeSmallCMGlobalValue()
2182 MRI.setRegClass(NewMI.getReg(0), &AArch64::GPR64commonRegClass); in legalizeDynStackAlloc()
/src/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineRegisterInfo.h692 void setRegClass(Register Reg, const TargetRegisterClass *RC);
/src/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86DomainReassignment.cpp507 MRI->setRegClass(Reg, getDstRC(MRI->getRegClass(Reg), Domain)); in reassign()

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