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Searched refs:sdst (Results 1 – 25 of 25) sorted by relevance

/src/contrib/tcsh/
H A Dtc.str.c168 Char **sdst, **dst; local
175 sdst = dst = xmalloc((n + 1) * sizeof(Char *));
180 return (sdst);
187 char **sdst, **dst; local
194 sdst = dst = xmalloc((n + 1) * sizeof(char *));
199 return (sdst);
224 static char *sdst = NULL; local
231 if (sdst == NULL) {
233 sdst = xmalloc((dstsize + MALLOC_SURPLUS) * sizeof(char));
235 dst = sdst;
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/src/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSOPInstructions.td72 bits<7> sdst;
77 let Inst{22-16} = !if(ps.has_sdst, sdst, ?);
82 opName, (outs SReg_32:$sdst),
85 "$sdst, $src0", pattern> {
86 let Constraints = !if(tied_in, "$sdst = $sdst_in", "");
91 opName, (outs SReg_32:$sdst), (ins SReg_32:$src0),
92 "$sdst, $src0", pattern>;
101 // Special case for movreld where sdst is treated as a use operand.
103 opName, (outs), (ins SReg_32:$sdst, SSrc_b32:$src0),
104 "$sdst, $src0", pattern>;
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H A DSMInstructions.td83 bits<7> sdst;
123 : SM_Pseudo<opName, (outs dstClass:$sdst),
125 " $sdst, $sbase, " # offsets.Asm # "$cpol", []> {
173 let Constraints = "@earlyclobber $sdst",
201 opName, (outs SReg_64_XEXEC:$sdst), (ins),
202 " $sdst", [(set i64:$sdst, (node))]> {
228 opName, (outs SReg_32_XM0_XEXEC:$sdst), (ins),
229 " $sdst", [(set i32:$sdst, (node))]> {
284 !if(isRet, (outs dataClass:$sdst), (outs)),
287 !if(isRet, " $sdst", " $sdata") #
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H A DVOPCInstructions.td78 let Outs64 = (outs VOPDstS64orS32:$sdst);
190 // This class is used only with VOPC instructions. Use $sdst for out operand
203 (inst p.DstRC:$sdst),
206 (inst p.DstRC:$sdst, p.Src0RC32:$src0),
209 (inst p.DstRC:$sdst, p.Src0RC32:$src0, p.Src1RC32:$src1),
257 [(set i1:$sdst,
264 [(set i1:$sdst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]);
782 let AsmVOP3Base = "$sdst, $src0_modifiers, $src1";
838 [(set i1:$sdst,
1285 bits<8> sdst;
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H A DSIPeepholeSDWA.cpp911 const MachineOperand *Sdst = TII->getNamedOperand(MI, AMDGPU::OpName::sdst); in pseudoOpConvertToVOP2()
923 MachineOperand *CarryOut = TII->getNamedOperand(MISucc, AMDGPU::OpName::sdst); in pseudoOpConvertToVOP2()
975 const MachineOperand *SDst = TII->getNamedOperand(MI, AMDGPU::OpName::sdst); in isConvertibleToSDWA()
986 } else if (TII->getNamedOperand(MI, AMDGPU::OpName::sdst) || in isConvertibleToSDWA()
1048 } else if ((Dst = TII->getNamedOperand(MI, AMDGPU::OpName::sdst))) { in convertToSDWA()
1049 assert(Dst && AMDGPU::hasNamedOperand(SDWAOpcode, AMDGPU::OpName::sdst)); in convertToSDWA()
1052 assert(AMDGPU::hasNamedOperand(SDWAOpcode, AMDGPU::OpName::sdst)); in convertToSDWA()
H A DSIInstructions.td149 def S_MOV_B64_IMM_PSEUDO : SPseudoInstSI <(outs SReg_64:$sdst),
186 def ENTER_STRICT_WWM : SPseudoInstSI <(outs SReg_1:$sdst), (ins i64imm:$src0)> {
194 def EXIT_STRICT_WWM : SPseudoInstSI <(outs SReg_1:$sdst), (ins SReg_1:$src0)> {
200 def ENTER_STRICT_WQM : SPseudoInstSI <(outs SReg_1:$sdst), (ins i64imm:$src0)> {
208 def EXIT_STRICT_WQM : SPseudoInstSI <(outs SReg_1:$sdst), (ins SReg_1:$src0)> {
217 (outs SReg_32:$sdst), (ins SSrc_b32:$mask),
218 [(set i1:$sdst, (int_amdgcn_inverse_ballot i32:$mask))]
223 (outs SReg_64:$sdst), (ins SSrc_b64:$mask),
224 [(set i1:$sdst, (int_amdgcn_inverse_ballot i64:$mask))]
271 def WAVE_REDUCE_UMIN_PSEUDO_U32 : VPseudoInstSI <(outs SGPR_32:$sdst),
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H A DVOPInstructions.td362 bits<7> sdst;
366 let Inst{14-8} = sdst;
583 bits<8> sdst; // {vcc_sdst{0}, sdst{6-0}}
585 let Inst{46-40} = !if(P.EmitDst, sdst{6-0}, ?);
586 let Inst{47} = !if(P.EmitDst, sdst{7}, 0);
1377 bits<7> sdst;
1378 let Inst{14 - 8} = sdst;
1383 bits<7> sdst;
1384 let Inst{14 - 8} = sdst;
H A DGCNDPPCombine.cpp130 if (const auto *SDst = TII->getNamedOperand(MI, AMDGPU::OpName::sdst)) { in isShrinkable()
246 if (auto *SDst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::sdst)) { in createDPPInst()
H A DSIInstrInfo.td1974 (outs DstRCSDWA:$sdst),
1982 string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC
2053 "$sdst",
2055 ""); // use $sdst for VOPC
2082 "$sdst",
2084 ""); // use $sdst for VOPC
2158 "$sdst", // VOPC
2839 // Maps a v_cmpx opcode with sdst to opcode without sdst.
H A DSIShrinkInstructions.cpp779 MachineOperand *Op = TII->getNamedOperand(MI, AMDGPU::OpName::sdst); in tryReplaceDeadSDST()
992 AMDGPU::OpName::sdst); in runOnMachineFunction()
H A DSIOptimizeExecMasking.cpp677 MachineOperand *VCmpDest = TII->getNamedOperand(*VCmp, AMDGPU::OpName::sdst); in tryRecordVCmpxAndSaveexecSequence()
H A DVOP3Instructions.td25 let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst);
26 let Asm64 = "$vdst, $sdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$omod";
39 let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst);
40 let Asm64 = "$vdst, $sdst, $src0, $src1, $src2$clamp";
H A DGCNHazardRecognizer.cpp1209 SDSTName = AMDGPU::OpName::sdst; in fixSMEMtoVectorWriteHazards()
1302 if (TII->getNamedOperand(MI, AMDGPU::OpName::sdst)) in fixVcmpxExecWARHazard()
2780 const MachineOperand *SDSTOp = TII.getNamedOperand(*MI, AMDGPU::OpName::sdst); in fixVALUMaskWriteHazard()
H A DVOP2Instructions.td352 (inst ps.Pfl.DstRC:$vdst, VOPDstS64orS32:$sdst,
545 let AsmVOP3Base = "$vdst, $sdst, $src0, $src1$clamp";
562 let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst);
578 let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst);
579 let AsmVOP3Base = "$vdst, $sdst, $src0, $src1, $src2$clamp";
H A DSILoadStoreOptimizer.cpp1154 if (const auto *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::sdst)) { in getDataRegClass()
1491 copyToDestRegs(CI, Paired, InsertBefore, AMDGPU::OpName::sdst, DestReg); in mergeSMemLoadImmPair()
H A DAMDGPU.td477 def FeatureSDWASdst : SubtargetFeature<"sdwa-sdst",
839 def FeatureNoSdstCMPX : SubtargetFeature<"no-sdst-cmpx",
H A DSIInstrInfo.cpp489 DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::sdst); in getMemOperandsWithOffsetWidth()
/src/crypto/openssl/providers/implementations/macs/
H A Dsiphash_prov.c76 struct siphash_data_st *sdst; in siphash_dup() local
80 sdst = OPENSSL_malloc(sizeof(*sdst)); in siphash_dup()
81 if (sdst == NULL) in siphash_dup()
84 *sdst = *ssrc; in siphash_dup()
85 return sdst; in siphash_dup()
/src/sys/netinet6/
H A Dicmp6.c2324 struct sockaddr_in6 sdst; in icmp6_redirect_input() local
2331 bzero(&sdst, sizeof(sdst)); in icmp6_redirect_input()
2333 sdst.sin6_family = ssrc.sin6_family = AF_INET6; in icmp6_redirect_input()
2334 sdst.sin6_len = ssrc.sin6_len = sizeof(struct sockaddr_in6); in icmp6_redirect_input()
2335 bcopy(&reddst6, &sdst.sin6_addr, sizeof(struct in6_addr)); in icmp6_redirect_input()
2349 rib_add_redirect(fibnum, (struct sockaddr *)&sdst, gw, in icmp6_redirect_input()
/src/crypto/heimdal/lib/roken/
H A Dglob.c810 Char *sdst = dst; in g_strcat() local
818 return (sdst); in g_strcat()
/src/usr.sbin/route6d/
H A Droute6d.c1951 rt_del(const struct sockaddr_in6 *sdst, in rt_del() argument
1962 if (sdst->sin6_family != AF_INET6) { in rt_del()
1966 if (IN6_IS_ADDR_LINKLOCAL(&sdst->sin6_addr) in rt_del()
1967 || IN6_ARE_ADDR_EQUAL(&sdst->sin6_addr, &in6addr_loopback) in rt_del()
1968 || IN6_IS_ADDR_MULTICAST(&sdst->sin6_addr)) { in rt_del()
1970 inet6_n2p(&sdst->sin6_addr)); in rt_del()
1973 dst = &sdst->sin6_addr; in rt_del()
1991 &sdst->sin6_addr) in rt_del()
/src/sys/cam/scsi/
H A Dscsi_ch.h83 uint8_t sdst[2]; /* second destination address */ member
H A Dscsi_ch.c1772 scsi_ulto2b(dst2, scsi_cmd->sdst); in scsi_exchange_medium()
/src/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp778 if (AMDGPU::hasNamedOperand(MI.getOpcode(), AMDGPU::OpName::sdst)) in convertSDWAInst()
782 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); in convertSDWAInst()
786 AMDGPU::OpName::sdst); in convertSDWAInst()
/src/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp4841 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::sdst); in validateWaitCnt()