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Searched refs:reo_base (Results 1 – 3 of 3) sorted by relevance

/src/sys/contrib/dev/athk/ath11k/
H A Dhw.c107 u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG; in ath11k_hw_ipq8074_reo_setup() local
119 val = ath11k_hif_read32(ab, reo_base + HAL_REO1_GEN_ENABLE); in ath11k_hw_ipq8074_reo_setup()
126 ath11k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val); in ath11k_hw_ipq8074_reo_setup()
128 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(ab), in ath11k_hw_ipq8074_reo_setup()
130 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(ab), in ath11k_hw_ipq8074_reo_setup()
132 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(ab), in ath11k_hw_ipq8074_reo_setup()
134 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(ab), in ath11k_hw_ipq8074_reo_setup()
137 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_0, in ath11k_hw_ipq8074_reo_setup()
140 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_1, in ath11k_hw_ipq8074_reo_setup()
143 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2, in ath11k_hw_ipq8074_reo_setup()
[all …]
/src/sys/contrib/dev/athk/ath12k/
H A Dhal_rx.c898 u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG; in ath12k_hal_reo_hw_setup() local
901 val = ath12k_hif_read32(ab, reo_base + HAL_REO1_GEN_ENABLE); in ath12k_hal_reo_hw_setup()
905 ath12k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val); in ath12k_hal_reo_hw_setup()
907 val = ath12k_hif_read32(ab, reo_base + HAL_REO1_MISC_CTRL_ADDR(ab)); in ath12k_hal_reo_hw_setup()
915 ath12k_hif_write32(ab, reo_base + HAL_REO1_MISC_CTRL_ADDR(ab), val); in ath12k_hal_reo_hw_setup()
917 ath12k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(ab), in ath12k_hal_reo_hw_setup()
919 ath12k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(ab), in ath12k_hal_reo_hw_setup()
921 ath12k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(ab), in ath12k_hal_reo_hw_setup()
923 ath12k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(ab), in ath12k_hal_reo_hw_setup()
926 ath12k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2, in ath12k_hal_reo_hw_setup()
[all …]
H A Ddp.c1343 u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG; in ath12k_dp_cc_config() local
1350 ath12k_hif_write32(ab, reo_base + HAL_REO1_SW_COOKIE_CFG0(ab), cmem_base); in ath12k_dp_cc_config()
1362 ath12k_hif_write32(ab, reo_base + HAL_REO1_SW_COOKIE_CFG1(ab), val); in ath12k_dp_cc_config()