| /src/sys/dev/aic7xxx/ |
| H A D | aic79xx_reg_print.c | 17 ahd_mode_ptr_print(u_int regvalue, u_int *cur_col, u_int wrap) in ahd_mode_ptr_print() argument
20 0x00, regvalue, cur_col, wrap)); in ahd_mode_ptr_print()
36 ahd_intstat_print(u_int regvalue, u_int *cur_col, u_int wrap) in ahd_intstat_print() argument
39 0x01, regvalue, cur_col, wrap)); in ahd_intstat_print()
73 ahd_seqintcode_print(u_int regvalue, u_int *cur_col, u_int wrap) in ahd_seqintcode_print() argument
76 0x02, regvalue, cur_col, wrap)); in ahd_seqintcode_print()
91 ahd_clrint_print(u_int regvalue, u_int *cur_col, u_int wrap) in ahd_clrint_print() argument
94 0x03, regvalue, cur_col, wrap)); in ahd_clrint_print()
108 ahd_error_print(u_int regvalue, u_int *cur_col, u_int wrap) in ahd_error_print() argument
111 0x04, regvalue, cur_col, wrap)); in ahd_error_print()
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| H A D | aic7xxx_reg_print.c | 23 ahc_scsiseq_print(u_int regvalue, u_int *cur_col, u_int wrap) in ahc_scsiseq_print() argument
26 0x00, regvalue, cur_col, wrap)); in ahc_scsiseq_print()
40 ahc_sxfrctl0_print(u_int regvalue, u_int *cur_col, u_int wrap) in ahc_sxfrctl0_print() argument
43 0x01, regvalue, cur_col, wrap)); in ahc_sxfrctl0_print()
57 ahc_sxfrctl1_print(u_int regvalue, u_int *cur_col, u_int wrap) in ahc_sxfrctl1_print() argument
60 0x02, regvalue, cur_col, wrap)); in ahc_sxfrctl1_print()
84 ahc_scsisigi_print(u_int regvalue, u_int *cur_col, u_int wrap) in ahc_scsisigi_print() argument
87 0x03, regvalue, cur_col, wrap)); in ahc_scsisigi_print()
109 ahc_scsisigo_print(u_int regvalue, u_int *cur_col, u_int wrap) in ahc_scsisigo_print() argument
112 0x03, regvalue, cur_col, wrap)); in ahc_scsisigo_print()
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| H A D | aic79xx_reg.h | 18 #define ahd_mode_ptr_print(regvalue, cur_col, wrap) \ argument
19 ahd_print_register(NULL, 0, "MODE_PTR", 0x00, regvalue, cur_col, wrap)
25 #define ahd_intstat_print(regvalue, cur_col, wrap) \ argument
26 ahd_print_register(NULL, 0, "INTSTAT", 0x01, regvalue, cur_col, wrap)
32 #define ahd_seqintcode_print(regvalue, cur_col, wrap) \ argument
33 ahd_print_register(NULL, 0, "SEQINTCODE", 0x02, regvalue, cur_col, wrap)
39 #define ahd_clrint_print(regvalue, cur_col, wrap) \ argument
40 ahd_print_register(NULL, 0, "CLRINT", 0x03, regvalue, cur_col, wrap)
46 #define ahd_error_print(regvalue, cur_col, wrap) \ argument
47 ahd_print_register(NULL, 0, "ERROR", 0x04, regvalue, cur_col, wrap)
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| H A D | aic7xxx_reg.h | 18 #define ahc_scsiseq_print(regvalue, cur_col, wrap) \ argument
19 ahc_print_register(NULL, 0, "SCSISEQ", 0x00, regvalue, cur_col, wrap)
25 #define ahc_sxfrctl0_print(regvalue, cur_col, wrap) \ argument
26 ahc_print_register(NULL, 0, "SXFRCTL0", 0x01, regvalue, cur_col, wrap)
32 #define ahc_sxfrctl1_print(regvalue, cur_col, wrap) \ argument
33 ahc_print_register(NULL, 0, "SXFRCTL1", 0x02, regvalue, cur_col, wrap)
39 #define ahc_scsisigi_print(regvalue, cur_col, wrap) \ argument
40 ahc_print_register(NULL, 0, "SCSISIGI", 0x03, regvalue, cur_col, wrap)
46 #define ahc_scsisigo_print(regvalue, cur_col, wrap) \ argument
47 ahc_print_register(NULL, 0, "SCSISIGO", 0x03, regvalue, cur_col, wrap)
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| /src/lib/libproc/ |
| H A D | proc_regs.c | 42 proc_regget(struct proc_handle *phdl, proc_reg_t reg, unsigned long *regvalue) in proc_regget() argument
57 *regvalue = regs.elr; in proc_regget()
59 *regvalue = regs.r_rip; in proc_regget()
61 *regvalue = regs.r_pc; in proc_regget()
63 *regvalue = regs.r_eip; in proc_regget()
65 *regvalue = regs.pc; in proc_regget()
67 *regvalue = regs.sepc; in proc_regget()
72 *regvalue = regs.sp; in proc_regget()
74 *regvalue = regs.r_rsp; in proc_regget()
76 *regvalue = regs.r_sp; in proc_regget()
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| /src/sys/dev/clk/starfive/ |
| H A D | jh7110_clk.c | 61 uint32_t regvalue, offset, bitmask = 1UL << id % 32; in jh7110_reset_assert() local
68 regvalue = READ4(sc, offset); in jh7110_reset_assert()
71 regvalue |= bitmask; in jh7110_reset_assert()
73 regvalue &= ~bitmask; in jh7110_reset_assert()
74 WRITE4(sc, offset, regvalue); in jh7110_reset_assert()
85 uint32_t regvalue, offset, bitmask; in jh7110_reset_is_asserted() local
92 regvalue = READ4(sc, offset); in jh7110_reset_is_asserted()
97 *reset = (regvalue & bitmask) == 0; in jh7110_reset_is_asserted()
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| /src/contrib/ntp/ntpd/ |
| H A D | refclock_bancomm.c | 254 int regvalue; variable
326 regvalue = 0; /* More esoteric stuff to do... */ in vme_start()
327 if( ioctl( fd_vme, WCR0, ®value ) ) in vme_start()
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| /src/sys/dev/e1000/ |
| H A D | e1000_mac.c | 2169 u32 i, regvalue = 0; in e1000_write_8bit_ctrl_reg_generic() local
2174 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT); in e1000_write_8bit_ctrl_reg_generic()
2175 E1000_WRITE_REG(hw, reg, regvalue); in e1000_write_8bit_ctrl_reg_generic()
2180 regvalue = E1000_READ_REG(hw, reg); in e1000_write_8bit_ctrl_reg_generic()
2181 if (regvalue & E1000_GEN_CTL_READY) in e1000_write_8bit_ctrl_reg_generic()
2184 if (!(regvalue & E1000_GEN_CTL_READY)) { in e1000_write_8bit_ctrl_reg_generic()
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