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/src/sys/contrib/device-tree/Bindings/mfd/
H A Dmc13xxx.txt16 - leds : Contain the led nodes and initial register values in property
17 "led-control". Number of register depends of used IC, for MC13783 is 6,
55 sw1a : regulator SW1A (register 24, bit 0)
56 sw1b : regulator SW1B (register 25, bit 0)
57 sw2a : regulator SW2A (register 26, bit 0)
58 sw2b : regulator SW2B (register 27, bit 0)
59 sw3 : regulator SW3 (register 29, bit 20)
60 vaudio : regulator VAUDIO (register 32, bit 0)
61 viohi : regulator VIOHI (register 32, bit 3)
62 violo : regulator VIOLO (register 32, bit 6)
[all …]
/src/contrib/llvm-project/compiler-rt/lib/sanitizer_common/
H A Dsanitizer_syscall_linux_loongarch64.inc14 // About local register variables:
31 register u64 a7 asm("$a7") = nr;
32 register u64 a0 asm("$a0");
42 register u64 a7 asm("$a7") = nr;
43 register u64 a0 asm("$a0") = arg1;
53 register u64 a7 asm("$a7") = nr;
54 register u64 a0 asm("$a0") = arg1;
55 register u64 a1 asm("$a1") = arg2;
66 register u64 a7 asm("$a7") = nr;
67 register u64 a0 asm("$a0") = arg1;
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H A Dsanitizer_syscall_linux_arm.inc16 register u32 r8 asm("r7") = nr;
17 register u32 r0 asm("r0");
28 register u32 r8 asm("r7") = nr;
29 register u32 r0 asm("r0") = arg1;
40 register u32 r8 asm("r7") = nr;
41 register u32 r0 asm("r0") = arg1;
42 register u32 r1 asm("r1") = arg2;
53 register u32 r8 asm("r7") = nr;
54 register u32 r0 asm("r0") = arg1;
55 register u32 r1 asm("r1") = arg2;
[all …]
H A Dsanitizer_syscall_linux_hexagon.inc37 register u32 r6 __asm__("r6") = n;
38 register u32 r0 __asm__("r0");
45 register u32 r6 __asm__("r6") = n;
46 register u32 r0 __asm__("r0") = a;
54 register u32 r6 __asm__("r6") = n;
55 register u32 r0 __asm__("r0") = a;
56 register u32 r1 __asm__("r1") = b;
64 register u32 r6 __asm__("r6") = n;
65 register u32 r0 __asm__("r0") = a;
66 register u32 r1 __asm__("r1") = b;
[all …]
H A Dsanitizer_syscall_linux_aarch64.inc16 register u64 x8 asm("x8") = nr;
17 register u64 x0 asm("x0");
28 register u64 x8 asm("x8") = nr;
29 register u64 x0 asm("x0") = arg1;
40 register u64 x8 asm("x8") = nr;
41 register u64 x0 asm("x0") = arg1;
42 register u64 x1 asm("x1") = arg2;
53 register u64 x8 asm("x8") = nr;
54 register u64 x0 asm("x0") = arg1;
55 register u64 x1 asm("x1") = arg2;
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H A Dsanitizer_syscall_linux_riscv64.inc13 // About local register variables:
34 register u64 a7 asm("a7") = nr;
35 register u64 a0 asm("a0");
45 register u64 a7 asm("a7") = nr;
46 register u64 a0 asm("a0") = arg1;
56 register u64 a7 asm("a7") = nr;
57 register u64 a0 asm("a0") = arg1;
58 register u64 a1 asm("a1") = arg2;
69 register u64 a7 asm("a7") = nr;
70 register u64 a0 asm("a0") = arg1;
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/src/sys/dev/aic7xxx/
H A Daic79xx.reg2 * Aic79xx register and scratch ram definitions.
83 * as the source and destination of any register accesses in our
84 * register window.
86 register MODE_PTR {
100 register INTSTAT {
117 register SEQINTCODE {
196 register CLRINT {
212 register ERROR {
227 register CLRERR {
243 register HCNTRL {
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H A Daic7xxx.reg2 * Aic7xxx register and scratch ram definitions.
55 register SCSISEQ {
72 register SXFRCTL0 {
88 register SXFRCTL1 {
104 register SCSISIGI {
131 * Writing to this register modifies the control signals on the bus. Only
135 register SCSISIGO {
160 * Contents of this register determine the Synchronous SCSI data transfer
165 register SCSIRATE {
181 register SCSIID {
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/src/sys/contrib/device-tree/Bindings/leds/
H A Dregister-bit-led.txt4 where single bits in a certain register can turn on/off a
5 single LED. The register bit LEDs appear as children to the
16 - compatible : must be "register-bit-led"
17 - offset : register offset to the register controlling this LED
18 - mask : bit mask for the bit controlling this LED in the register
36 compatible = "register-bit-led";
44 compatible = "register-bit-led";
52 compatible = "register-bit-led";
60 compatible = "register-bit-led";
67 compatible = "register-bit-led";
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/src/sys/dev/mdio/
H A Dmdio_if.m29 * @brief Read register from device on MDIO bus.
33 * @param reg The PHY register offset.
42 * @brief Read register from device on MDIO muxed bus.
47 * @param reg The PHY register offset.
57 * @brief Write register to device on MDIO bus.
61 * @param reg The PHY register offset.
72 * @brief Write register to device on MDIO muxed bus.
77 * @param reg The PHY register offset.
90 * @brief Read extended register from device on MDIO bus.
95 * MDIO_DEVADDR_NONE to request Clause 22 register addressing.
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/src/sys/contrib/device-tree/src/mips/mti/
H A Dsead3.dts114 compatible = "register-bit-led";
120 compatible = "register-bit-led";
126 compatible = "register-bit-led";
132 compatible = "register-bit-led";
138 compatible = "register-bit-led";
144 compatible = "register-bit-led";
150 compatible = "register-bit-led";
156 compatible = "register-bit-led";
163 compatible = "register-bit-led";
169 compatible = "register-bit-led";
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/src/sys/contrib/device-tree/Bindings/pinctrl/
H A Dpinctrl-single.txt1 One-register-per-pin type device tree based pinctrl driver
8 - reg : offset and length of the register set for the mux registers
13 - pinctrl-single,register-width : pinmux register access width in bits
16 in the pinmux register
23 - pinctrl-single,bit-per-mux : boolean to indicate that one register controls
28 drive strength in the pinmux register. They're value of drive strength
35 input bias pullup in the pinmux register.
41 input bias pulldown in the pinmux register.
57 input schmitt in the pinmux register. In some silicons, there're two input
58 schmitt value (rising-edge & falling-edge) in the pinmux register.
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/src/sys/contrib/device-tree/Bindings/reset/
H A Dti-syscon-reset.txt7 sometimes a part of a larger register space region implementing various
8 functionalities. This register range is best represented as a syscon node to
10 register space.
30 - ti,reset-bits : Contains the reset control register information
34 register from the syscon register base
36 assert control register
38 register from the syscon register base
40 deassert control register
41 Cell #5 : offset of the reset status register
42 from the syscon register base
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/src/sys/contrib/device-tree/Bindings/c6x/
H A Ddscr.txt9 more configuration registers often protected by a lock register where one or
10 more key values must be written to a lock register in order to unlock the
11 configuration register for writes. These configuration register may be used to
13 sources (internal or pin), etc. In some cases, a configuration register is
25 - reg: register area base and size
35 offset of the devstat register
46 a lock register. Each tuple consists of the register offset, lock register
47 offsset, and the key value used to unlock the register.
52 written to the first kick register and the second key must be written to
53 the second register before other registers in the area are write-enabled.
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/src/sys/contrib/device-tree/Bindings/clock/ti/
H A Dmux.txt4 register-mapped multiplexer with multiple input clock signals or
9 as they are programmed into the register. E.g:
13 results in programming the register as follows:
15 register value selected parent clock
21 into the register, instead indexing begins at 1. The optional property
24 register value selected clock parent
29 The binding must provide the register to control the mux. Optionally
30 the number of bits to shift the control field in the register can be
40 - reg : register offset for register controlling adjustable mux
50 - ti,latch-bit : latch the mux value to HW, only needed if the register
/src/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleA8.td123 // Scaled register offset, issues over 2 cycles
144 // Scaled register offset with update, issues over 2 cycles
202 // Scaled register offset, issues over 2 cycles
222 // Scaled register offset with update, issues over 2 cycles
774 // Double-register FP Unary
778 // Quad-register FP Unary
784 // Double-register FP Binary
792 // Double-register FP VMUL
797 // Quad-register FP Binary
803 // Quad-register FP VMUL
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/src/sys/contrib/device-tree/Bindings/phy/
H A Dti-phy.txt7 "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.
8 "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register
15 "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on
17 "ti,control-phy-usb2-am437" - if it has power down register like USB2 PHY on
19 - reg : register ranges as listed in the reg-names property
35 - reg : Address and length of the register set for the device.
36 - reg-names: The names of the register addresses corresponding to the registers
56 CTRL_CORE_SMA_SW_0 register and register offset to the CTRL_CORE_SMA_SW_0
57 register that contains the SATA_PLL_SOFT_RESET bit. Only valid for sata_phy.
59 register offset to write the PCS delay value.
[all …]
/src/sys/contrib/device-tree/Bindings/net/
H A Dmicrel.txt12 KSZ8001: register 0x1e, bits 15..14
13 KSZ8041: register 0x1e, bits 15..14
14 KSZ8021: register 0x1f, bits 5..4
15 KSZ8031: register 0x1f, bits 5..4
16 KSZ8051: register 0x1f, bits 5..4
17 KSZ8081: register 0x1f, bits 5..4
18 KSZ8091: register 0x1f, bits 5..4
19 LAN8814: register EP5.0, bit 6
/src/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrFormats.td15 // We instantiate 2 of these for every actual instruction (register based
42 // Generates both register and stack based versions of one actual instruction.
43 // We have 2 sets of operands (oops & iops) for the register and stack
45 // The register versions have virtual-register operands which correspond to wasm
46 // locals or stack locations. Each use and def of the register corresponds to an
49 // instructions do not have register operands (they implicitly operate on the
50 // stack), and local.gets and local.sets are explicit. The register instructions
64 // For instructions that have no register ops, so both sets are the same.
H A DWebAssemblyRegisterInfo.td10 /// This file describes the WebAssembly register classes and some nominal
35 // The register allocation framework requires register classes have at least
36 // one register, so we define a few for the integer / floating point register
37 // classes since we otherwise don't need a physical register in those classes.
50 // The value stack "register". This is an opaque entity which serves to order
54 // The incoming arguments "register". This is an opaque entity which serves to
/src/sys/contrib/device-tree/Bindings/i2c/
H A Di2c-mux-reg.txt3 This binding describes an I2C bus multiplexer that uses a single register
14 - reg: this pair of <offset size> specifies the register to control the mux.
18 - little-endian: The existence indicates the register is in little endian.
19 - big-endian: The existence indicates the register is in big endian.
22 - write-only: The existence indicates the register is write-only.
27 in the relevant node's reg property will be output to the register.
31 register will be set according to the idle value.
34 left programmed into the register.
45 little-endian; /* little endian register on PCIe */
/src/sys/contrib/device-tree/Bindings/mmc/
H A Dsdhci-msm.txt33 - reg: Base address and length of the register in the following order:
34 - Host controller register map (required)
35 - SD Core register map (required for controllers earlier than msm-v5)
36 - CQE register map (Optional, CQE support is present on SDHC instance meant
38 - Inline Crypto Engine register map (optional)
39 - reg-names: When CQE register map is supplied, below reg-names are required
40 - "hc" for Host controller register map
41 - "core" for SD core register map
42 - "cqhci" for CQE register map
43 - "ice" for Inline Crypto Engine register map (optional)
[all …]
H A Dsdhci.txt7 - sdhci-caps-mask: The sdhci capabilities register is incorrect. This 64bit
8 property corresponds to the bits in the sdhci capability register. If the bit
9 is on in the mask then the bit is incorrect in the register and should be
11 - sdhci-caps: The sdhci capabilities register is incorrect. This 64bit
12 property corresponds to the bits in the sdhci capability register. If the
/src/sys/contrib/device-tree/Bindings/serial/
H A Dfsl-lpuart.txt6 on Vybrid vf610 SoC with 8-bit register organization
8 on LS1021A SoC with 32-bit big-endian register organization
10 on LS1028A SoC with 32-bit little-endian register organization
12 on i.MX7ULP SoC with 32-bit little-endian register organization
14 on i.MX8QXP SoC with 32-bit little-endian register organization
16 on i.MX8QM SoC with 32-bit little-endian register organization
17 - reg : Address and length of the register set for the device
/src/sys/contrib/device-tree/Bindings/arm/
H A Dsyna.txt34 CPU control register allows various operations on CPUs, like resetting them
39 - reg: address and length of the register set
50 Marvell Berlin SoCs have a chip control register set providing several
60 - reg: address and length of following register sets for
61 BG2/BG2CD: chip control register set
62 BG2Q: chip control register set and cpu pll registers
66 Marvell Berlin SoCs have a system control register set providing several
73 - reg: address and length of the system control register set

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