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Searched refs:reg_start (Results 1 – 6 of 6) sorted by relevance

/src/sys/contrib/dev/athk/ath12k/
H A Dhal.c533 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_RING_BASE_LSB(ab); in ath12k_hal_srng_create_config_qcn9274()
534 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_RING_HP; in ath12k_hal_srng_create_config_qcn9274()
539 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_SW0_RING_BASE_LSB(ab); in ath12k_hal_srng_create_config_qcn9274()
540 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_SW0_RING_HP; in ath12k_hal_srng_create_config_qcn9274()
543 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_BASE_LSB(ab); in ath12k_hal_srng_create_config_qcn9274()
544 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_HP; in ath12k_hal_srng_create_config_qcn9274()
549 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_RING_BASE_LSB(ab); in ath12k_hal_srng_create_config_qcn9274()
550 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_HP; in ath12k_hal_srng_create_config_qcn9274()
553 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_STATUS_RING_BASE_LSB(ab); in ath12k_hal_srng_create_config_qcn9274()
554 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_STATUS_HP; in ath12k_hal_srng_create_config_qcn9274()
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H A Dhal.h782 u32 reg_start[HAL_SRNG_NUM_REG_GRP]; member
/src/sys/contrib/dev/athk/ath11k/
H A Dhal.c262 srng_config->reg_start[HAL_SRNG_REG_GRP_R0] + in ath11k_hal_ce_dst_setup()
1047 srng->hwreg_base[i] = srng_config->reg_start[i] + in ath11k_hal_srng_setup()
1173 target_reg = srng_config->reg_start[HAL_HP_OFFSET_IN_REG_START]; in ath11k_hal_srng_update_shadow_config()
1253 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_RING_BASE_LSB(ab); in ath11k_hal_srng_create_config()
1254 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_RING_HP(ab); in ath11k_hal_srng_create_config()
1259 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_TCL_RING_BASE_LSB(ab); in ath11k_hal_srng_create_config()
1260 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_TCL_RING_HP(ab); in ath11k_hal_srng_create_config()
1263 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_BASE_LSB(ab); in ath11k_hal_srng_create_config()
1264 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_HP(ab); in ath11k_hal_srng_create_config()
1267 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_RING_BASE_LSB(ab); in ath11k_hal_srng_create_config()
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H A Dhal.h659 u32 reg_start[HAL_SRNG_NUM_REG_GRP]; member
/src/sys/arm64/vmm/io/
H A Dvgic_v3.c176 #define VGIC_REGISTER_RANGE(reg_start, reg_end, reg_size, reg_flags, readf, \ argument
179 .start = (reg_start), \
187 #define VGIC_REGISTER_RANGE_RAZ_WI(reg_start, reg_end, reg_size, reg_flags) \ argument
188 VGIC_REGISTER_RANGE(reg_start, reg_end, reg_size, reg_flags, \
/src/sys/kern/
H A Dsubr_csan.c713 kcsan_bus_space_alloc(bus_space_tag_t tag, bus_addr_t reg_start, in kcsan_bus_space_alloc() argument
719 return (bus_space_alloc(tag, reg_start, reg_end, size, alignment, in kcsan_bus_space_alloc()