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Searched refs:reg_addr (Results 1 – 25 of 59) sorted by relevance

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/src/sys/dev/bxe/
H A Dbxe_dump.h57 struct reg_addr { struct
78 static const struct reg_addr page_read_regs_e2[] = { argument
87 static const struct reg_addr page_read_regs_e3[] = {
91 static const struct reg_addr reg_addrs[] = {
1912 static const struct reg_addr idle_reg_addrs[] = {
H A Decore_init.h256 uint32_t reg_addr, reg_bit_map, vnic; in ecore_map_q_cos() local
277 reg_addr = ECORE_VOQ_Q_REG_ADDR(curr_cos, pf_q_num); in ecore_map_q_cos()
278 reg_bit_map = REG_RD(sc, reg_addr); in ecore_map_q_cos()
279 REG_WR(sc, reg_addr, reg_bit_map & (~q_bit_map)); in ecore_map_q_cos()
282 reg_addr = ECORE_VOQ_Q_REG_ADDR(new_cos, pf_q_num); in ecore_map_q_cos()
283 reg_bit_map = REG_RD(sc, reg_addr); in ecore_map_q_cos()
284 REG_WR(sc, reg_addr, reg_bit_map | q_bit_map); in ecore_map_q_cos()
289 reg_addr = ECORE_Q_CMDQ_REG_ADDR(pf_q_num); in ecore_map_q_cos()
290 reg_bit_map = REG_RD(sc, reg_addr); in ecore_map_q_cos()
295 REG_WR(sc, reg_addr, reg_bit_map); in ecore_map_q_cos()
/src/sys/contrib/alpine-hal/eth/
H A Dal_hal_eth_kr.c215 uint16_t reg_addr; in al_eth_an_lt_reg_read() local
220 reg_addr = al_eth_an_lt_regs_addr[reg_id][AL_ETH_LT_UNIT_REV_1]; in al_eth_an_lt_reg_read()
222 al_reg_write32(&adapter->mac_regs_base->kr.an_addr, reg_addr); in al_eth_an_lt_reg_read()
225 al_reg_write32(&adapter->mac_regs_base->kr.pma_addr, reg_addr); in al_eth_an_lt_reg_read()
231 reg_addr = al_eth_an_lt_regs_addr[reg_id][AL_ETH_LT_UNIT_REV_2]; in al_eth_an_lt_reg_read()
238 reg_addr); in al_eth_an_lt_reg_read()
248 reg_addr); in al_eth_an_lt_reg_read()
258 reg_addr); in al_eth_an_lt_reg_read()
268 reg_addr); in al_eth_an_lt_reg_read()
282 (an_lt == AL_ETH_AN_REGS) ? "AN" : "LT", lane, reg_addr, val); in al_eth_an_lt_reg_read()
[all …]
/src/sys/arm/arm/
H A Ddebug_monitor.c550 uint32_t reg_addr, reg_ctrl; in dbg_find_slot() local
556 reg_addr = DBG_REG_BASE_BVR; in dbg_find_slot()
561 reg_addr = DBG_REG_BASE_WVR; in dbg_find_slot()
570 if ((dbg_wb_read_reg(reg_addr, i) == addr) && in dbg_find_slot()
620 uint32_t reg_ctrl, reg_addr, ctrl, addr; in dbg_setup_xpoint() local
679 reg_addr = DBG_REG_BASE_BVR; in dbg_setup_xpoint()
700 reg_addr = DBG_REG_BASE_WVR; in dbg_setup_xpoint()
706 dbg_wb_write_reg(reg_addr, i, addr); in dbg_setup_xpoint()
737 uint32_t reg_ctrl, reg_addr, addr; in dbg_remove_xpoint() local
751 reg_addr = DBG_REG_BASE_BVR; in dbg_remove_xpoint()
[all …]
/src/sys/contrib/alpine-hal/
H A Dal_hal_udma_main.c109 uint32_t *reg_addr; in al_udma_q_config() local
113 reg_addr = &udma_q->q_regs->m2s_q.rlimit.mask; in al_udma_q_config()
115 val = al_reg_read32(reg_addr); in al_udma_q_config()
118 al_reg_write32(reg_addr, val); in al_udma_q_config()
132 uint32_t *reg_addr; in al_udma_q_config_compl() local
136 reg_addr = &udma_q->q_regs->m2s_q.comp_cfg; in al_udma_q_config_compl()
138 reg_addr = &udma_q->q_regs->s2m_q.comp_cfg; in al_udma_q_config_compl()
140 val = al_reg_read32(reg_addr); in al_udma_q_config_compl()
152 al_reg_write32(reg_addr, val); in al_udma_q_config_compl()
H A Dal_hal_serdes_25g_regs.h61 uint32_t reg_addr; member
/src/sys/dev/al_eth/
H A Dal_init_eth_lm.h174 uint8_t reg_addr, uint8_t *val);
176 uint8_t reg_addr, uint8_t val);
252 uint8_t reg_addr, uint8_t *val);
254 uint8_t reg_addr, uint8_t val);
/src/sys/dev/qat/qat_common/
H A Dqat_hal.c317 unsigned short reg_addr; in qat_hal_get_reg_addr() local
322 reg_addr = 0x80 | (reg_num & 0x7f); in qat_hal_get_reg_addr()
326 reg_addr = reg_num & 0x1f; in qat_hal_get_reg_addr()
331 reg_addr = 0x180 | (reg_num & 0x1f); in qat_hal_get_reg_addr()
334 reg_addr = 0x140 | ((reg_num & 0x3) << 1); in qat_hal_get_reg_addr()
339 reg_addr = 0x1c0 | (reg_num & 0x1f); in qat_hal_get_reg_addr()
342 reg_addr = 0x100 | ((reg_num & 0x3) << 1); in qat_hal_get_reg_addr()
345 reg_addr = 0x280 | (reg_num & 0x1f); in qat_hal_get_reg_addr()
348 reg_addr = 0x200; in qat_hal_get_reg_addr()
351 reg_addr = 0x220; in qat_hal_get_reg_addr()
[all …]
/src/sys/dev/ixgbe/
H A Dixgbe_x550.h64 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
66 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
100 s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
102 s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
H A Dixgbe_phy.h166 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
168 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
170 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
172 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
H A Dixgbe_api.h71 s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
73 s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
215 s32 ixgbe_read_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr,
217 s32 ixgbe_write_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr,
H A Dixgbe_api.c575 s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, in ixgbe_read_phy_reg() argument
581 return ixgbe_call_func(hw, hw->phy.ops.read_reg, (hw, reg_addr, in ixgbe_read_phy_reg()
594 s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, in ixgbe_write_phy_reg() argument
600 return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr, in ixgbe_write_phy_reg()
1321 s32 ixgbe_read_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr, in ixgbe_read_iosf_sb_reg() argument
1324 return ixgbe_call_func(hw, hw->mac.ops.read_iosf_sb_reg, (hw, reg_addr, in ixgbe_read_iosf_sb_reg()
1337 s32 ixgbe_write_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr, in ixgbe_write_iosf_sb_reg() argument
1340 return ixgbe_call_func(hw, hw->mac.ops.write_iosf_sb_reg, (hw, reg_addr, in ixgbe_write_iosf_sb_reg()
H A Dixgbe_phy.c597 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, in ixgbe_read_phy_reg_mdi() argument
603 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | in ixgbe_read_phy_reg_mdi()
634 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | in ixgbe_read_phy_reg_mdi()
679 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, in ixgbe_read_phy_reg_generic() argument
690 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data); in ixgbe_read_phy_reg_generic()
705 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, in ixgbe_write_phy_reg_mdi() argument
714 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | in ixgbe_write_phy_reg_mdi()
743 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | in ixgbe_write_phy_reg_mdi()
779 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, in ixgbe_write_phy_reg_generic() argument
788 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type, in ixgbe_write_phy_reg_generic()
/src/sys/dev/qlnx/qlnxe/
H A Dbcm_osal.h58 extern uint32_t qlnx_direct_reg_rd32(void *p_hwfn, uint32_t *reg_addr);
59 extern void qlnx_direct_reg_wr32(void *p_hwfn, void *reg_addr, uint32_t value);
60 extern void qlnx_direct_reg_wr64(void *p_hwfn, void *reg_addr, uint64_t value);
62 extern uint32_t qlnx_reg_rd32(void *p_hwfn, uint32_t reg_addr);
63 extern void qlnx_reg_wr32(void *p_hwfn, uint32_t reg_addr, uint32_t value);
64 extern void qlnx_reg_wr16(void *p_hwfn, uint32_t reg_addr, uint16_t value);
66 extern void qlnx_dbell_wr32(void *p_hwfn, uint32_t reg_addr, uint32_t value);
67 extern void qlnx_dbell_wr32_db(void *p_hwfn, void *reg_addr, uint32_t value);
/src/sys/dev/cxgb/common/
H A Dcxgb_common.h149 int reg_addr, unsigned int *val);
151 int reg_addr, unsigned int val);
584 int reg_addr, unsigned int *val);
586 int reg_addr, unsigned int val);
626 #define XGM_REG(reg_addr, idx) \ argument
627 ((reg_addr) + (idx) * (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR))
630 unsigned int reg_addr; member
839 int t3_mi1_read(adapter_t *adapter, int phy_addr, int mmd_addr, int reg_addr,
841 int t3_mi1_write(adapter_t *adapter, int phy_addr, int mmd_addr, int reg_addr,
H A Dcxgb_vsc7323.c140 if ((ret = t3_elmr_blk_write(adap, sys_avp[i].reg_addr, in t3_vsc7323_init()
169 if ((ret = t3_elmr_blk_write(adap, fifo_avp[i].reg_addr, in t3_vsc7323_init()
174 if ((ret = t3_elmr_blk_write(adap, xg_avp[i].reg_addr, in t3_vsc7323_init()
/src/sys/dev/vnic/
H A Dnic_main.c889 uint64_t reg_addr; in nic_handle_mbx_intr() local
917 reg_addr = NIC_PF_QSET_0_127_CFG | in nic_handle_mbx_intr()
920 nic_reg_write(nic, reg_addr, cfg); in nic_handle_mbx_intr()
923 reg_addr = NIC_PF_QSET_0_127_RQ_0_7_CFG | in nic_handle_mbx_intr()
926 nic_reg_write(nic, reg_addr, mbx.rq.cfg); in nic_handle_mbx_intr()
929 reg_addr = NIC_PF_QSET_0_127_RQ_0_7_BP_CFG | in nic_handle_mbx_intr()
932 nic_reg_write(nic, reg_addr, mbx.rq.cfg); in nic_handle_mbx_intr()
938 reg_addr = NIC_PF_QSET_0_127_RQ_0_7_DROP_CFG | in nic_handle_mbx_intr()
941 nic_reg_write(nic, reg_addr, mbx.rq.cfg); in nic_handle_mbx_intr()
944 reg_addr = NIC_PF_QSET_0_127_SQ_0_7_CFG | in nic_handle_mbx_intr()
[all …]
/src/contrib/llvm-project/lldb/source/Plugins/Process/Utility/
H A DRegisterContextMemory.cpp93 addr_t reg_addr = m_reg_data_addr + reg_info->byte_offset; in WriteRegister() local
94 Status error(WriteRegisterValueToMemory(reg_info, reg_addr, in WriteRegister()
/src/sys/dev/ixl/
H A Di40e_prototype.h125 u32 reg_addr, u64 reg_val,
128 u32 reg_addr, u64 *reg_val,
576 u32 reg_addr, u32 *reg_val,
578 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr);
580 u32 reg_addr, u32 reg_val,
582 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val);
587 u32 reg_addr, u32 reg_val,
593 u32 reg_addr, u32 *reg_val,
/src/contrib/ofed/libcxgb4/
H A Dt4_regs.h39 #define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr)) argument
42 #define PF0_REG(reg_addr) (PF0_BASE + (reg_addr)) argument
49 #define MYPORT_REG(reg_addr) (MYPORT_BASE + (reg_addr)) argument
52 #define PORT0_REG(reg_addr) (PORT0_BASE + (reg_addr)) argument
61 #define PCIE_MEM_ACCESS_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) argument
62 #define PCIE_MAILBOX_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) argument
63 #define MC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) argument
64 #define EDC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) argument
66 #define PCIE_FW_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) argument
/src/sys/contrib/dev/athk/ath10k/
H A Ddebug.c684 u32 reg_addr; in ath10k_reg_addr_read() local
687 reg_addr = ar->debug.reg_addr; in ath10k_reg_addr_read()
690 len += scnprintf(buf + len, sizeof(buf) - len, "0x%x\n", reg_addr); in ath10k_reg_addr_read()
700 u32 reg_addr; in ath10k_reg_addr_write() local
703 ret = kstrtou32_from_user(user_buf, count, 0, &reg_addr); in ath10k_reg_addr_write()
707 if (!IS_ALIGNED(reg_addr, 4)) in ath10k_reg_addr_write()
711 ar->debug.reg_addr = reg_addr; in ath10k_reg_addr_write()
732 u32 reg_addr, reg_val; in ath10k_reg_value_read() local
743 reg_addr = ar->debug.reg_addr; in ath10k_reg_value_read()
745 reg_val = ath10k_hif_read32(ar, reg_addr); in ath10k_reg_value_read()
[all …]
/src/sys/dev/cxgb/
H A Dcxgb_adapter.h429 t3_read_reg(adapter_t *adapter, uint32_t reg_addr) in t3_read_reg() argument
431 return (bus_space_read_4(adapter->bt, adapter->bh, reg_addr)); in t3_read_reg()
435 t3_write_reg(adapter_t *adapter, uint32_t reg_addr, uint32_t val) in t3_write_reg() argument
437 bus_space_write_4(adapter->bt, adapter->bh, reg_addr, val); in t3_write_reg()
/src/contrib/llvm-project/lldb/source/Commands/
H A DCommandObjectRegister.cpp95 addr_t reg_addr = reg_value.GetAsUInt64(LLDB_INVALID_ADDRESS); in DumpRegister() local
96 if (reg_addr != LLDB_INVALID_ADDRESS) { in DumpRegister()
99 reg_addr, so_reg_addr)) { in DumpRegister()
/src/sys/arm64/arm64/
H A Ddebug_monitor.c416 uint64_t *reg_addr, *reg_ctrl; in dbg_find_slot() local
422 reg_addr = monitor->dbg_bvr; in dbg_find_slot()
427 reg_addr = monitor->dbg_wvr; in dbg_find_slot()
436 if (reg_addr[i] == addr && in dbg_find_slot()
/src/sys/dev/qat/include/common/
H A Dicp_qat_uclo.h293 unsigned int reg_addr; member
326 unsigned int reg_addr; member

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