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Searched refs:rd32 (Results 1 – 25 of 34) sorted by relevance

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/src/sys/dev/ixl/
H A Dixl_pf_i2c.c77 u32 i2cctl = rd32(hw, IXL_I2C_REG(hw)); in ixl_i2c_bus_clear()
114 u32 i2cctl = rd32(hw, IXL_I2C_REG(hw)); in ixl_i2c_stop()
165 u32 i2cctl = rd32(hw, IXL_I2C_REG(hw)); in ixl_clock_in_i2c_bit()
174 i2cctl = rd32(hw, IXL_I2C_REG(hw)); in ixl_clock_in_i2c_bit()
179 i2cctl = rd32(hw, IXL_I2C_REG(hw)); in ixl_clock_in_i2c_bit()
202 u32 i2cctl = rd32(hw, IXL_I2C_REG(hw)); in ixl_get_i2c_ack()
211 i2cctl = rd32(hw, IXL_I2C_REG(hw)); in ixl_get_i2c_ack()
219 i2cctl = rd32(hw, IXL_I2C_REG(hw)); in ixl_get_i2c_ack()
252 u32 i2cctl = rd32(hw, IXL_I2C_REG(hw)); in ixl_clock_out_i2c_bit()
302 i2cctl = rd32(hw, IXL_I2C_REG(hw)); in ixl_clock_out_i2c_byte()
[all …]
H A Di40e_adminq.c318 reg = rd32(hw, hw->aq.asq.bal); in i40e_config_asq_regs()
354 reg = rd32(hw, hw->aq.arq.bal); in i40e_config_arq_regs()
789 while (rd32(hw, hw->aq.asq.head) != ntc) { in i40e_clean_asq()
791 "ntc %d head %d.\n", ntc, rd32(hw, hw->aq.asq.head)); in i40e_clean_asq()
826 return rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use; in i40e_asq_done()
866 val = rd32(hw, hw->aq.asq.head); in i40e_asq_send_command()
1023 if (rd32(hw, hw->aq.asq.len) & I40E_GL_ATQLEN_ATQCRIT_MASK) { in i40e_asq_send_command()
1094 ntu = rd32(hw, hw->aq.arq.head) & I40E_PF_ARQH_ARQH_MASK; in i40e_clean_arq_element()
1096 ntu = rd32(hw, hw->aq.arq.head) & I40E_VF_ARQH1_ARQH_MASK; in i40e_clean_arq_element()
H A Dixl_pf_iflib.c91 icr0 = rd32(hw, I40E_PFINT_ICR0); in ixl_intr()
145 reg = rd32(hw, I40E_PFINT_ICR0); in ixl_msix_adminq()
150 mask = rd32(hw, I40E_PFINT_ICR0_ENA); in ixl_msix_adminq()
167 rstat_reg = rd32(hw, I40E_GLGEN_RSTAT); in ixl_msix_adminq()
210 reg = rd32(hw, I40E_PFHMC_ERRORINFO); in ixl_msix_adminq()
214 reg = rd32(hw, I40E_PFHMC_ERRORDATA); in ixl_msix_adminq()
778 val = rd32(tx_que->vsi->hw, tx_que->txr.tail); in ixl_sysctl_qtx_tail_handler()
800 val = rd32(rx_que->vsi->hw, rx_que->rxr.tail); in ixl_sysctl_qrx_tail_handler()
H A Dixl_pf_main.c244 fwsts = rd32(hw, I40E_GL_FWSTS) & I40E_GL_FWSTS_FWS1B_MASK; in ixl_get_fw_mode()
787 rd32(hw, I40E_PFINT_ICR0); /* read to clear */ in ixl_configure_intr0_msix()
1684 reg = rd32(hw, I40E_QTX_ENA(pf_qidx)); in ixl_enable_tx_ring()
1690 reg = rd32(hw, I40E_QTX_ENA(pf_qidx)); in ixl_enable_tx_ring()
1718 reg = rd32(hw, I40E_QRX_ENA(pf_qidx)); in ixl_enable_rx_ring()
1724 reg = rd32(hw, I40E_QRX_ENA(pf_qidx)); in ixl_enable_rx_ring()
1771 reg = rd32(hw, I40E_QTX_ENA(pf_qidx)); in ixl_disable_tx_ring()
1776 reg = rd32(hw, I40E_QTX_ENA(pf_qidx)); in ixl_disable_tx_ring()
1807 reg = rd32(hw, I40E_QRX_ENA(pf_qidx)); in ixl_disable_rx_ring()
1812 reg = rd32(hw, I40E_QRX_ENA(pf_qidx)); in ixl_disable_rx_ring()
[all …]
H A Di40e_lan_hmc.c135 obj->max_cnt = rd32(hw, I40E_GLHMC_LANQMAX); in i40e_init_lan_hmc()
138 size_exp = rd32(hw, I40E_GLHMC_LANTXOBJSZ); in i40e_init_lan_hmc()
155 obj->max_cnt = rd32(hw, I40E_GLHMC_LANQMAX); in i40e_init_lan_hmc()
161 size_exp = rd32(hw, I40E_GLHMC_LANRXOBJSZ); in i40e_init_lan_hmc()
178 obj->max_cnt = rd32(hw, I40E_GLHMC_FCOEMAX); in i40e_init_lan_hmc()
184 size_exp = rd32(hw, I40E_GLHMC_FCOEDDPOBJSZ); in i40e_init_lan_hmc()
201 obj->max_cnt = rd32(hw, I40E_GLHMC_FCOEFMAX); in i40e_init_lan_hmc()
207 size_exp = rd32(hw, I40E_GLHMC_FCOEFOBJSZ); in i40e_init_lan_hmc()
H A Di40e_common.c399 return !!(rd32(hw, hw->aq.asq.len) & in i40e_check_asq_alive()
402 return !!(rd32(hw, hw->aq.asq.len) & in i40e_check_asq_alive()
1014 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) in i40e_init_shared_code()
1017 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >> in i40e_init_shared_code()
1019 func_rid = rd32(hw, I40E_PF_FUNC_RID); in i40e_init_shared_code()
1166 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); in i40e_pre_tx_queue_cfg()
1307 reg = rd32(hw, I40E_GLGEN_RSTAT); in i40e_poll_globr()
1338 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) & in i40e_pf_reset()
1345 reg = rd32(hw, I40E_GLGEN_RSTAT); in i40e_pf_reset()
1357 reg = rd32(hw, I40E_GLNVM_ULD); in i40e_pf_reset()
[all …]
H A Di40e_nvm.c58 gens = rd32(hw, I40E_GLNVM_GENS); in i40e_init_nvm()
65 fla = rd32(hw, I40E_GLNVM_FLA); in i40e_init_nvm()
102 gtime = rd32(hw, I40E_GLVFGEN_TIMER); in i40e_acquire_nvm()
118 gtime = rd32(hw, I40E_GLVFGEN_TIMER); in i40e_acquire_nvm()
187 srctl = rd32(hw, I40E_GLNVM_SRCTL); in i40e_poll_sr_srctl_done_bit()
234 sr_reg = rd32(hw, I40E_GLNVM_SRDATA); in i40e_read_nvm_word_srctl()
1331 gtime = rd32(hw, I40E_GLVFGEN_TIMER); in i40e_nvmupd_state_writing()
H A Dixl_pf_iov.c363 ciad = rd32(hw, I40E_PF_PCI_CIAD); in ixl_flush_pcie()
382 vfrtrig = rd32(hw, I40E_VPGEN_VFRTRIG(vf->vf_num)); in ixl_reset_vf()
410 vfrstat = rd32(hw, I40E_VPGEN_VFRSTAT(vf->vf_num)); in ixl_reinit_vf()
420 vfrtrig = rd32(hw, I40E_VPGEN_VFRTRIG(vf->vf_num)); in ixl_reinit_vf()
1535 icr0 = rd32(hw, I40E_PFINT_ICR0_ENA); in ixl_handle_vflr()
1549 vflrstat = rd32(hw, I40E_GLGEN_VFLRSTAT(vflrstat_index)); in ixl_handle_vflr()
H A Di40e_osdep.h223 #define rd32(a, reg) rd32_osdep((a)->back, (reg)) macro
/src/sys/dev/irdma/
H A Dicrdma_hw.c276 temp = rd32(vsi->dev->hw, rx_pause_enable + 4 * fn_id); in irdma_is_lfc_set()
278 temp = rd32(vsi->dev->hw, tx_pause_enable + 4 * fn_id); in irdma_is_lfc_set()
280 lfc &= rd32(vsi->dev->hw, in irdma_is_lfc_set()
293 value = rd32(vsi->dev->hw, reg_offset); in irdma_check_tc_has_pfc()
317 pause = (rd32(vsi->dev->hw, rx_pause_enable + 4 * fn_id) >> in irdma_is_pfc_set()
319 pause &= (rd32(vsi->dev->hw, tx_pause_enable + 4 * fn_id) >> in irdma_is_pfc_set()
414 wqm_data = rd32(hw, GLPE_WQMTXIDXDATA); in disable_prefetch()
427 wqm_data = rd32(hw, GLPE_WQMTXIDXDATA); in disable_tx_spad()
438 val = rd32(hw, GL_RDPU_CNTRL); in rdpu_ackreqpmthresh()
H A Dosdep.h188 #define rd32(a, reg) irdma_rd32((a)->dev_context, (reg)) macro
H A Dfbsd_kcompat.c611 val = rd32(&rf->hw, GL_RDPU_CNTRL); in irdma_modify_rdpu_bw()
618 val = rd32(&rf->hw, GL_RDPU_CNTRL); in irdma_modify_rdpu_bw()
/src/sys/dev/ice/
H A Dice_controlq.c110 return (rd32(hw, cq->sq.len) & (cq->sq.len_mask | in ice_check_sq_alive()
280 if (rd32(hw, ring->bal) != ICE_LO_DWORD(ring->desc_buf.pa)) in ice_cfg_cq_regs()
886 head = rd32(hw, sq->head); in ice_clean_sq()
904 head = rd32(hw, sq->head); in ice_clean_sq()
1005 return rd32(hw, cq->sq.head) == cq->sq.next_to_use; in ice_sq_done()
1064 val = rd32(hw, cq->sq.head); in ice_sq_send_cmd_nolock()
1171 if (rd32(hw, cq->rq.len) & cq->rq.len_crit_mask || in ice_sq_send_cmd_nolock()
1172 rd32(hw, cq->sq.len) & cq->sq.len_crit_mask) { in ice_sq_send_cmd_nolock()
1269 ntu = (u16)(rd32(hw, cq->rq.head) & cq->rq.head_mask); in ice_clean_rq_elem()
1324 ntu = (u16)(rd32(hw, cq->rq.head) & cq->rq.head_mask); in ice_clean_rq_elem()
H A Dice_osdep.h85 uint32_t rd32(struct ice_hw *hw, uint32_t reg);
90 #define ice_flush(_hw) rd32((_hw), GLGEN_STAT)
H A Dice_common.c796 val = rd32(hw, E830_PRTMAC_CL01_PAUSE_QUANTA); in ice_fill_tx_timer_and_fc_thresh()
801 val = rd32(hw, E830_PRTMAC_CL01_QUANTA_THRESH); in ice_fill_tx_timer_and_fc_thresh()
805 val = rd32(hw, E800_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(E800_IDX_OF_LFC)); in ice_fill_tx_timer_and_fc_thresh()
811 val = rd32(hw, E800_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(E800_IDX_OF_LFC)); in ice_fill_tx_timer_and_fc_thresh()
962 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) & in ice_get_itr_intrl_gran()
1030 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) & in ice_init_hw()
1231 grst_timeout = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >> in ice_check_reset()
1236 reg = rd32(hw, GLGEN_RSTAT); in ice_check_reset()
1261 reg = rd32(hw, GLNVM_ULD) & uld_mask; in ice_check_reset()
1294 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) || in ice_pf_reset()
[all …]
H A Dice_iov.c491 reg = rd32(hw, GLGEN_VFLRSTAT(reg_idx)); in ice_iov_handle_vflr()
513 reg = rd32(hw, VPGEN_VFRTRIG(vf->vf_num)); in ice_iov_ready_vf()
552 reg = rd32(hw, VPGEN_VFRTRIG(vf->vf_num)); in ice_reset_vf()
568 reg = rd32(hw, PF_PCI_CIAD); in ice_reset_vf()
589 reg = rd32(hw, VPGEN_VFRSTAT(vf->vf_num)); in ice_reset_vf()
H A Dice_vf_mbx.c299 u32 reg = rd32(hw, E830_MBX_VF_IN_FLIGHT_MSGS_AT_PF_CNT(vf_id)); in ice_mbx_vf_clear_cnt_e830()
H A Dice_osdep.c191 rd32(struct ice_hw *hw, uint32_t reg) in rd32() function
H A Dice_lib.c1489 val = rd32(hw, QINT_RQCTL(reg)); in ice_flush_rxq_interrupts()
1526 val = rd32(hw, QINT_TQCTL(reg)); in ice_flush_txq_interrupts()
1768 regval = rd32(hw, QRXFLXP_CNTXT(pf_q)); in ice_setup_rx_ctx()
1842 qrx_ctrl = rd32(hw, QRX_CTRL(pf_q)); in ice_is_rxq_ready()
2158 val = rd32(hw, cq->rq.len); in ice_check_ctrlq_errors()
2177 val = rd32(hw, cq->sq.len); in ice_check_ctrlq_errors()
4741 info = rd32(hw, PFHMC_ERRORINFO); in ice_log_hmc_error()
4742 data = rd32(hw, PFHMC_ERRORDATA); in ice_log_hmc_error()
5272 rd32(hw, PFINT_OICR); in ice_configure_misc_interrupts()
6442 if (rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) { in ice_sysctl_request_reset()
[all …]
H A Dice_nvm.c1428 gens_stat = rd32(hw, GLNVM_GENS); in ice_init_nvm()
1435 fla = rd32(hw, GLNVM_FLA); in ice_init_nvm()
2062 data->regval = rd32(hw, cmd->offset); in ice_nvm_access_read()
/src/sys/dev/iavf/
H A Diavf_adminq.c299 reg = rd32(hw, hw->aq.asq.bal); in iavf_config_asq_regs()
331 reg = rd32(hw, hw->aq.arq.bal); in iavf_config_arq_regs()
618 while (rd32(hw, hw->aq.asq.head) != ntc) { in iavf_clean_asq()
620 "ntc %d head %d.\n", ntc, rd32(hw, hw->aq.asq.head)); in iavf_clean_asq()
655 return rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use; in iavf_asq_done()
695 val = rd32(hw, hw->aq.asq.head); in iavf_asq_send_command()
852 if (rd32(hw, hw->aq.asq.len) & IAVF_VF_ATQLEN1_ATQCRIT_MASK) { in iavf_asq_send_command()
922 ntu = rd32(hw, hw->aq.arq.head) & IAVF_VF_ARQH1_ARQH_MASK; in iavf_clean_arq_element()
H A Dif_iavf_iflib.c1133 oldreg = reg = rd32(hw, hw->aq.arq.len); in iavf_check_aq_errors()
1160 oldreg = reg = rd32(hw, hw->aq.asq.len); in iavf_check_aq_errors()
1236 reg = rd32(hw, IAVF_VFINT_ICR0_ENA1); in iavf_process_adminq()
1382 val = rd32(hw, IAVF_VFGEN_RSTAT) & in iavf_if_timer()
1596 reg = rd32(hw, IAVF_VFINT_ICR01); in iavf_msix_adminq()
1601 mask = rd32(hw, IAVF_VFINT_ICR0_ENA1); in iavf_msix_adminq()
1682 rd32(hw, IAVF_VFGEN_RSTAT); in iavf_disable_queue_irq()
H A Diavf_lib.c205 reg = rd32(hw, IAVF_VFGEN_RSTAT) & in iavf_reset_complete()
376 rd32(hw, IAVF_VFGEN_RSTAT); in iavf_enable_adminq_irq()
1115 hena = (u64)rd32(hw, IAVF_VFQF_HENA(0)) | in iavf_config_rss_reg()
1116 ((u64)rd32(hw, IAVF_VFQF_HENA(1)) << 32); in iavf_config_rss_reg()
H A Diavf_osdep.h246 #define rd32(hw, reg) iavf_rd32(hw, reg) macro
H A Diavf_osdep.c376 rd32(hw, osdep->flush_reg); in iavf_flush()

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