1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (C) 2012-2014 Intel Corporation
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #ifndef __NVME_PRIVATE_H__
30 #define __NVME_PRIVATE_H__
31
32 #include <sys/param.h>
33 #include <sys/bio.h>
34 #include <sys/bus.h>
35 #include <sys/counter.h>
36 #include <sys/kernel.h>
37 #include <sys/lock.h>
38 #include <sys/malloc.h>
39 #include <sys/memdesc.h>
40 #include <sys/module.h>
41 #include <sys/mutex.h>
42 #include <sys/rman.h>
43 #include <sys/systm.h>
44 #include <sys/taskqueue.h>
45
46 #include <vm/uma.h>
47
48 #include <machine/bus.h>
49
50 #include "nvme.h"
51
52 #define DEVICE2SOFTC(dev) ((struct nvme_controller *) device_get_softc(dev))
53
54 MALLOC_DECLARE(M_NVME);
55
56 #define IDT32_PCI_ID 0x80d0111d /* 32 channel board */
57 #define IDT8_PCI_ID 0x80d2111d /* 8 channel board */
58
59 #define NVME_ADMIN_TRACKERS (16)
60 #define NVME_ADMIN_ENTRIES (128)
61
62 /*
63 * NVME_IO_ENTRIES defines the size of an I/O qpair's submission and completion
64 * queues, while NVME_IO_TRACKERS defines the maximum number of I/O that we
65 * will allow outstanding on an I/O qpair at any time. The only advantage in
66 * having IO_ENTRIES > IO_TRACKERS is for debugging purposes - when dumping
67 * the contents of the submission and completion queues, it will show a longer
68 * history of data.
69 */
70 #define NVME_IO_ENTRIES (256)
71 #define NVME_IO_TRACKERS (128)
72 #define NVME_MIN_IO_TRACKERS (4)
73 #define NVME_MAX_IO_TRACKERS (1024)
74
75 #define NVME_INT_COAL_TIME (0) /* disabled */
76 #define NVME_INT_COAL_THRESHOLD (0) /* 0-based */
77
78 #define NVME_MAX_NAMESPACES (16)
79 #define NVME_MAX_ASYNC_EVENTS (8)
80
81 #define NVME_ADMIN_TIMEOUT_PERIOD (60) /* in seconds */
82 #define NVME_DEFAULT_TIMEOUT_PERIOD (30) /* in seconds */
83 #define NVME_MIN_TIMEOUT_PERIOD (5)
84 #define NVME_MAX_TIMEOUT_PERIOD (120)
85
86 #define NVME_DEFAULT_RETRY_COUNT (4)
87
88 /* Maximum log page size to fetch for AERs. */
89 #define NVME_MAX_AER_LOG_SIZE (4096)
90
91 /*
92 * Define CACHE_LINE_SIZE here for older FreeBSD versions that do not define
93 * it.
94 */
95 #ifndef CACHE_LINE_SIZE
96 #define CACHE_LINE_SIZE (64)
97 #endif
98
99 #define NVME_GONE 0xfffffffful
100
101 extern int32_t nvme_retry_count;
102 extern bool nvme_verbose_cmd_dump;
103
104 struct nvme_completion_poll_status {
105 struct nvme_completion cpl;
106 int done;
107 };
108
109 struct nvme_request {
110 struct nvme_command cmd;
111 struct nvme_qpair *qpair;
112 struct memdesc payload;
113 nvme_cb_fn_t cb_fn;
114 void *cb_arg;
115 int16_t retries;
116 uint16_t ioq;
117 #define NVME_IOQ_DEFAULT 0xffff
118 bool payload_valid;
119 bool timeout;
120 bool spare[2]; /* Future use */
121 STAILQ_ENTRY(nvme_request) stailq;
122 };
123
124 struct nvme_async_event_request {
125 struct nvme_controller *ctrlr;
126 struct nvme_request *req;
127 struct task task;
128 struct mtx mtx;
129 struct nvme_completion cpl;
130 uint32_t log_page_id;
131 uint32_t log_page_size;
132 uint8_t log_page_buffer[NVME_MAX_AER_LOG_SIZE];
133 };
134
135 struct nvme_tracker {
136 TAILQ_ENTRY(nvme_tracker) tailq;
137 struct nvme_request *req;
138 struct nvme_qpair *qpair;
139 sbintime_t deadline;
140 bus_dmamap_t payload_dma_map;
141 uint16_t cid;
142
143 uint64_t *prp;
144 bus_addr_t prp_bus_addr;
145 };
146
147 enum nvme_recovery {
148 RECOVERY_NONE = 0, /* Normal operations */
149 RECOVERY_WAITING, /* waiting for the reset to complete */
150 };
151 struct nvme_qpair {
152 struct nvme_controller *ctrlr;
153 uint32_t id;
154 int domain;
155 int cpu;
156
157 uint16_t vector;
158 int rid;
159 struct resource *res;
160 void *tag;
161
162 struct callout timer; /* recovery lock */
163 bool timer_armed; /* recovery lock */
164 enum nvme_recovery recovery_state; /* recovery lock */
165
166 uint32_t num_entries;
167 uint32_t num_trackers;
168 uint32_t sq_tdbl_off;
169 uint32_t cq_hdbl_off;
170
171 uint32_t phase;
172 uint32_t sq_head;
173 uint32_t sq_tail;
174 uint32_t cq_head;
175
176 int64_t num_cmds;
177 int64_t num_intr_handler_calls;
178 int64_t num_retries;
179 int64_t num_failures;
180 int64_t num_ignored;
181 int64_t num_recovery_nolock;
182
183 struct nvme_command *cmd;
184 struct nvme_completion *cpl;
185
186 bus_dma_tag_t dma_tag;
187 bus_dma_tag_t dma_tag_payload;
188
189 bus_dmamap_t queuemem_map;
190 uint64_t cmd_bus_addr;
191 uint64_t cpl_bus_addr;
192
193 TAILQ_HEAD(, nvme_tracker) free_tr;
194 TAILQ_HEAD(, nvme_tracker) outstanding_tr;
195 STAILQ_HEAD(, nvme_request) queued_req;
196
197 struct nvme_tracker **act_tr;
198
199 struct mtx_padalign lock;
200 struct mtx_padalign recovery;
201 } __aligned(CACHE_LINE_SIZE);
202
203 struct nvme_namespace {
204 struct nvme_controller *ctrlr;
205 struct nvme_namespace_data data;
206 uint32_t id;
207 uint32_t flags;
208 struct cdev *cdev;
209 uint32_t boundary;
210 struct mtx lock;
211 };
212
213 /*
214 * One of these per allocated PCI device.
215 */
216 struct nvme_controller {
217 device_t dev;
218
219 struct mtx lock;
220 int domain;
221 uint32_t ready_timeout_in_ms;
222 uint32_t quirks;
223 #define QUIRK_DELAY_B4_CHK_RDY 1 /* Can't touch MMIO on disable */
224 #define QUIRK_DISABLE_TIMEOUT 2 /* Disable broken completion timeout feature */
225 #define QUIRK_INTEL_ALIGNMENT 4 /* Pre NVMe 1.3 performance alignment */
226 #define QUIRK_AHCI 8 /* Attached via AHCI redirect */
227
228 int resource_id;
229 struct resource *resource;
230
231 /*
232 * The NVMe spec allows for the MSI-X table to be placed in BAR 4/5,
233 * separate from the control registers which are in BAR 0/1. These
234 * members track the mapping of BAR 4/5 for that reason.
235 */
236 int msix_table_resource_id;
237 struct resource *msix_table_resource;
238 int msix_pba_resource_id;
239 struct resource *msix_pba_resource;
240
241 int msi_count;
242 uint32_t enable_aborts;
243
244 uint32_t num_io_queues;
245 uint32_t max_hw_pend_io;
246
247 /* Fields for tracking progress during controller initialization. */
248 struct intr_config_hook config_hook;
249 uint32_t ns_identified;
250 uint32_t queues_created;
251
252 struct task reset_task;
253 struct taskqueue *taskqueue;
254
255 /* For shared legacy interrupt. */
256 int rid;
257 struct resource *res;
258 void *tag;
259
260 /** maximum i/o size in bytes */
261 uint32_t max_xfer_size;
262
263 /** LO and HI capacity mask */
264 uint32_t cap_lo;
265 uint32_t cap_hi;
266
267 /** Page size and log2(page_size) - 12 that we're currently using */
268 uint32_t page_size;
269 uint32_t mps;
270
271 /** interrupt coalescing time period (in microseconds) */
272 uint32_t int_coal_time;
273
274 /** interrupt coalescing threshold */
275 uint32_t int_coal_threshold;
276
277 /** timeout period in seconds */
278 uint32_t admin_timeout_period;
279 uint32_t timeout_period;
280
281 /** doorbell stride */
282 uint32_t dstrd;
283
284 struct nvme_qpair adminq;
285 struct nvme_qpair *ioq;
286
287 struct nvme_controller_data cdata;
288 struct nvme_namespace ns[NVME_MAX_NAMESPACES];
289
290 struct cdev *cdev;
291
292 /** bit mask of event types currently enabled for async events */
293 uint32_t async_event_config;
294
295 uint32_t num_aers;
296 struct nvme_async_event_request aer[NVME_MAX_ASYNC_EVENTS];
297
298 uint32_t is_resetting;
299
300 bool fail_on_reset;
301 bool is_failed;
302 bool is_failed_admin;
303 bool is_dying;
304 bool isr_warned;
305 bool is_initialized;
306
307 /* Host Memory Buffer */
308 int hmb_nchunks;
309 size_t hmb_chunk;
310 bus_dma_tag_t hmb_tag;
311 struct nvme_hmb_chunk {
312 bus_dmamap_t hmbc_map;
313 void *hmbc_vaddr;
314 uint64_t hmbc_paddr;
315 } *hmb_chunks;
316 bus_dma_tag_t hmb_desc_tag;
317 bus_dmamap_t hmb_desc_map;
318 struct nvme_hmb_desc *hmb_desc_vaddr;
319 uint64_t hmb_desc_paddr;
320
321 /* Statistics */
322 counter_u64_t alignment_splits;
323 };
324
325 #define nvme_mmio_offsetof(reg) \
326 offsetof(struct nvme_registers, reg)
327
328 #define nvme_mmio_read_4(sc, reg) \
329 bus_read_4((sc)->resource, nvme_mmio_offsetof(reg))
330
331 #define nvme_mmio_write_4(sc, reg, val) \
332 bus_write_4((sc)->resource, nvme_mmio_offsetof(reg), val)
333
334 #define nvme_mmio_write_8(sc, reg, val) \
335 do { \
336 bus_write_4((sc)->resource, nvme_mmio_offsetof(reg), \
337 (val) & 0xFFFFFFFF); \
338 bus_write_4((sc)->resource, nvme_mmio_offsetof(reg) + 4, \
339 ((val) & 0xFFFFFFFF00000000ULL) >> 32); \
340 } while (0);
341
342 #define nvme_printf(ctrlr, fmt, args...) \
343 device_printf(ctrlr->dev, fmt, ##args)
344
345 void nvme_ns_test(struct nvme_namespace *ns, u_long cmd, caddr_t arg);
346
347 void nvme_ctrlr_cmd_identify_controller(struct nvme_controller *ctrlr,
348 void *payload,
349 nvme_cb_fn_t cb_fn, void *cb_arg);
350 void nvme_ctrlr_cmd_identify_namespace(struct nvme_controller *ctrlr,
351 uint32_t nsid, void *payload,
352 nvme_cb_fn_t cb_fn, void *cb_arg);
353 void nvme_ctrlr_cmd_set_interrupt_coalescing(struct nvme_controller *ctrlr,
354 uint32_t microseconds,
355 uint32_t threshold,
356 nvme_cb_fn_t cb_fn,
357 void *cb_arg);
358 void nvme_ctrlr_cmd_get_error_page(struct nvme_controller *ctrlr,
359 struct nvme_error_information_entry *payload,
360 uint32_t num_entries, /* 0 = max */
361 nvme_cb_fn_t cb_fn,
362 void *cb_arg);
363 void nvme_ctrlr_cmd_get_health_information_page(struct nvme_controller *ctrlr,
364 uint32_t nsid,
365 struct nvme_health_information_page *payload,
366 nvme_cb_fn_t cb_fn,
367 void *cb_arg);
368 void nvme_ctrlr_cmd_get_firmware_page(struct nvme_controller *ctrlr,
369 struct nvme_firmware_page *payload,
370 nvme_cb_fn_t cb_fn,
371 void *cb_arg);
372 void nvme_ctrlr_cmd_create_io_cq(struct nvme_controller *ctrlr,
373 struct nvme_qpair *io_que,
374 nvme_cb_fn_t cb_fn, void *cb_arg);
375 void nvme_ctrlr_cmd_create_io_sq(struct nvme_controller *ctrlr,
376 struct nvme_qpair *io_que,
377 nvme_cb_fn_t cb_fn, void *cb_arg);
378 void nvme_ctrlr_cmd_delete_io_cq(struct nvme_controller *ctrlr,
379 struct nvme_qpair *io_que,
380 nvme_cb_fn_t cb_fn, void *cb_arg);
381 void nvme_ctrlr_cmd_delete_io_sq(struct nvme_controller *ctrlr,
382 struct nvme_qpair *io_que,
383 nvme_cb_fn_t cb_fn, void *cb_arg);
384 void nvme_ctrlr_cmd_set_num_queues(struct nvme_controller *ctrlr,
385 uint32_t num_queues, nvme_cb_fn_t cb_fn,
386 void *cb_arg);
387 void nvme_ctrlr_cmd_set_async_event_config(struct nvme_controller *ctrlr,
388 uint32_t state,
389 nvme_cb_fn_t cb_fn, void *cb_arg);
390 void nvme_ctrlr_cmd_abort(struct nvme_controller *ctrlr, uint16_t cid,
391 uint16_t sqid, nvme_cb_fn_t cb_fn, void *cb_arg);
392
393 void nvme_completion_poll_cb(void *arg, const struct nvme_completion *cpl);
394
395 int nvme_ctrlr_construct(struct nvme_controller *ctrlr, device_t dev);
396 void nvme_ctrlr_destruct(struct nvme_controller *ctrlr, device_t dev);
397 void nvme_ctrlr_shutdown(struct nvme_controller *ctrlr);
398 void nvme_ctrlr_reset(struct nvme_controller *ctrlr);
399 /* ctrlr defined as void * to allow use with config_intrhook. */
400 void nvme_ctrlr_start_config_hook(void *ctrlr_arg);
401 void nvme_ctrlr_submit_admin_request(struct nvme_controller *ctrlr,
402 struct nvme_request *req);
403 void nvme_ctrlr_submit_io_request(struct nvme_controller *ctrlr,
404 struct nvme_request *req);
405
406 int nvme_qpair_construct(struct nvme_qpair *qpair,
407 uint32_t num_entries, uint32_t num_trackers,
408 struct nvme_controller *ctrlr);
409 void nvme_qpair_submit_tracker(struct nvme_qpair *qpair,
410 struct nvme_tracker *tr);
411 bool nvme_qpair_process_completions(struct nvme_qpair *qpair);
412 void nvme_qpair_submit_request(struct nvme_qpair *qpair,
413 struct nvme_request *req);
414 void nvme_qpair_reset(struct nvme_qpair *qpair);
415 void nvme_qpair_fail(struct nvme_qpair *qpair);
416
417 void nvme_admin_qpair_enable(struct nvme_qpair *qpair);
418 void nvme_admin_qpair_disable(struct nvme_qpair *qpair);
419 void nvme_admin_qpair_destroy(struct nvme_qpair *qpair);
420
421 void nvme_io_qpair_enable(struct nvme_qpair *qpair);
422 void nvme_io_qpair_disable(struct nvme_qpair *qpair);
423 void nvme_io_qpair_destroy(struct nvme_qpair *qpair);
424
425 int nvme_ns_construct(struct nvme_namespace *ns, uint32_t id,
426 struct nvme_controller *ctrlr);
427 void nvme_ns_destruct(struct nvme_namespace *ns);
428
429 void nvme_sysctl_initialize_ctrlr(struct nvme_controller *ctrlr);
430
431 void nvme_qpair_print_command(struct nvme_qpair *qpair,
432 struct nvme_command *cmd);
433 void nvme_qpair_print_completion(struct nvme_qpair *qpair,
434 struct nvme_completion *cpl);
435
436 int nvme_attach(device_t dev);
437 int nvme_shutdown(device_t dev);
438 int nvme_detach(device_t dev);
439
440 /*
441 * Wait for a command to complete using the nvme_completion_poll_cb. Used in
442 * limited contexts where the caller knows it's OK to block briefly while the
443 * command runs. The ISR will run the callback which will set status->done to
444 * true, usually within microseconds. If not, then after one second timeout
445 * handler should reset the controller and abort all outstanding requests
446 * including this polled one. If still not after ten seconds, then something is
447 * wrong with the driver, and panic is the only way to recover.
448 *
449 * Most commands using this interface aren't actual I/O to the drive's media so
450 * complete within a few microseconds. Adaptively spin for one tick to catch the
451 * vast majority of these without waiting for a tick plus scheduling delays. Since
452 * these are on startup, this drastically reduces startup time.
453 */
454 static __inline void
nvme_completion_poll(struct nvme_completion_poll_status * status)455 nvme_completion_poll(struct nvme_completion_poll_status *status)
456 {
457 int timeout = ticks + 10 * hz;
458 sbintime_t delta = SBT_1US;
459
460 while (!atomic_load_acq_int(&status->done)) {
461 if (timeout - ticks < 0)
462 panic("NVME polled command failed to complete within 10s.");
463 pause_sbt("nvme", delta, 0, C_PREL(1));
464 delta = min(SBT_1MS, delta + delta / 2);
465 }
466 }
467
468 static __inline void
nvme_single_map(void * arg,bus_dma_segment_t * seg,int nseg,int error)469 nvme_single_map(void *arg, bus_dma_segment_t *seg, int nseg, int error)
470 {
471 uint64_t *bus_addr = (uint64_t *)arg;
472
473 KASSERT(nseg == 1, ("number of segments (%d) is not 1", nseg));
474 if (error != 0)
475 printf("nvme_single_map err %d\n", error);
476 *bus_addr = seg[0].ds_addr;
477 }
478
479 static __inline struct nvme_request *
_nvme_allocate_request(const int how,nvme_cb_fn_t cb_fn,void * cb_arg)480 _nvme_allocate_request(const int how, nvme_cb_fn_t cb_fn, void *cb_arg)
481 {
482 struct nvme_request *req;
483
484 KASSERT(how == M_WAITOK || how == M_NOWAIT,
485 ("nvme_allocate_request: invalid how %d", how));
486
487 req = malloc(sizeof(*req), M_NVME, how | M_ZERO);
488 if (req != NULL) {
489 req->ioq = NVME_IOQ_DEFAULT;
490 req->cb_fn = cb_fn;
491 req->cb_arg = cb_arg;
492 req->timeout = true;
493 }
494 return (req);
495 }
496
497 static __inline struct nvme_request *
nvme_allocate_request_vaddr(void * payload,size_t payload_size,const int how,nvme_cb_fn_t cb_fn,void * cb_arg)498 nvme_allocate_request_vaddr(void *payload, size_t payload_size,
499 const int how, nvme_cb_fn_t cb_fn, void *cb_arg)
500 {
501 struct nvme_request *req;
502
503 KASSERT(payload_size <= UINT32_MAX,
504 ("payload size %zu exceeds maximum", payload_size));
505 req = _nvme_allocate_request(how, cb_fn, cb_arg);
506 if (req != NULL) {
507 req->payload = memdesc_vaddr(payload, payload_size);
508 req->payload_valid = true;
509 }
510 return (req);
511 }
512
513 static __inline struct nvme_request *
nvme_allocate_request_null(const int how,nvme_cb_fn_t cb_fn,void * cb_arg)514 nvme_allocate_request_null(const int how, nvme_cb_fn_t cb_fn, void *cb_arg)
515 {
516 struct nvme_request *req;
517
518 req = _nvme_allocate_request(how, cb_fn, cb_arg);
519 return (req);
520 }
521
522 static __inline struct nvme_request *
nvme_allocate_request_bio(struct bio * bio,const int how,nvme_cb_fn_t cb_fn,void * cb_arg)523 nvme_allocate_request_bio(struct bio *bio, const int how, nvme_cb_fn_t cb_fn,
524 void *cb_arg)
525 {
526 struct nvme_request *req;
527
528 req = _nvme_allocate_request(how, cb_fn, cb_arg);
529 if (req != NULL) {
530 req->payload = memdesc_bio(bio);
531 req->payload_valid = true;
532 }
533 return (req);
534 }
535
536 static __inline struct nvme_request *
nvme_allocate_request_ccb(union ccb * ccb,const int how,nvme_cb_fn_t cb_fn,void * cb_arg)537 nvme_allocate_request_ccb(union ccb *ccb, const int how, nvme_cb_fn_t cb_fn,
538 void *cb_arg)
539 {
540 struct nvme_request *req;
541
542 req = _nvme_allocate_request(how, cb_fn, cb_arg);
543 if (req != NULL) {
544 req->payload = memdesc_ccb(ccb);
545 req->payload_valid = true;
546 }
547 return (req);
548 }
549
550 #define nvme_free_request(req) free(req, M_NVME)
551
552 static __inline void
nvme_request_set_ioq(struct nvme_controller * ctrlr,struct nvme_request * req,uint16_t ioq)553 nvme_request_set_ioq(struct nvme_controller *ctrlr, struct nvme_request *req,
554 uint16_t ioq)
555 {
556 /*
557 * Note: NVMe queues are numbered 1-65535. The ioq here is numbered
558 * 0-65534 to avoid off-by-one bugs, with 65535 being reserved for
559 * DEFAULT.
560 */
561 KASSERT(ioq == NVME_IOQ_DEFAULT || ioq < ctrlr->num_io_queues,
562 ("ioq %d out of range 0..%d", ioq, ctrlr->num_io_queues));
563 if (ioq < 0 || ioq >= ctrlr->num_io_queues)
564 ioq = NVME_IOQ_DEFAULT;
565 req->ioq = ioq;
566 }
567
568 void nvme_notify_async(struct nvme_controller *ctrlr,
569 const struct nvme_completion *async_cpl,
570 uint32_t log_page_id, void *log_page_buffer,
571 uint32_t log_page_size);
572 void nvme_notify_fail(struct nvme_controller *ctrlr);
573
574 void nvme_ctrlr_shared_handler(void *arg);
575 void nvme_ctrlr_poll(struct nvme_controller *ctrlr);
576
577 int nvme_ctrlr_suspend(struct nvme_controller *ctrlr);
578 int nvme_ctrlr_resume(struct nvme_controller *ctrlr);
579
580 #endif /* __NVME_PRIVATE_H__ */
581