1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #ifndef __RTW89_FW_H__
6 #define __RTW89_FW_H__
7
8 #include "core.h"
9
10 enum rtw89_fw_dl_status {
11 RTW89_FWDL_INITIAL_STATE = 0,
12 RTW89_FWDL_FWDL_ONGOING = 1,
13 RTW89_FWDL_CHECKSUM_FAIL = 2,
14 RTW89_FWDL_SECURITY_FAIL = 3,
15 RTW89_FWDL_CV_NOT_MATCH = 4,
16 RTW89_FWDL_RSVD0 = 5,
17 RTW89_FWDL_WCPU_FWDL_RDY = 6,
18 RTW89_FWDL_WCPU_FW_INIT_RDY = 7
19 };
20
21 struct rtw89_c2hreg_hdr {
22 u32 w0;
23 };
24
25 #define RTW89_C2HREG_HDR_FUNC_MASK GENMASK(6, 0)
26 #define RTW89_C2HREG_HDR_ACK BIT(7)
27 #define RTW89_C2HREG_HDR_LEN_MASK GENMASK(11, 8)
28 #define RTW89_C2HREG_HDR_SEQ_MASK GENMASK(15, 12)
29
30 struct rtw89_c2hreg_phycap {
31 u32 w0;
32 u32 w1;
33 u32 w2;
34 u32 w3;
35 } __packed;
36
37 #define RTW89_C2HREG_PHYCAP_W0_FUNC GENMASK(6, 0)
38 #define RTW89_C2HREG_PHYCAP_W0_ACK BIT(7)
39 #define RTW89_C2HREG_PHYCAP_W0_LEN GENMASK(11, 8)
40 #define RTW89_C2HREG_PHYCAP_W0_SEQ GENMASK(15, 12)
41 #define RTW89_C2HREG_PHYCAP_W0_RX_NSS GENMASK(23, 16)
42 #define RTW89_C2HREG_PHYCAP_W0_BW GENMASK(31, 24)
43 #define RTW89_C2HREG_PHYCAP_W1_TX_NSS GENMASK(7, 0)
44 #define RTW89_C2HREG_PHYCAP_W1_PROT GENMASK(15, 8)
45 #define RTW89_C2HREG_PHYCAP_W1_NIC GENMASK(23, 16)
46 #define RTW89_C2HREG_PHYCAP_W1_WL_FUNC GENMASK(31, 24)
47 #define RTW89_C2HREG_PHYCAP_W2_HW_TYPE GENMASK(7, 0)
48 #define RTW89_C2HREG_PHYCAP_W3_ANT_TX_NUM GENMASK(15, 8)
49 #define RTW89_C2HREG_PHYCAP_W3_ANT_RX_NUM GENMASK(23, 16)
50 #define RTW89_C2HREG_PHYCAP_W3_BAND_SEL GENMASK(31, 24)
51
52 #define RTW89_C2HREG_PHYCAP_P1_W0_B1_RX_NSS GENMASK(23, 16)
53 #define RTW89_C2HREG_PHYCAP_P1_W0_B1_BW GENMASK(31, 24)
54 #define RTW89_C2HREG_PHYCAP_P1_W1_B1_TX_NSS GENMASK(7, 0)
55 #define RTW89_C2HREG_PHYCAP_P1_W1_B1_ANT_TX_NUM GENMASK(15, 8)
56 #define RTW89_C2HREG_PHYCAP_P1_W1_B1_ANT_RX_NUM GENMASK(23, 16)
57 #define RTW89_C2HREG_PHYCAP_P1_W1_B1_BAND_SEL GENMASK(31, 24)
58 #define RTW89_C2HREG_PHYCAP_P1_W2_QAM GENMASK(7, 0)
59 #define RTW89_C2HREG_PHYCAP_P1_W2_QAM_256 0x1
60 #define RTW89_C2HREG_PHYCAP_P1_W2_QAM_1024 0x2
61 #define RTW89_C2HREG_PHYCAP_P1_W2_QAM_4096 0x3
62 #define RTW89_C2HREG_PHYCAP_P1_W2_B1_QAM GENMASK(15, 8)
63
64 #define RTW89_C2HREG_AOAC_RPT_1_W0_KEY_IDX GENMASK(23, 16)
65 #define RTW89_C2HREG_AOAC_RPT_1_W1_IV_0 GENMASK(7, 0)
66 #define RTW89_C2HREG_AOAC_RPT_1_W1_IV_1 GENMASK(15, 8)
67 #define RTW89_C2HREG_AOAC_RPT_1_W1_IV_2 GENMASK(23, 16)
68 #define RTW89_C2HREG_AOAC_RPT_1_W1_IV_3 GENMASK(31, 24)
69 #define RTW89_C2HREG_AOAC_RPT_1_W2_IV_4 GENMASK(7, 0)
70 #define RTW89_C2HREG_AOAC_RPT_1_W2_IV_5 GENMASK(15, 8)
71 #define RTW89_C2HREG_AOAC_RPT_1_W2_IV_6 GENMASK(23, 16)
72 #define RTW89_C2HREG_AOAC_RPT_1_W2_IV_7 GENMASK(31, 24)
73 #define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_0 GENMASK(7, 0)
74 #define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_1 GENMASK(15, 8)
75 #define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_2 GENMASK(23, 16)
76 #define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_3 GENMASK(31, 24)
77 #define RTW89_C2HREG_AOAC_RPT_2_W0_PTK_IV_4 GENMASK(23, 16)
78 #define RTW89_C2HREG_AOAC_RPT_2_W0_PTK_IV_5 GENMASK(31, 24)
79 #define RTW89_C2HREG_AOAC_RPT_2_W1_PTK_IV_6 GENMASK(7, 0)
80 #define RTW89_C2HREG_AOAC_RPT_2_W1_PTK_IV_7 GENMASK(15, 8)
81 #define RTW89_C2HREG_AOAC_RPT_2_W1_IGTK_IPN_IV_0 GENMASK(23, 16)
82 #define RTW89_C2HREG_AOAC_RPT_2_W1_IGTK_IPN_IV_1 GENMASK(31, 24)
83 #define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_2 GENMASK(7, 0)
84 #define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_3 GENMASK(15, 8)
85 #define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_4 GENMASK(23, 16)
86 #define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_5 GENMASK(31, 24)
87 #define RTW89_C2HREG_AOAC_RPT_2_W3_IGTK_IPN_IV_6 GENMASK(7, 0)
88 #define RTW89_C2HREG_AOAC_RPT_2_W3_IGTK_IPN_IV_7 GENMASK(15, 8)
89
90 #define RTW89_C2HREG_PS_LEAVE_ACK_RET GENMASK(7, 0)
91 #define RTW89_C2HREG_PS_LEAVE_ACK_MACID GENMASK(31, 16)
92
93 struct rtw89_h2creg_hdr {
94 u32 w0;
95 };
96
97 #define RTW89_H2CREG_HDR_FUNC_MASK GENMASK(6, 0)
98 #define RTW89_H2CREG_HDR_LEN_MASK GENMASK(11, 8)
99
100 struct rtw89_h2creg_sch_tx_en {
101 u32 w0;
102 u32 w1;
103 } __packed;
104
105 #define RTW89_H2CREG_SCH_TX_EN_W0_EN GENMASK(31, 16)
106 #define RTW89_H2CREG_SCH_TX_EN_W1_MASK GENMASK(15, 0)
107 #define RTW89_H2CREG_SCH_TX_EN_W1_BAND BIT(16)
108
109 #define RTW89_H2CREG_WOW_CPUIO_RX_CTRL_EN GENMASK(23, 16)
110
111 #define RTW89_H2CREG_GET_FEATURE_PART_NUM GENMASK(23, 16)
112
113 #define RTW89_H2CREG_MAX 4
114 #define RTW89_C2HREG_MAX 4
115 #define RTW89_C2HREG_HDR_LEN 2
116 #define RTW89_H2CREG_HDR_LEN 2
117 #define RTW89_C2H_TIMEOUT 1000000
118 #define RTW89_C2H_TIMEOUT_USB 4000
119
120 struct rtw89_mac_c2h_info {
121 u8 id;
122 u8 content_len;
123 union {
124 u32 c2hreg[RTW89_C2HREG_MAX];
125 struct rtw89_c2hreg_hdr hdr;
126 struct rtw89_c2hreg_phycap phycap;
127 } u;
128 };
129
130 struct rtw89_mac_h2c_info {
131 u8 id;
132 u8 content_len;
133 union {
134 u32 h2creg[RTW89_H2CREG_MAX];
135 struct rtw89_h2creg_hdr hdr;
136 struct rtw89_h2creg_sch_tx_en sch_tx_en;
137 } u;
138 };
139
140 enum rtw89_mac_h2c_type {
141 RTW89_FWCMD_H2CREG_FUNC_H2CREG_LB = 0,
142 RTW89_FWCMD_H2CREG_FUNC_CNSL_CMD,
143 RTW89_FWCMD_H2CREG_FUNC_FWERR,
144 RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE,
145 RTW89_FWCMD_H2CREG_FUNC_GETPKT_INFORM,
146 RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN,
147 RTW89_FWCMD_H2CREG_FUNC_WOW_TRX_STOP,
148 RTW89_FWCMD_H2CREG_FUNC_AOAC_RPT_1,
149 RTW89_FWCMD_H2CREG_FUNC_AOAC_RPT_2,
150 RTW89_FWCMD_H2CREG_FUNC_AOAC_RPT_3_REQ,
151 RTW89_FWCMD_H2CREG_FUNC_WOW_CPUIO_RX_CTRL,
152 };
153
154 enum rtw89_mac_c2h_type {
155 RTW89_FWCMD_C2HREG_FUNC_C2HREG_LB = 0,
156 RTW89_FWCMD_C2HREG_FUNC_ERR_RPT,
157 RTW89_FWCMD_C2HREG_FUNC_ERR_MSG,
158 RTW89_FWCMD_C2HREG_FUNC_PHY_CAP,
159 RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT,
160 RTW89_FWCMD_C2HREG_FUNC_WOW_CPUIO_RX_ACK = 0xA,
161 RTW89_FWCMD_C2HREG_FUNC_PHY_CAP_PART1 = 0xC,
162 RTW89_FWCMD_C2HREG_FUNC_PS_LEAVE_ACK = 0xD,
163 RTW89_FWCMD_C2HREG_FUNC_NULL = 0xFF,
164 };
165
166 enum rtw89_fw_c2h_category {
167 RTW89_C2H_CAT_TEST,
168 RTW89_C2H_CAT_MAC,
169 RTW89_C2H_CAT_OUTSRC,
170 };
171
172 enum rtw89_fw_log_level {
173 RTW89_FW_LOG_LEVEL_OFF,
174 RTW89_FW_LOG_LEVEL_CRT,
175 RTW89_FW_LOG_LEVEL_SER,
176 RTW89_FW_LOG_LEVEL_WARN,
177 RTW89_FW_LOG_LEVEL_LOUD,
178 RTW89_FW_LOG_LEVEL_TR,
179 };
180
181 enum rtw89_fw_log_path {
182 RTW89_FW_LOG_LEVEL_UART,
183 RTW89_FW_LOG_LEVEL_C2H,
184 RTW89_FW_LOG_LEVEL_SNI,
185 };
186
187 enum rtw89_fw_log_comp {
188 RTW89_FW_LOG_COMP_VER,
189 RTW89_FW_LOG_COMP_INIT,
190 RTW89_FW_LOG_COMP_TASK,
191 RTW89_FW_LOG_COMP_CNS,
192 RTW89_FW_LOG_COMP_H2C,
193 RTW89_FW_LOG_COMP_C2H,
194 RTW89_FW_LOG_COMP_TX,
195 RTW89_FW_LOG_COMP_RX,
196 RTW89_FW_LOG_COMP_IPSEC,
197 RTW89_FW_LOG_COMP_TIMER,
198 RTW89_FW_LOG_COMP_DBGPKT,
199 RTW89_FW_LOG_COMP_PS,
200 RTW89_FW_LOG_COMP_ERROR,
201 RTW89_FW_LOG_COMP_WOWLAN,
202 RTW89_FW_LOG_COMP_SECURE_BOOT,
203 RTW89_FW_LOG_COMP_BTC,
204 RTW89_FW_LOG_COMP_BB,
205 RTW89_FW_LOG_COMP_TWT,
206 RTW89_FW_LOG_COMP_RF,
207 RTW89_FW_LOG_COMP_MCC = 20,
208 RTW89_FW_LOG_COMP_MLO = 26,
209 RTW89_FW_LOG_COMP_SCAN = 28,
210 };
211
212 enum rtw89_pkt_offload_op {
213 RTW89_PKT_OFLD_OP_ADD,
214 RTW89_PKT_OFLD_OP_DEL,
215 RTW89_PKT_OFLD_OP_READ,
216
217 NUM_OF_RTW89_PKT_OFFLOAD_OP,
218 };
219
220 #define RTW89_PKT_OFLD_WAIT_TAG(pkt_id, pkt_op) \
221 ((pkt_id) * NUM_OF_RTW89_PKT_OFFLOAD_OP + (pkt_op))
222
223 enum rtw89_scanofld_notify_reason {
224 RTW89_SCAN_DWELL_NOTIFY,
225 RTW89_SCAN_PRE_TX_NOTIFY,
226 RTW89_SCAN_POST_TX_NOTIFY,
227 RTW89_SCAN_ENTER_CH_NOTIFY,
228 RTW89_SCAN_LEAVE_CH_NOTIFY,
229 RTW89_SCAN_END_SCAN_NOTIFY,
230 RTW89_SCAN_REPORT_NOTIFY,
231 RTW89_SCAN_CHKPT_NOTIFY,
232 RTW89_SCAN_ENTER_OP_NOTIFY,
233 RTW89_SCAN_LEAVE_OP_NOTIFY,
234 };
235
236 enum rtw89_scanofld_status {
237 RTW89_SCAN_STATUS_NOTIFY,
238 RTW89_SCAN_STATUS_SUCCESS,
239 RTW89_SCAN_STATUS_FAIL,
240 };
241
242 enum rtw89_chan_type {
243 RTW89_CHAN_OPERATE = 0,
244 RTW89_CHAN_ACTIVE,
245 RTW89_CHAN_DFS,
246 RTW89_CHAN_EXTRA_OP,
247 };
248
249 enum rtw89_p2pps_action {
250 RTW89_P2P_ACT_INIT = 0,
251 RTW89_P2P_ACT_UPDATE = 1,
252 RTW89_P2P_ACT_REMOVE = 2,
253 RTW89_P2P_ACT_TERMINATE = 3,
254 };
255
256 #define RTW89_DEFAULT_CQM_HYST 4
257 #define RTW89_DEFAULT_CQM_THOLD -70
258
259 enum rtw89_bcn_fltr_offload_mode {
260 RTW89_BCN_FLTR_OFFLOAD_MODE_0 = 0,
261 RTW89_BCN_FLTR_OFFLOAD_MODE_1,
262 RTW89_BCN_FLTR_OFFLOAD_MODE_2,
263 RTW89_BCN_FLTR_OFFLOAD_MODE_3,
264
265 RTW89_BCN_FLTR_OFFLOAD_MODE_DEFAULT = RTW89_BCN_FLTR_OFFLOAD_MODE_0,
266 };
267
268 enum rtw89_bcn_fltr_type {
269 RTW89_BCN_FLTR_BEACON_LOSS,
270 RTW89_BCN_FLTR_RSSI,
271 RTW89_BCN_FLTR_NOTIFY,
272 };
273
274 enum rtw89_bcn_fltr_rssi_event {
275 RTW89_BCN_FLTR_RSSI_NOT_CHANGED,
276 RTW89_BCN_FLTR_RSSI_HIGH,
277 RTW89_BCN_FLTR_RSSI_LOW,
278 };
279
280 #define FWDL_SECTION_MAX_NUM 10
281 #define FWDL_SECTION_CHKSUM_LEN 8
282 #define FWDL_SECTION_PER_PKT_LEN 2020
283
284 struct rtw89_fw_hdr_section_info {
285 u8 redl;
286 const u8 *addr;
287 u32 len;
288 u32 len_override;
289 u32 dladdr;
290 u32 mssc;
291 u8 type;
292 bool ignore;
293 const u8 *key_addr;
294 u32 key_len;
295 u32 key_idx;
296 };
297
298 struct rtw89_fw_bin_info {
299 u8 section_num;
300 u32 part_size;
301 u32 hdr_len;
302 bool dynamic_hdr_en;
303 u32 dynamic_hdr_len;
304 u8 idmem_share_mode;
305 bool dsp_checksum;
306 bool secure_section_exist;
307 struct rtw89_fw_hdr_section_info section_info[FWDL_SECTION_MAX_NUM];
308 };
309
310 struct rtw89_fw_macid_pause_grp {
311 __le32 pause_grp[4];
312 __le32 mask_grp[4];
313 } __packed;
314
315 struct rtw89_fw_macid_pause_sleep_grp {
316 struct {
317 __le32 pause_grp[4];
318 __le32 pause_mask_grp[4];
319 __le32 sleep_grp[4];
320 __le32 sleep_mask_grp[4];
321 } __packed n[4];
322 } __packed;
323
324 #define RTW89_H2C_MAX_SIZE 2048
325 #define RTW89_CHANNEL_TIME 45
326 #define RTW89_CHANNEL_TIME_6G 20
327 #define RTW89_CHANNEL_TIME_EXTRA_OP 30
328 #define RTW89_DFS_CHAN_TIME 105
329 #define RTW89_OFF_CHAN_TIME 100
330 #define RTW89_P2P_CHAN_TIME 105
331 #define RTW89_DWELL_TIME 20
332 #define RTW89_DWELL_TIME_6G 10
333 #define RTW89_SCAN_WIDTH 0
334 #define RTW89_SCANOFLD_MAX_SSID 8
335 #define RTW89_SCANOFLD_MAX_IE_LEN 512
336 #define RTW89_SCANOFLD_PKT_NONE 0xFF
337 #define RTW89_SCANOFLD_DEBUG_MASK 0x1F
338 #define RTW89_CHAN_INVALID 0xFF
339 #define RTW89_MAC_CHINFO_SIZE 28
340 #define RTW89_MAC_CHINFO_SIZE_BE 32
341 #define RTW89_SCAN_LIST_GUARD 4
342 #define RTW89_SCAN_LIST_LIMIT(size) \
343 ((RTW89_H2C_MAX_SIZE / (size)) - RTW89_SCAN_LIST_GUARD)
344 #define RTW89_SCAN_LIST_LIMIT_AX RTW89_SCAN_LIST_LIMIT(RTW89_MAC_CHINFO_SIZE)
345 #define RTW89_SCAN_LIST_LIMIT_BE RTW89_SCAN_LIST_LIMIT(RTW89_MAC_CHINFO_SIZE_BE)
346
347 #define RTW89_BCN_LOSS_CNT 60
348
349 struct rtw89_mac_chinfo_ax {
350 u8 period;
351 u8 dwell_time;
352 u8 central_ch;
353 u8 pri_ch;
354 u8 bw:3;
355 u8 notify_action:5;
356 u8 num_pkt:4;
357 u8 tx_pkt:1;
358 u8 pause_data:1;
359 u8 ch_band:2;
360 u8 probe_id;
361 u8 dfs_ch:1;
362 u8 tx_null:1;
363 u8 rand_seq_num:1;
364 u8 cfg_tx_pwr:1;
365 u8 macid_tx: 1;
366 u8 rsvd0: 3;
367 u8 pkt_id[RTW89_SCANOFLD_MAX_SSID];
368 u16 tx_pwr_idx;
369 u8 rsvd1;
370 struct list_head list;
371 bool is_psc;
372 };
373
374 struct rtw89_mac_chinfo_be {
375 u8 period;
376 u8 dwell_time;
377 u8 central_ch;
378 u8 pri_ch;
379 u8 bw:3;
380 u8 ch_band:2;
381 u8 dfs_ch:1;
382 u8 pause_data:1;
383 u8 tx_null:1;
384 u8 rand_seq_num:1;
385 u8 notify_action:5;
386 u8 probe_id;
387 u8 leave_crit;
388 u8 chkpt_timer;
389 u8 leave_time;
390 u8 leave_th;
391 u16 tx_pkt_ctrl;
392 u8 pkt_id[RTW89_SCANOFLD_MAX_SSID];
393 u8 sw_def;
394 u16 fw_probe0_ssids;
395 u16 fw_probe0_shortssids;
396 u16 fw_probe0_bssids;
397
398 struct list_head list;
399 bool is_psc;
400 };
401
402 struct rtw89_pktofld_info {
403 struct list_head list;
404 u8 id;
405 bool wildcard_6ghz;
406
407 /* Below fields are for WiFi 6 chips 6 GHz RNR use only */
408 u8 ssid[IEEE80211_MAX_SSID_LEN];
409 u8 ssid_len;
410 u8 bssid[ETH_ALEN];
411 u16 channel_6ghz;
412 bool cancel;
413 };
414
415 struct rtw89_h2c_ra {
416 __le32 w0;
417 __le32 w1;
418 __le32 w2;
419 __le32 w3;
420 } __packed;
421
422 #define RTW89_H2C_RA_W0_IS_DIS BIT(0)
423 #define RTW89_H2C_RA_W0_MODE GENMASK(5, 1)
424 #define RTW89_H2C_RA_W0_BW_CAP GENMASK(7, 6)
425 #define RTW89_H2C_RA_W0_MACID GENMASK(15, 8)
426 #define RTW89_H2C_RA_W0_DCM BIT(16)
427 #define RTW89_H2C_RA_W0_ER BIT(17)
428 #define RTW89_H2C_RA_W0_INIT_RATE_LV GENMASK(19, 18)
429 #define RTW89_H2C_RA_W0_UPD_ALL BIT(20)
430 #define RTW89_H2C_RA_W0_SGI BIT(21)
431 #define RTW89_H2C_RA_W0_LDPC BIT(22)
432 #define RTW89_H2C_RA_W0_STBC BIT(23)
433 #define RTW89_H2C_RA_W0_SS_NUM GENMASK(26, 24)
434 #define RTW89_H2C_RA_W0_GILTF GENMASK(29, 27)
435 #define RTW89_H2C_RA_W0_UPD_BW_NSS_MASK BIT(30)
436 #define RTW89_H2C_RA_W0_UPD_MASK BIT(31)
437 #define RTW89_H2C_RA_W1_RAMASK_LO32 GENMASK(31, 0)
438 #define RTW89_H2C_RA_W2_RAMASK_HI32 GENMASK(30, 0)
439 #define RTW89_H2C_RA_W2_BFEE_CSI_CTL BIT(31)
440 #define RTW89_H2C_RA_W3_BAND_NUM GENMASK(7, 0)
441 #define RTW89_H2C_RA_W3_RA_CSI_RATE_EN BIT(8)
442 #define RTW89_H2C_RA_W3_FIXED_CSI_RATE_EN BIT(9)
443 #define RTW89_H2C_RA_W3_CR_TBL_SEL BIT(10)
444 #define RTW89_H2C_RA_W3_FIX_GILTF_EN BIT(11)
445 #define RTW89_H2C_RA_W3_FIX_GILTF GENMASK(14, 12)
446 #define RTW89_H2C_RA_W3_FIXED_CSI_MCS_SS_IDX GENMASK(23, 16)
447 #define RTW89_H2C_RA_W3_FIXED_CSI_MODE GENMASK(25, 24)
448 #define RTW89_H2C_RA_W3_FIXED_CSI_GI_LTF GENMASK(28, 26)
449 #define RTW89_H2C_RA_W3_FIXED_CSI_BW GENMASK(31, 29)
450 #define RTW89_H2C_RA_V1_W3_PARTIAL_BW_SU_ER BIT(15)
451 #define RTW89_H2C_RA_V1_W3_FIXED_CSI_RATE_L GENMASK(23, 16)
452 #define RTW89_H2C_RA_V1_W3_IS_NOISY BIT(24)
453 #define RTW89_H2C_RA_V1_W3_PSRA_EN BIT(25)
454 #define RTW89_H2C_RA_V1_W3_MACID_MSB GENMASK(28, 27)
455 #define RTW89_H2C_RA_V1_W3_BAND GENMASK(30, 29)
456 #define RTW89_H2C_RA_V1_W3_NEW_DBGREG BIT(31)
457
458 struct rtw89_h2c_ra_v1 {
459 struct rtw89_h2c_ra v0;
460 __le32 w4;
461 __le32 w5;
462 } __packed;
463
464 #define RTW89_H2C_RA_V1_W4_MODE_EHT GENMASK(6, 0)
465 #define RTW89_H2C_RA_V1_W4_BW_EHT GENMASK(10, 8)
466 #define RTW89_H2C_RA_V1_W4_RAMASK_UHL16 GENMASK(31, 16)
467 #define RTW89_H2C_RA_V1_W5_RAMASK_UHH16 GENMASK(15, 0)
468
RTW89_SET_FWCMD_SEC_IDX(void * cmd,u32 val)469 static inline void RTW89_SET_FWCMD_SEC_IDX(void *cmd, u32 val)
470 {
471 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 0));
472 }
473
RTW89_SET_FWCMD_SEC_OFFSET(void * cmd,u32 val)474 static inline void RTW89_SET_FWCMD_SEC_OFFSET(void *cmd, u32 val)
475 {
476 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8));
477 }
478
RTW89_SET_FWCMD_SEC_LEN(void * cmd,u32 val)479 static inline void RTW89_SET_FWCMD_SEC_LEN(void *cmd, u32 val)
480 {
481 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(23, 16));
482 }
483
RTW89_SET_FWCMD_SEC_TYPE(void * cmd,u32 val)484 static inline void RTW89_SET_FWCMD_SEC_TYPE(void *cmd, u32 val)
485 {
486 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(3, 0));
487 }
488
RTW89_SET_FWCMD_SEC_EXT_KEY(void * cmd,u32 val)489 static inline void RTW89_SET_FWCMD_SEC_EXT_KEY(void *cmd, u32 val)
490 {
491 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(4));
492 }
493
RTW89_SET_FWCMD_SEC_SPP_MODE(void * cmd,u32 val)494 static inline void RTW89_SET_FWCMD_SEC_SPP_MODE(void *cmd, u32 val)
495 {
496 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(5));
497 }
498
RTW89_SET_FWCMD_SEC_KEY0(void * cmd,u32 val)499 static inline void RTW89_SET_FWCMD_SEC_KEY0(void *cmd, u32 val)
500 {
501 le32p_replace_bits((__le32 *)(cmd) + 0x02, val, GENMASK(31, 0));
502 }
503
RTW89_SET_FWCMD_SEC_KEY1(void * cmd,u32 val)504 static inline void RTW89_SET_FWCMD_SEC_KEY1(void *cmd, u32 val)
505 {
506 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(31, 0));
507 }
508
RTW89_SET_FWCMD_SEC_KEY2(void * cmd,u32 val)509 static inline void RTW89_SET_FWCMD_SEC_KEY2(void *cmd, u32 val)
510 {
511 le32p_replace_bits((__le32 *)(cmd) + 0x04, val, GENMASK(31, 0));
512 }
513
RTW89_SET_FWCMD_SEC_KEY3(void * cmd,u32 val)514 static inline void RTW89_SET_FWCMD_SEC_KEY3(void *cmd, u32 val)
515 {
516 le32p_replace_bits((__le32 *)(cmd) + 0x05, val, GENMASK(31, 0));
517 }
518
RTW89_SET_EDCA_SEL(void * cmd,u32 val)519 static inline void RTW89_SET_EDCA_SEL(void *cmd, u32 val)
520 {
521 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(1, 0));
522 }
523
RTW89_SET_EDCA_BAND(void * cmd,u32 val)524 static inline void RTW89_SET_EDCA_BAND(void *cmd, u32 val)
525 {
526 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(3));
527 }
528
RTW89_SET_EDCA_WMM(void * cmd,u32 val)529 static inline void RTW89_SET_EDCA_WMM(void *cmd, u32 val)
530 {
531 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(4));
532 }
533
RTW89_SET_EDCA_AC(void * cmd,u32 val)534 static inline void RTW89_SET_EDCA_AC(void *cmd, u32 val)
535 {
536 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(6, 5));
537 }
538
RTW89_SET_EDCA_PARAM(void * cmd,u32 val)539 static inline void RTW89_SET_EDCA_PARAM(void *cmd, u32 val)
540 {
541 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(31, 0));
542 }
543 #define FW_EDCA_PARAM_TXOPLMT_MSK GENMASK(26, 16)
544 #define FW_EDCA_PARAM_CWMAX_MSK GENMASK(15, 12)
545 #define FW_EDCA_PARAM_CWMIN_MSK GENMASK(11, 8)
546 #define FW_EDCA_PARAM_AIFS_MSK GENMASK(7, 0)
547
548 #define FWDL_SECURITY_SECTION_TYPE 9
549 #define FWDL_SECURITY_SIGLEN 512
550 #define FWDL_SECURITY_CHKSUM_LEN 8
551
552 struct rtw89_fw_dynhdr_sec {
553 __le32 w0;
554 u8 content[];
555 } __packed;
556
557 struct rtw89_fw_dynhdr_hdr {
558 __le32 hdr_len;
559 __le32 setcion_count;
560 /* struct rtw89_fw_dynhdr_sec (nested flexible structures) */
561 } __packed;
562
563 struct rtw89_fw_hdr_section {
564 __le32 w0;
565 __le32 w1;
566 __le32 w2;
567 __le32 w3;
568 } __packed;
569
570 #define FWSECTION_HDR_W0_DL_ADDR GENMASK(31, 0)
571 #define FWSECTION_HDR_W1_METADATA GENMASK(31, 24)
572 #define FWSECTION_HDR_W1_SECTIONTYPE GENMASK(27, 24)
573 #define FWSECTION_HDR_W1_SEC_SIZE GENMASK(23, 0)
574 #define FWSECTION_HDR_W1_CHECKSUM BIT(28)
575 #define FWSECTION_HDR_W1_REDL BIT(29)
576 #define FWSECTION_HDR_W2_MSSC GENMASK(31, 0)
577
578 struct rtw89_fw_hdr {
579 __le32 w0;
580 __le32 w1;
581 __le32 w2;
582 __le32 w3;
583 __le32 w4;
584 __le32 w5;
585 __le32 w6;
586 __le32 w7;
587 struct rtw89_fw_hdr_section sections[];
588 /* struct rtw89_fw_dynhdr_hdr (optional) */
589 } __packed;
590
591 #define FW_HDR_W1_MAJOR_VERSION GENMASK(7, 0)
592 #define FW_HDR_W1_MINOR_VERSION GENMASK(15, 8)
593 #define FW_HDR_W1_SUBVERSION GENMASK(23, 16)
594 #define FW_HDR_W1_SUBINDEX GENMASK(31, 24)
595 #define FW_HDR_W2_COMMITID GENMASK(31, 0)
596 #define FW_HDR_W3_LEN GENMASK(23, 16)
597 #define FW_HDR_W3_HDR_VER GENMASK(31, 24)
598 #define FW_HDR_W4_MONTH GENMASK(7, 0)
599 #define FW_HDR_W4_DATE GENMASK(15, 8)
600 #define FW_HDR_W4_HOUR GENMASK(23, 16)
601 #define FW_HDR_W4_MIN GENMASK(31, 24)
602 #define FW_HDR_W5_YEAR GENMASK(31, 0)
603 #define FW_HDR_W6_SEC_NUM GENMASK(15, 8)
604 #define FW_HDR_W7_PART_SIZE GENMASK(15, 0)
605 #define FW_HDR_W7_DYN_HDR BIT(16)
606 #define FW_HDR_W7_IDMEM_SHARE_MODE GENMASK(21, 18)
607 #define FW_HDR_W7_CMD_VERSERION GENMASK(31, 24)
608
609 struct rtw89_fw_hdr_section_v1 {
610 __le32 w0;
611 __le32 w1;
612 __le32 w2;
613 __le32 w3;
614 } __packed;
615
616 #define FWSECTION_HDR_V1_W0_DL_ADDR GENMASK(31, 0)
617 #define FWSECTION_HDR_V1_W1_METADATA GENMASK(31, 24)
618 #define FWSECTION_HDR_V1_W1_SECTIONTYPE GENMASK(27, 24)
619 #define FWSECTION_HDR_V1_W1_SEC_SIZE GENMASK(23, 0)
620 #define FWSECTION_HDR_V1_W1_CHECKSUM BIT(28)
621 #define FWSECTION_HDR_V1_W1_REDL BIT(29)
622 #define FWSECTION_HDR_V1_W2_MSSC GENMASK(7, 0)
623 #define FORMATTED_MSSC 0xFF
624 #define FORMATTED_MSSC_MASK GENMASK(7, 0)
625 #define FWSECTION_HDR_V1_W2_BBMCU_IDX GENMASK(27, 24)
626
627 struct rtw89_fw_hdr_v1 {
628 __le32 w0;
629 __le32 w1;
630 __le32 w2;
631 __le32 w3;
632 __le32 w4;
633 __le32 w5;
634 __le32 w6;
635 __le32 w7;
636 __le32 w8;
637 __le32 w9;
638 __le32 w10;
639 __le32 w11;
640 struct rtw89_fw_hdr_section_v1 sections[];
641 } __packed;
642
643 #define FW_HDR_V1_W1_MAJOR_VERSION GENMASK(7, 0)
644 #define FW_HDR_V1_W1_MINOR_VERSION GENMASK(15, 8)
645 #define FW_HDR_V1_W1_SUBVERSION GENMASK(23, 16)
646 #define FW_HDR_V1_W1_SUBINDEX GENMASK(31, 24)
647 #define FW_HDR_V1_W2_COMMITID GENMASK(31, 0)
648 #define FW_HDR_V1_W3_CMD_VERSERION GENMASK(23, 16)
649 #define FW_HDR_V1_W3_HDR_VER GENMASK(31, 24)
650 #define FW_HDR_V1_W4_MONTH GENMASK(7, 0)
651 #define FW_HDR_V1_W4_DATE GENMASK(15, 8)
652 #define FW_HDR_V1_W4_HOUR GENMASK(23, 16)
653 #define FW_HDR_V1_W4_MIN GENMASK(31, 24)
654 #define FW_HDR_V1_W5_YEAR GENMASK(15, 0)
655 #define FW_HDR_V1_W5_HDR_SIZE GENMASK(31, 16)
656 #define FW_HDR_V1_W6_SEC_NUM GENMASK(15, 8)
657 #define FW_HDR_V1_W6_DSP_CHKSUM BIT(24)
658 #define FW_HDR_V1_W7_PART_SIZE GENMASK(15, 0)
659 #define FW_HDR_V1_W7_DYN_HDR BIT(16)
660 #define FW_HDR_V1_W7_IDMEM_SHARE_MODE GENMASK(21, 18)
661
662 enum rtw89_fw_mss_pool_rmp_tbl_type {
663 MSS_POOL_RMP_TBL_BITMASK = 0x0,
664 MSS_POOL_RMP_TBL_RECORD = 0x1,
665 };
666
667 #define FWDL_MSS_POOL_DEFKEYSETS_SIZE 8
668
669 struct rtw89_fw_mss_pool_hdr {
670 u8 signature[8]; /* equal to mss_signature[] */
671 __le32 rmp_tbl_offset;
672 __le32 key_raw_offset;
673 u8 defen;
674 u8 rsvd[3];
675 u8 rmpfmt; /* enum rtw89_fw_mss_pool_rmp_tbl_type */
676 u8 mssdev_max;
677 __le16 keypair_num;
678 __le16 msscust_max;
679 __le16 msskey_num_max;
680 __le32 rsvd3;
681 u8 rmp_tbl[];
682 } __packed;
683
684 union rtw89_fw_section_mssc_content {
685 struct {
686 u8 pad[0x20];
687 u8 bit_in_chip_list;
688 u8 ver;
689 } __packed blacklist;
690 struct {
691 u8 pad[58];
692 __le32 v;
693 } __packed sb_sel_ver;
694 struct {
695 u8 pad[60];
696 __le16 v;
697 } __packed key_sign_len;
698 } __packed;
699
700 struct rtw89_fw_blacklist {
701 u8 ver;
702 u8 list[32];
703 };
704
705 extern const struct rtw89_fw_blacklist rtw89_fw_blacklist_default;
706
SET_CTRL_INFO_MACID(void * table,u32 val)707 static inline void SET_CTRL_INFO_MACID(void *table, u32 val)
708 {
709 le32p_replace_bits((__le32 *)(table) + 0, val, GENMASK(6, 0));
710 }
711
SET_CTRL_INFO_OPERATION(void * table,u32 val)712 static inline void SET_CTRL_INFO_OPERATION(void *table, u32 val)
713 {
714 le32p_replace_bits((__le32 *)(table) + 0, val, BIT(7));
715 }
716 #define SET_CMC_TBL_MASK_DATARATE GENMASK(8, 0)
SET_CMC_TBL_DATARATE(void * table,u32 val)717 static inline void SET_CMC_TBL_DATARATE(void *table, u32 val)
718 {
719 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(8, 0));
720 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATARATE,
721 GENMASK(8, 0));
722 }
723 #define SET_CMC_TBL_MASK_FORCE_TXOP BIT(0)
SET_CMC_TBL_FORCE_TXOP(void * table,u32 val)724 static inline void SET_CMC_TBL_FORCE_TXOP(void *table, u32 val)
725 {
726 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(9));
727 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_FORCE_TXOP,
728 BIT(9));
729 }
730 #define SET_CMC_TBL_MASK_DATA_BW GENMASK(1, 0)
SET_CMC_TBL_DATA_BW(void * table,u32 val)731 static inline void SET_CMC_TBL_DATA_BW(void *table, u32 val)
732 {
733 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(11, 10));
734 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_BW,
735 GENMASK(11, 10));
736 }
737 #define SET_CMC_TBL_MASK_DATA_GI_LTF GENMASK(2, 0)
SET_CMC_TBL_DATA_GI_LTF(void * table,u32 val)738 static inline void SET_CMC_TBL_DATA_GI_LTF(void *table, u32 val)
739 {
740 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(14, 12));
741 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_GI_LTF,
742 GENMASK(14, 12));
743 }
744 #define SET_CMC_TBL_MASK_DARF_TC_INDEX BIT(0)
SET_CMC_TBL_DARF_TC_INDEX(void * table,u32 val)745 static inline void SET_CMC_TBL_DARF_TC_INDEX(void *table, u32 val)
746 {
747 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(15));
748 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DARF_TC_INDEX,
749 BIT(15));
750 }
751 #define SET_CMC_TBL_MASK_ARFR_CTRL GENMASK(3, 0)
SET_CMC_TBL_ARFR_CTRL(void * table,u32 val)752 static inline void SET_CMC_TBL_ARFR_CTRL(void *table, u32 val)
753 {
754 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(19, 16));
755 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ARFR_CTRL,
756 GENMASK(19, 16));
757 }
758 #define SET_CMC_TBL_MASK_ACQ_RPT_EN BIT(0)
SET_CMC_TBL_ACQ_RPT_EN(void * table,u32 val)759 static inline void SET_CMC_TBL_ACQ_RPT_EN(void *table, u32 val)
760 {
761 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(20));
762 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ACQ_RPT_EN,
763 BIT(20));
764 }
765 #define SET_CMC_TBL_MASK_MGQ_RPT_EN BIT(0)
SET_CMC_TBL_MGQ_RPT_EN(void * table,u32 val)766 static inline void SET_CMC_TBL_MGQ_RPT_EN(void *table, u32 val)
767 {
768 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(21));
769 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_MGQ_RPT_EN,
770 BIT(21));
771 }
772 #define SET_CMC_TBL_MASK_ULQ_RPT_EN BIT(0)
SET_CMC_TBL_ULQ_RPT_EN(void * table,u32 val)773 static inline void SET_CMC_TBL_ULQ_RPT_EN(void *table, u32 val)
774 {
775 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(22));
776 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ULQ_RPT_EN,
777 BIT(22));
778 }
779 #define SET_CMC_TBL_MASK_TWTQ_RPT_EN BIT(0)
SET_CMC_TBL_TWTQ_RPT_EN(void * table,u32 val)780 static inline void SET_CMC_TBL_TWTQ_RPT_EN(void *table, u32 val)
781 {
782 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(23));
783 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TWTQ_RPT_EN,
784 BIT(23));
785 }
786 #define SET_CMC_TBL_MASK_DISRTSFB BIT(0)
SET_CMC_TBL_DISRTSFB(void * table,u32 val)787 static inline void SET_CMC_TBL_DISRTSFB(void *table, u32 val)
788 {
789 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(25));
790 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISRTSFB,
791 BIT(25));
792 }
793 #define SET_CMC_TBL_MASK_DISDATAFB BIT(0)
SET_CMC_TBL_DISDATAFB(void * table,u32 val)794 static inline void SET_CMC_TBL_DISDATAFB(void *table, u32 val)
795 {
796 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(26));
797 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISDATAFB,
798 BIT(26));
799 }
800 #define SET_CMC_TBL_MASK_TRYRATE BIT(0)
SET_CMC_TBL_TRYRATE(void * table,u32 val)801 static inline void SET_CMC_TBL_TRYRATE(void *table, u32 val)
802 {
803 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(27));
804 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TRYRATE,
805 BIT(27));
806 }
807 #define SET_CMC_TBL_MASK_AMPDU_DENSITY GENMASK(3, 0)
SET_CMC_TBL_AMPDU_DENSITY(void * table,u32 val)808 static inline void SET_CMC_TBL_AMPDU_DENSITY(void *table, u32 val)
809 {
810 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(31, 28));
811 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_AMPDU_DENSITY,
812 GENMASK(31, 28));
813 }
814 #define SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE GENMASK(8, 0)
SET_CMC_TBL_DATA_RTY_LOWEST_RATE(void * table,u32 val)815 static inline void SET_CMC_TBL_DATA_RTY_LOWEST_RATE(void *table, u32 val)
816 {
817 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(8, 0));
818 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE,
819 GENMASK(8, 0));
820 }
821 #define SET_CMC_TBL_MASK_AMPDU_TIME_SEL BIT(0)
SET_CMC_TBL_AMPDU_TIME_SEL(void * table,u32 val)822 static inline void SET_CMC_TBL_AMPDU_TIME_SEL(void *table, u32 val)
823 {
824 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(9));
825 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_TIME_SEL,
826 BIT(9));
827 }
828 #define SET_CMC_TBL_MASK_AMPDU_LEN_SEL BIT(0)
SET_CMC_TBL_AMPDU_LEN_SEL(void * table,u32 val)829 static inline void SET_CMC_TBL_AMPDU_LEN_SEL(void *table, u32 val)
830 {
831 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(10));
832 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_LEN_SEL,
833 BIT(10));
834 }
835 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL BIT(0)
SET_CMC_TBL_RTS_TXCNT_LMT_SEL(void * table,u32 val)836 static inline void SET_CMC_TBL_RTS_TXCNT_LMT_SEL(void *table, u32 val)
837 {
838 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(11));
839 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL,
840 BIT(11));
841 }
842 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT GENMASK(3, 0)
SET_CMC_TBL_RTS_TXCNT_LMT(void * table,u32 val)843 static inline void SET_CMC_TBL_RTS_TXCNT_LMT(void *table, u32 val)
844 {
845 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(15, 12));
846 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT,
847 GENMASK(15, 12));
848 }
849 #define SET_CMC_TBL_MASK_RTSRATE GENMASK(8, 0)
SET_CMC_TBL_RTSRATE(void * table,u32 val)850 static inline void SET_CMC_TBL_RTSRATE(void *table, u32 val)
851 {
852 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(24, 16));
853 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTSRATE,
854 GENMASK(24, 16));
855 }
856 #define SET_CMC_TBL_MASK_VCS_STBC BIT(0)
SET_CMC_TBL_VCS_STBC(void * table,u32 val)857 static inline void SET_CMC_TBL_VCS_STBC(void *table, u32 val)
858 {
859 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(27));
860 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_VCS_STBC,
861 BIT(27));
862 }
863 #define SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE GENMASK(3, 0)
SET_CMC_TBL_RTS_RTY_LOWEST_RATE(void * table,u32 val)864 static inline void SET_CMC_TBL_RTS_RTY_LOWEST_RATE(void *table, u32 val)
865 {
866 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(31, 28));
867 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE,
868 GENMASK(31, 28));
869 }
870 #define SET_CMC_TBL_MASK_DATA_TX_CNT_LMT GENMASK(5, 0)
SET_CMC_TBL_DATA_TX_CNT_LMT(void * table,u32 val)871 static inline void SET_CMC_TBL_DATA_TX_CNT_LMT(void *table, u32 val)
872 {
873 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(5, 0));
874 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TX_CNT_LMT,
875 GENMASK(5, 0));
876 }
877 #define SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL BIT(0)
SET_CMC_TBL_DATA_TXCNT_LMT_SEL(void * table,u32 val)878 static inline void SET_CMC_TBL_DATA_TXCNT_LMT_SEL(void *table, u32 val)
879 {
880 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(6));
881 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL,
882 BIT(6));
883 }
884 #define SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL BIT(0)
SET_CMC_TBL_MAX_AGG_NUM_SEL(void * table,u32 val)885 static inline void SET_CMC_TBL_MAX_AGG_NUM_SEL(void *table, u32 val)
886 {
887 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(7));
888 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL,
889 BIT(7));
890 }
891 #define SET_CMC_TBL_MASK_RTS_EN BIT(0)
SET_CMC_TBL_RTS_EN(void * table,u32 val)892 static inline void SET_CMC_TBL_RTS_EN(void *table, u32 val)
893 {
894 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(8));
895 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_EN,
896 BIT(8));
897 }
898 #define SET_CMC_TBL_MASK_CTS2SELF_EN BIT(0)
SET_CMC_TBL_CTS2SELF_EN(void * table,u32 val)899 static inline void SET_CMC_TBL_CTS2SELF_EN(void *table, u32 val)
900 {
901 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(9));
902 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CTS2SELF_EN,
903 BIT(9));
904 }
905 #define SET_CMC_TBL_MASK_CCA_RTS GENMASK(1, 0)
SET_CMC_TBL_CCA_RTS(void * table,u32 val)906 static inline void SET_CMC_TBL_CCA_RTS(void *table, u32 val)
907 {
908 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(11, 10));
909 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CCA_RTS,
910 GENMASK(11, 10));
911 }
912 #define SET_CMC_TBL_MASK_HW_RTS_EN BIT(0)
SET_CMC_TBL_HW_RTS_EN(void * table,u32 val)913 static inline void SET_CMC_TBL_HW_RTS_EN(void *table, u32 val)
914 {
915 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(12));
916 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_HW_RTS_EN,
917 BIT(12));
918 }
919 #define SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE GENMASK(1, 0)
SET_CMC_TBL_RTS_DROP_DATA_MODE(void * table,u32 val)920 static inline void SET_CMC_TBL_RTS_DROP_DATA_MODE(void *table, u32 val)
921 {
922 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(14, 13));
923 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE,
924 GENMASK(14, 13));
925 }
926 #define SET_CMC_TBL_MASK_AMPDU_MAX_LEN GENMASK(10, 0)
SET_CMC_TBL_AMPDU_MAX_LEN(void * table,u32 val)927 static inline void SET_CMC_TBL_AMPDU_MAX_LEN(void *table, u32 val)
928 {
929 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(26, 16));
930 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_LEN,
931 GENMASK(26, 16));
932 }
933 #define SET_CMC_TBL_MASK_UL_MU_DIS BIT(0)
SET_CMC_TBL_UL_MU_DIS(void * table,u32 val)934 static inline void SET_CMC_TBL_UL_MU_DIS(void *table, u32 val)
935 {
936 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(27));
937 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_UL_MU_DIS,
938 BIT(27));
939 }
940 #define SET_CMC_TBL_MASK_AMPDU_MAX_TIME GENMASK(3, 0)
SET_CMC_TBL_AMPDU_MAX_TIME(void * table,u32 val)941 static inline void SET_CMC_TBL_AMPDU_MAX_TIME(void *table, u32 val)
942 {
943 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(31, 28));
944 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_TIME,
945 GENMASK(31, 28));
946 }
947 #define SET_CMC_TBL_MASK_MAX_AGG_NUM GENMASK(7, 0)
SET_CMC_TBL_MAX_AGG_NUM(void * table,u32 val)948 static inline void SET_CMC_TBL_MAX_AGG_NUM(void *table, u32 val)
949 {
950 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(7, 0));
951 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_MAX_AGG_NUM,
952 GENMASK(7, 0));
953 }
954 #define SET_CMC_TBL_MASK_BA_BMAP GENMASK(1, 0)
SET_CMC_TBL_BA_BMAP(void * table,u32 val)955 static inline void SET_CMC_TBL_BA_BMAP(void *table, u32 val)
956 {
957 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(9, 8));
958 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BA_BMAP,
959 GENMASK(9, 8));
960 }
961 #define SET_CMC_TBL_MASK_VO_LFTIME_SEL GENMASK(2, 0)
SET_CMC_TBL_VO_LFTIME_SEL(void * table,u32 val)962 static inline void SET_CMC_TBL_VO_LFTIME_SEL(void *table, u32 val)
963 {
964 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(18, 16));
965 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VO_LFTIME_SEL,
966 GENMASK(18, 16));
967 }
968 #define SET_CMC_TBL_MASK_VI_LFTIME_SEL GENMASK(2, 0)
SET_CMC_TBL_VI_LFTIME_SEL(void * table,u32 val)969 static inline void SET_CMC_TBL_VI_LFTIME_SEL(void *table, u32 val)
970 {
971 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(21, 19));
972 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VI_LFTIME_SEL,
973 GENMASK(21, 19));
974 }
975 #define SET_CMC_TBL_MASK_BE_LFTIME_SEL GENMASK(2, 0)
SET_CMC_TBL_BE_LFTIME_SEL(void * table,u32 val)976 static inline void SET_CMC_TBL_BE_LFTIME_SEL(void *table, u32 val)
977 {
978 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(24, 22));
979 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BE_LFTIME_SEL,
980 GENMASK(24, 22));
981 }
982 #define SET_CMC_TBL_MASK_BK_LFTIME_SEL GENMASK(2, 0)
SET_CMC_TBL_BK_LFTIME_SEL(void * table,u32 val)983 static inline void SET_CMC_TBL_BK_LFTIME_SEL(void *table, u32 val)
984 {
985 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(27, 25));
986 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BK_LFTIME_SEL,
987 GENMASK(27, 25));
988 }
989 #define SET_CMC_TBL_MASK_SECTYPE GENMASK(3, 0)
SET_CMC_TBL_SECTYPE(void * table,u32 val)990 static inline void SET_CMC_TBL_SECTYPE(void *table, u32 val)
991 {
992 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(31, 28));
993 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_SECTYPE,
994 GENMASK(31, 28));
995 }
996 #define SET_CMC_TBL_MASK_MULTI_PORT_ID GENMASK(2, 0)
SET_CMC_TBL_MULTI_PORT_ID(void * table,u32 val)997 static inline void SET_CMC_TBL_MULTI_PORT_ID(void *table, u32 val)
998 {
999 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(2, 0));
1000 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MULTI_PORT_ID,
1001 GENMASK(2, 0));
1002 }
1003 #define SET_CMC_TBL_MASK_BMC BIT(0)
SET_CMC_TBL_BMC(void * table,u32 val)1004 static inline void SET_CMC_TBL_BMC(void *table, u32 val)
1005 {
1006 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(3));
1007 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_BMC,
1008 BIT(3));
1009 }
1010 #define SET_CMC_TBL_MASK_MBSSID GENMASK(3, 0)
SET_CMC_TBL_MBSSID(void * table,u32 val)1011 static inline void SET_CMC_TBL_MBSSID(void *table, u32 val)
1012 {
1013 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(7, 4));
1014 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MBSSID,
1015 GENMASK(7, 4));
1016 }
1017 #define SET_CMC_TBL_MASK_NAVUSEHDR BIT(0)
SET_CMC_TBL_NAVUSEHDR(void * table,u32 val)1018 static inline void SET_CMC_TBL_NAVUSEHDR(void *table, u32 val)
1019 {
1020 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(8));
1021 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_NAVUSEHDR,
1022 BIT(8));
1023 }
1024 #define SET_CMC_TBL_MASK_TXPWR_MODE GENMASK(2, 0)
SET_CMC_TBL_TXPWR_MODE(void * table,u32 val)1025 static inline void SET_CMC_TBL_TXPWR_MODE(void *table, u32 val)
1026 {
1027 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(11, 9));
1028 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_TXPWR_MODE,
1029 GENMASK(11, 9));
1030 }
1031 #define SET_CMC_TBL_MASK_DATA_DCM BIT(0)
SET_CMC_TBL_DATA_DCM(void * table,u32 val)1032 static inline void SET_CMC_TBL_DATA_DCM(void *table, u32 val)
1033 {
1034 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(12));
1035 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_DCM,
1036 BIT(12));
1037 }
1038 #define SET_CMC_TBL_MASK_DATA_ER BIT(0)
SET_CMC_TBL_DATA_ER(void * table,u32 val)1039 static inline void SET_CMC_TBL_DATA_ER(void *table, u32 val)
1040 {
1041 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(13));
1042 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_ER,
1043 BIT(13));
1044 }
1045 #define SET_CMC_TBL_MASK_DATA_LDPC BIT(0)
SET_CMC_TBL_DATA_LDPC(void * table,u32 val)1046 static inline void SET_CMC_TBL_DATA_LDPC(void *table, u32 val)
1047 {
1048 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(14));
1049 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_LDPC,
1050 BIT(14));
1051 }
1052 #define SET_CMC_TBL_MASK_DATA_STBC BIT(0)
SET_CMC_TBL_DATA_STBC(void * table,u32 val)1053 static inline void SET_CMC_TBL_DATA_STBC(void *table, u32 val)
1054 {
1055 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(15));
1056 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_STBC,
1057 BIT(15));
1058 }
1059 #define SET_CMC_TBL_MASK_A_CTRL_BQR BIT(0)
SET_CMC_TBL_A_CTRL_BQR(void * table,u32 val)1060 static inline void SET_CMC_TBL_A_CTRL_BQR(void *table, u32 val)
1061 {
1062 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(16));
1063 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BQR,
1064 BIT(16));
1065 }
1066 #define SET_CMC_TBL_MASK_A_CTRL_UPH BIT(0)
SET_CMC_TBL_A_CTRL_UPH(void * table,u32 val)1067 static inline void SET_CMC_TBL_A_CTRL_UPH(void *table, u32 val)
1068 {
1069 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(17));
1070 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_UPH,
1071 BIT(17));
1072 }
1073 #define SET_CMC_TBL_MASK_A_CTRL_BSR BIT(0)
SET_CMC_TBL_A_CTRL_BSR(void * table,u32 val)1074 static inline void SET_CMC_TBL_A_CTRL_BSR(void *table, u32 val)
1075 {
1076 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(18));
1077 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BSR,
1078 BIT(18));
1079 }
1080 #define SET_CMC_TBL_MASK_A_CTRL_CAS BIT(0)
SET_CMC_TBL_A_CTRL_CAS(void * table,u32 val)1081 static inline void SET_CMC_TBL_A_CTRL_CAS(void *table, u32 val)
1082 {
1083 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(19));
1084 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_CAS,
1085 BIT(19));
1086 }
1087 #define SET_CMC_TBL_MASK_DATA_BW_ER BIT(0)
SET_CMC_TBL_DATA_BW_ER(void * table,u32 val)1088 static inline void SET_CMC_TBL_DATA_BW_ER(void *table, u32 val)
1089 {
1090 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(20));
1091 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_BW_ER,
1092 BIT(20));
1093 }
1094 #define SET_CMC_TBL_MASK_LSIG_TXOP_EN BIT(0)
SET_CMC_TBL_LSIG_TXOP_EN(void * table,u32 val)1095 static inline void SET_CMC_TBL_LSIG_TXOP_EN(void *table, u32 val)
1096 {
1097 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(21));
1098 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_LSIG_TXOP_EN,
1099 BIT(21));
1100 }
1101 #define SET_CMC_TBL_MASK_CTRL_CNT_VLD BIT(0)
SET_CMC_TBL_CTRL_CNT_VLD(void * table,u32 val)1102 static inline void SET_CMC_TBL_CTRL_CNT_VLD(void *table, u32 val)
1103 {
1104 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(27));
1105 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT_VLD,
1106 BIT(27));
1107 }
1108 #define SET_CMC_TBL_MASK_CTRL_CNT GENMASK(3, 0)
SET_CMC_TBL_CTRL_CNT(void * table,u32 val)1109 static inline void SET_CMC_TBL_CTRL_CNT(void *table, u32 val)
1110 {
1111 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(31, 28));
1112 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT,
1113 GENMASK(31, 28));
1114 }
1115 #define SET_CMC_TBL_MASK_RESP_REF_RATE GENMASK(8, 0)
SET_CMC_TBL_RESP_REF_RATE(void * table,u32 val)1116 static inline void SET_CMC_TBL_RESP_REF_RATE(void *table, u32 val)
1117 {
1118 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(8, 0));
1119 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_RESP_REF_RATE,
1120 GENMASK(8, 0));
1121 }
1122 #define SET_CMC_TBL_MASK_ALL_ACK_SUPPORT BIT(0)
SET_CMC_TBL_ALL_ACK_SUPPORT(void * table,u32 val)1123 static inline void SET_CMC_TBL_ALL_ACK_SUPPORT(void *table, u32 val)
1124 {
1125 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(12));
1126 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ALL_ACK_SUPPORT,
1127 BIT(12));
1128 }
1129 #define SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT BIT(0)
SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(void * table,u32 val)1130 static inline void SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(void *table, u32 val)
1131 {
1132 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(13));
1133 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT,
1134 BIT(13));
1135 }
1136 #define SET_CMC_TBL_MASK_NTX_PATH_EN GENMASK(3, 0)
SET_CMC_TBL_NTX_PATH_EN(void * table,u32 val)1137 static inline void SET_CMC_TBL_NTX_PATH_EN(void *table, u32 val)
1138 {
1139 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(19, 16));
1140 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_NTX_PATH_EN,
1141 GENMASK(19, 16));
1142 }
1143 #define SET_CMC_TBL_MASK_PATH_MAP_A GENMASK(1, 0)
SET_CMC_TBL_PATH_MAP_A(void * table,u32 val)1144 static inline void SET_CMC_TBL_PATH_MAP_A(void *table, u32 val)
1145 {
1146 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(21, 20));
1147 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_A,
1148 GENMASK(21, 20));
1149 }
1150 #define SET_CMC_TBL_MASK_PATH_MAP_B GENMASK(1, 0)
SET_CMC_TBL_PATH_MAP_B(void * table,u32 val)1151 static inline void SET_CMC_TBL_PATH_MAP_B(void *table, u32 val)
1152 {
1153 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(23, 22));
1154 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_B,
1155 GENMASK(23, 22));
1156 }
1157 #define SET_CMC_TBL_MASK_PATH_MAP_C GENMASK(1, 0)
SET_CMC_TBL_PATH_MAP_C(void * table,u32 val)1158 static inline void SET_CMC_TBL_PATH_MAP_C(void *table, u32 val)
1159 {
1160 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(25, 24));
1161 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_C,
1162 GENMASK(25, 24));
1163 }
1164 #define SET_CMC_TBL_MASK_PATH_MAP_D GENMASK(1, 0)
SET_CMC_TBL_PATH_MAP_D(void * table,u32 val)1165 static inline void SET_CMC_TBL_PATH_MAP_D(void *table, u32 val)
1166 {
1167 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(27, 26));
1168 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_D,
1169 GENMASK(27, 26));
1170 }
1171 #define SET_CMC_TBL_MASK_ANTSEL_A BIT(0)
SET_CMC_TBL_ANTSEL_A(void * table,u32 val)1172 static inline void SET_CMC_TBL_ANTSEL_A(void *table, u32 val)
1173 {
1174 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(28));
1175 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_A,
1176 BIT(28));
1177 }
1178 #define SET_CMC_TBL_MASK_ANTSEL_B BIT(0)
SET_CMC_TBL_ANTSEL_B(void * table,u32 val)1179 static inline void SET_CMC_TBL_ANTSEL_B(void *table, u32 val)
1180 {
1181 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(29));
1182 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_B,
1183 BIT(29));
1184 }
1185 #define SET_CMC_TBL_MASK_ANTSEL_C BIT(0)
SET_CMC_TBL_ANTSEL_C(void * table,u32 val)1186 static inline void SET_CMC_TBL_ANTSEL_C(void *table, u32 val)
1187 {
1188 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(30));
1189 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_C,
1190 BIT(30));
1191 }
1192 #define SET_CMC_TBL_MASK_ANTSEL_D BIT(0)
SET_CMC_TBL_ANTSEL_D(void * table,u32 val)1193 static inline void SET_CMC_TBL_ANTSEL_D(void *table, u32 val)
1194 {
1195 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(31));
1196 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_D,
1197 BIT(31));
1198 }
1199
1200 #define SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING GENMASK(1, 0)
SET_CMC_TBL_NOMINAL_PKT_PADDING_V1(void * table,u32 val)1201 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING_V1(void *table, u32 val)
1202 {
1203 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(1, 0));
1204 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1205 GENMASK(1, 0));
1206 }
1207
SET_CMC_TBL_NOMINAL_PKT_PADDING40_V1(void * table,u32 val)1208 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40_V1(void *table, u32 val)
1209 {
1210 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(3, 2));
1211 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1212 GENMASK(3, 2));
1213 }
1214
SET_CMC_TBL_NOMINAL_PKT_PADDING80_V1(void * table,u32 val)1215 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80_V1(void *table, u32 val)
1216 {
1217 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(5, 4));
1218 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1219 GENMASK(5, 4));
1220 }
1221
SET_CMC_TBL_NOMINAL_PKT_PADDING160_V1(void * table,u32 val)1222 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160_V1(void *table, u32 val)
1223 {
1224 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 6));
1225 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1226 GENMASK(7, 6));
1227 }
1228
1229 #define SET_CMC_TBL_MASK_ADDR_CAM_INDEX GENMASK(7, 0)
SET_CMC_TBL_ADDR_CAM_INDEX(void * table,u32 val)1230 static inline void SET_CMC_TBL_ADDR_CAM_INDEX(void *table, u32 val)
1231 {
1232 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 0));
1233 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ADDR_CAM_INDEX,
1234 GENMASK(7, 0));
1235 }
1236 #define SET_CMC_TBL_MASK_PAID GENMASK(8, 0)
SET_CMC_TBL_PAID(void * table,u32 val)1237 static inline void SET_CMC_TBL_PAID(void *table, u32 val)
1238 {
1239 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(16, 8));
1240 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_PAID,
1241 GENMASK(16, 8));
1242 }
1243 #define SET_CMC_TBL_MASK_ULDL BIT(0)
SET_CMC_TBL_ULDL(void * table,u32 val)1244 static inline void SET_CMC_TBL_ULDL(void *table, u32 val)
1245 {
1246 le32p_replace_bits((__le32 *)(table) + 7, val, BIT(17));
1247 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ULDL,
1248 BIT(17));
1249 }
1250 #define SET_CMC_TBL_MASK_DOPPLER_CTRL GENMASK(1, 0)
SET_CMC_TBL_DOPPLER_CTRL(void * table,u32 val)1251 static inline void SET_CMC_TBL_DOPPLER_CTRL(void *table, u32 val)
1252 {
1253 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(19, 18));
1254 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_DOPPLER_CTRL,
1255 GENMASK(19, 18));
1256 }
SET_CMC_TBL_NOMINAL_PKT_PADDING(void * table,u32 val)1257 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING(void *table, u32 val)
1258 {
1259 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(21, 20));
1260 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1261 GENMASK(21, 20));
1262 }
1263
SET_CMC_TBL_NOMINAL_PKT_PADDING40(void * table,u32 val)1264 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40(void *table, u32 val)
1265 {
1266 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(23, 22));
1267 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1268 GENMASK(23, 22));
1269 }
1270 #define SET_CMC_TBL_MASK_TXPWR_TOLERENCE GENMASK(3, 0)
SET_CMC_TBL_TXPWR_TOLERENCE(void * table,u32 val)1271 static inline void SET_CMC_TBL_TXPWR_TOLERENCE(void *table, u32 val)
1272 {
1273 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(27, 24));
1274 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_TXPWR_TOLERENCE,
1275 GENMASK(27, 24));
1276 }
1277
SET_CMC_TBL_NOMINAL_PKT_PADDING80(void * table,u32 val)1278 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80(void *table, u32 val)
1279 {
1280 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(31, 30));
1281 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1282 GENMASK(31, 30));
1283 }
1284 #define SET_CMC_TBL_MASK_NC GENMASK(2, 0)
SET_CMC_TBL_NC(void * table,u32 val)1285 static inline void SET_CMC_TBL_NC(void *table, u32 val)
1286 {
1287 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(2, 0));
1288 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NC,
1289 GENMASK(2, 0));
1290 }
1291 #define SET_CMC_TBL_MASK_NR GENMASK(2, 0)
SET_CMC_TBL_NR(void * table,u32 val)1292 static inline void SET_CMC_TBL_NR(void *table, u32 val)
1293 {
1294 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(5, 3));
1295 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NR,
1296 GENMASK(5, 3));
1297 }
1298 #define SET_CMC_TBL_MASK_NG GENMASK(1, 0)
SET_CMC_TBL_NG(void * table,u32 val)1299 static inline void SET_CMC_TBL_NG(void *table, u32 val)
1300 {
1301 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(7, 6));
1302 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NG,
1303 GENMASK(7, 6));
1304 }
1305 #define SET_CMC_TBL_MASK_CB GENMASK(1, 0)
SET_CMC_TBL_CB(void * table,u32 val)1306 static inline void SET_CMC_TBL_CB(void *table, u32 val)
1307 {
1308 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(9, 8));
1309 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CB,
1310 GENMASK(9, 8));
1311 }
1312 #define SET_CMC_TBL_MASK_CS GENMASK(1, 0)
SET_CMC_TBL_CS(void * table,u32 val)1313 static inline void SET_CMC_TBL_CS(void *table, u32 val)
1314 {
1315 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(11, 10));
1316 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CS,
1317 GENMASK(11, 10));
1318 }
1319 #define SET_CMC_TBL_MASK_CSI_TXBF_EN BIT(0)
SET_CMC_TBL_CSI_TXBF_EN(void * table,u32 val)1320 static inline void SET_CMC_TBL_CSI_TXBF_EN(void *table, u32 val)
1321 {
1322 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(12));
1323 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_TXBF_EN,
1324 BIT(12));
1325 }
1326 #define SET_CMC_TBL_MASK_CSI_STBC_EN BIT(0)
SET_CMC_TBL_CSI_STBC_EN(void * table,u32 val)1327 static inline void SET_CMC_TBL_CSI_STBC_EN(void *table, u32 val)
1328 {
1329 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(13));
1330 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_STBC_EN,
1331 BIT(13));
1332 }
1333 #define SET_CMC_TBL_MASK_CSI_LDPC_EN BIT(0)
SET_CMC_TBL_CSI_LDPC_EN(void * table,u32 val)1334 static inline void SET_CMC_TBL_CSI_LDPC_EN(void *table, u32 val)
1335 {
1336 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(14));
1337 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_LDPC_EN,
1338 BIT(14));
1339 }
1340 #define SET_CMC_TBL_MASK_CSI_PARA_EN BIT(0)
SET_CMC_TBL_CSI_PARA_EN(void * table,u32 val)1341 static inline void SET_CMC_TBL_CSI_PARA_EN(void *table, u32 val)
1342 {
1343 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(15));
1344 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_PARA_EN,
1345 BIT(15));
1346 }
1347 #define SET_CMC_TBL_MASK_CSI_FIX_RATE GENMASK(8, 0)
SET_CMC_TBL_CSI_FIX_RATE(void * table,u32 val)1348 static inline void SET_CMC_TBL_CSI_FIX_RATE(void *table, u32 val)
1349 {
1350 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(24, 16));
1351 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_FIX_RATE,
1352 GENMASK(24, 16));
1353 }
1354 #define SET_CMC_TBL_MASK_CSI_GI_LTF GENMASK(2, 0)
SET_CMC_TBL_CSI_GI_LTF(void * table,u32 val)1355 static inline void SET_CMC_TBL_CSI_GI_LTF(void *table, u32 val)
1356 {
1357 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(27, 25));
1358 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_GI_LTF,
1359 GENMASK(27, 25));
1360 }
1361
SET_CMC_TBL_NOMINAL_PKT_PADDING160(void * table,u32 val)1362 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160(void *table, u32 val)
1363 {
1364 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(29, 28));
1365 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1366 GENMASK(29, 28));
1367 }
1368
1369 #define SET_CMC_TBL_MASK_CSI_BW GENMASK(1, 0)
SET_CMC_TBL_CSI_BW(void * table,u32 val)1370 static inline void SET_CMC_TBL_CSI_BW(void *table, u32 val)
1371 {
1372 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(31, 30));
1373 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_BW,
1374 GENMASK(31, 30));
1375 }
1376
1377 struct rtw89_h2c_cctlinfo_ud_g7 {
1378 __le32 c0;
1379 __le32 w0;
1380 __le32 w1;
1381 __le32 w2;
1382 __le32 w3;
1383 __le32 w4;
1384 __le32 w5;
1385 __le32 w6;
1386 __le32 w7;
1387 __le32 w8;
1388 __le32 w9;
1389 __le32 w10;
1390 __le32 w11;
1391 __le32 w12;
1392 __le32 w13;
1393 __le32 w14;
1394 __le32 w15;
1395 __le32 m0;
1396 __le32 m1;
1397 __le32 m2;
1398 __le32 m3;
1399 __le32 m4;
1400 __le32 m5;
1401 __le32 m6;
1402 __le32 m7;
1403 __le32 m8;
1404 __le32 m9;
1405 __le32 m10;
1406 __le32 m11;
1407 __le32 m12;
1408 __le32 m13;
1409 __le32 m14;
1410 __le32 m15;
1411 } __packed;
1412
1413 #define CCTLINFO_G7_C0_MACID GENMASK(6, 0)
1414 #define CCTLINFO_G7_C0_OP BIT(7)
1415
1416 #define CCTLINFO_G7_W0_DATARATE GENMASK(11, 0)
1417 #define CCTLINFO_G7_W0_DATA_GI_LTF GENMASK(14, 12)
1418 #define CCTLINFO_G7_W0_TRYRATE BIT(15)
1419 #define CCTLINFO_G7_W0_ARFR_CTRL GENMASK(17, 16)
1420 #define CCTLINFO_G7_W0_DIS_HE1SS_STBC BIT(18)
1421 #define CCTLINFO_G7_W0_ACQ_RPT_EN BIT(20)
1422 #define CCTLINFO_G7_W0_MGQ_RPT_EN BIT(21)
1423 #define CCTLINFO_G7_W0_ULQ_RPT_EN BIT(22)
1424 #define CCTLINFO_G7_W0_TWTQ_RPT_EN BIT(23)
1425 #define CCTLINFO_G7_W0_FORCE_TXOP BIT(24)
1426 #define CCTLINFO_G7_W0_DISRTSFB BIT(25)
1427 #define CCTLINFO_G7_W0_DISDATAFB BIT(26)
1428 #define CCTLINFO_G7_W0_NSTR_EN BIT(27)
1429 #define CCTLINFO_G7_W0_AMPDU_DENSITY GENMASK(31, 28)
1430 #define CCTLINFO_G7_W0_ALL (GENMASK(31, 20) | GENMASK(18, 0))
1431 #define CCTLINFO_G7_W1_DATA_RTY_LOWEST_RATE GENMASK(11, 0)
1432 #define CCTLINFO_G7_W1_RTS_TXCNT_LMT GENMASK(15, 12)
1433 #define CCTLINFO_G7_W1_RTSRATE GENMASK(27, 16)
1434 #define CCTLINFO_G7_W1_RTS_RTY_LOWEST_RATE GENMASK(31, 28)
1435 #define CCTLINFO_G7_W1_ALL GENMASK(31, 0)
1436 #define CCTLINFO_G7_W2_DATA_TX_CNT_LMT GENMASK(5, 0)
1437 #define CCTLINFO_G7_W2_DATA_TXCNT_LMT_SEL BIT(6)
1438 #define CCTLINFO_G7_W2_MAX_AGG_NUM_SEL BIT(7)
1439 #define CCTLINFO_G7_W2_RTS_EN BIT(8)
1440 #define CCTLINFO_G7_W2_CTS2SELF_EN BIT(9)
1441 #define CCTLINFO_G7_W2_CCA_RTS GENMASK(11, 10)
1442 #define CCTLINFO_G7_W2_HW_RTS_EN BIT(12)
1443 #define CCTLINFO_G7_W2_RTS_DROP_DATA_MODE GENMASK(14, 13)
1444 #define CCTLINFO_G7_W2_PRELD_EN BIT(15)
1445 #define CCTLINFO_G7_W2_AMPDU_MAX_LEN GENMASK(26, 16)
1446 #define CCTLINFO_G7_W2_UL_MU_DIS BIT(27)
1447 #define CCTLINFO_G7_W2_AMPDU_MAX_TIME GENMASK(31, 28)
1448 #define CCTLINFO_G7_W2_ALL GENMASK(31, 0)
1449 #define CCTLINFO_G7_W3_MAX_AGG_NUM GENMASK(7, 0)
1450 #define CCTLINFO_G7_W3_DATA_BW GENMASK(10, 8)
1451 #define CCTLINFO_G7_W3_DATA_BW_ER BIT(11)
1452 #define CCTLINFO_G7_W3_BA_BMAP GENMASK(14, 12)
1453 #define CCTLINFO_G7_W3_VCS_STBC BIT(15)
1454 #define CCTLINFO_G7_W3_VO_LFTIME_SEL GENMASK(18, 16)
1455 #define CCTLINFO_G7_W3_VI_LFTIME_SEL GENMASK(21, 19)
1456 #define CCTLINFO_G7_W3_BE_LFTIME_SEL GENMASK(24, 22)
1457 #define CCTLINFO_G7_W3_BK_LFTIME_SEL GENMASK(27, 25)
1458 #define CCTLINFO_G7_W3_AMPDU_TIME_SEL BIT(28)
1459 #define CCTLINFO_G7_W3_AMPDU_LEN_SEL BIT(29)
1460 #define CCTLINFO_G7_W3_RTS_TXCNT_LMT_SEL BIT(30)
1461 #define CCTLINFO_G7_W3_LSIG_TXOP_EN BIT(31)
1462 #define CCTLINFO_G7_W3_ALL GENMASK(31, 0)
1463 #define CCTLINFO_G7_W4_MULTI_PORT_ID GENMASK(2, 0)
1464 #define CCTLINFO_G7_W4_BYPASS_PUNC BIT(3)
1465 #define CCTLINFO_G7_W4_MBSSID GENMASK(7, 4)
1466 #define CCTLINFO_G7_W4_DATA_DCM BIT(8)
1467 #define CCTLINFO_G7_W4_DATA_ER BIT(9)
1468 #define CCTLINFO_G7_W4_DATA_LDPC BIT(10)
1469 #define CCTLINFO_G7_W4_DATA_STBC BIT(11)
1470 #define CCTLINFO_G7_W4_A_CTRL_BQR BIT(12)
1471 #define CCTLINFO_G7_W4_A_CTRL_BSR BIT(14)
1472 #define CCTLINFO_G7_W4_A_CTRL_CAS BIT(15)
1473 #define CCTLINFO_G7_W4_ACT_SUBCH_CBW GENMASK(31, 16)
1474 #define CCTLINFO_G7_W4_ALL (GENMASK(31, 14) | GENMASK(12, 0))
1475 #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING0 GENMASK(1, 0)
1476 #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING1 GENMASK(3, 2)
1477 #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING2 GENMASK(5, 4)
1478 #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING3 GENMASK(7, 6)
1479 #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING4 GENMASK(9, 8)
1480 #define CCTLINFO_G7_W5_SR_RATE GENMASK(14, 10)
1481 #define CCTLINFO_G7_W5_TID_DISABLE GENMASK(23, 16)
1482 #define CCTLINFO_G7_W5_ADDR_CAM_INDEX GENMASK(31, 24)
1483 #define CCTLINFO_G7_W5_ALL (GENMASK(31, 16) | GENMASK(14, 0))
1484 #define CCTLINFO_G7_W6_AID12_PAID GENMASK(11, 0)
1485 #define CCTLINFO_G7_W6_RESP_REF_RATE GENMASK(23, 12)
1486 #define CCTLINFO_G7_W6_ULDL BIT(31)
1487 #define CCTLINFO_G7_W6_ALL (BIT(31) | GENMASK(23, 0))
1488 #define CCTLINFO_G7_W7_NC GENMASK(2, 0)
1489 #define CCTLINFO_G7_W7_NR GENMASK(5, 3)
1490 #define CCTLINFO_G7_W7_NG GENMASK(7, 6)
1491 #define CCTLINFO_G7_W7_CB GENMASK(9, 8)
1492 #define CCTLINFO_G7_W7_CS GENMASK(11, 10)
1493 #define CCTLINFO_G7_W7_CSI_STBC_EN BIT(13)
1494 #define CCTLINFO_G7_W7_CSI_LDPC_EN BIT(14)
1495 #define CCTLINFO_G7_W7_CSI_PARA_EN BIT(15)
1496 #define CCTLINFO_G7_W7_CSI_FIX_RATE GENMASK(27, 16)
1497 #define CCTLINFO_G7_W7_CSI_BW GENMASK(31, 29)
1498 #define CCTLINFO_G7_W7_ALL (GENMASK(31, 29) | GENMASK(27, 13) | GENMASK(11, 0))
1499 #define CCTLINFO_G7_W8_ALL_ACK_SUPPORT BIT(0)
1500 #define CCTLINFO_G7_W8_BSR_QUEUE_SIZE_FORMAT BIT(1)
1501 #define CCTLINFO_G7_W8_BSR_OM_UPD_EN BIT(2)
1502 #define CCTLINFO_G7_W8_MACID_FWD_IDC BIT(3)
1503 #define CCTLINFO_G7_W8_AZ_SEC_EN BIT(4)
1504 #define CCTLINFO_G7_W8_CSI_SEC_EN BIT(5)
1505 #define CCTLINFO_G7_W8_FIX_UL_ADDRCAM_IDX BIT(6)
1506 #define CCTLINFO_G7_W8_CTRL_CNT_VLD BIT(7)
1507 #define CCTLINFO_G7_W8_CTRL_CNT GENMASK(11, 8)
1508 #define CCTLINFO_G7_W8_RESP_SEC_TYPE GENMASK(15, 12)
1509 #define CCTLINFO_G7_W8_ALL GENMASK(15, 0)
1510 /* W9~13 are reserved */
1511 #define CCTLINFO_G7_W14_VO_CURR_RATE GENMASK(11, 0)
1512 #define CCTLINFO_G7_W14_VI_CURR_RATE GENMASK(23, 12)
1513 #define CCTLINFO_G7_W14_BE_CURR_RATE_L GENMASK(31, 24)
1514 #define CCTLINFO_G7_W14_ALL GENMASK(31, 0)
1515 #define CCTLINFO_G7_W15_BE_CURR_RATE_H GENMASK(3, 0)
1516 #define CCTLINFO_G7_W15_BK_CURR_RATE GENMASK(15, 4)
1517 #define CCTLINFO_G7_W15_MGNT_CURR_RATE GENMASK(27, 16)
1518 #define CCTLINFO_G7_W15_ALL GENMASK(27, 0)
1519
1520 struct rtw89_h2c_bcn_upd {
1521 __le32 w0;
1522 __le32 w1;
1523 __le32 w2;
1524 } __packed;
1525
1526 #define RTW89_H2C_BCN_UPD_W0_PORT GENMASK(7, 0)
1527 #define RTW89_H2C_BCN_UPD_W0_MBSSID GENMASK(15, 8)
1528 #define RTW89_H2C_BCN_UPD_W0_BAND GENMASK(23, 16)
1529 #define RTW89_H2C_BCN_UPD_W0_GRP_IE_OFST GENMASK(31, 24)
1530 #define RTW89_H2C_BCN_UPD_W1_MACID GENMASK(7, 0)
1531 #define RTW89_H2C_BCN_UPD_W1_SSN_SEL GENMASK(9, 8)
1532 #define RTW89_H2C_BCN_UPD_W1_SSN_MODE GENMASK(11, 10)
1533 #define RTW89_H2C_BCN_UPD_W1_RATE GENMASK(20, 12)
1534 #define RTW89_H2C_BCN_UPD_W1_TXPWR GENMASK(23, 21)
1535 #define RTW89_H2C_BCN_UPD_W2_TXINFO_CTRL_EN BIT(0)
1536 #define RTW89_H2C_BCN_UPD_W2_NTX_PATH_EN GENMASK(4, 1)
1537 #define RTW89_H2C_BCN_UPD_W2_PATH_MAP_A GENMASK(6, 5)
1538 #define RTW89_H2C_BCN_UPD_W2_PATH_MAP_B GENMASK(8, 7)
1539 #define RTW89_H2C_BCN_UPD_W2_PATH_MAP_C GENMASK(10, 9)
1540 #define RTW89_H2C_BCN_UPD_W2_PATH_MAP_D GENMASK(12, 11)
1541 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_A BIT(13)
1542 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_B BIT(14)
1543 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_C BIT(15)
1544 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_D BIT(16)
1545 #define RTW89_H2C_BCN_UPD_W2_CSA_OFST GENMASK(31, 17)
1546
1547 struct rtw89_h2c_bcn_upd_be {
1548 __le32 w0;
1549 __le32 w1;
1550 __le32 w2;
1551 __le32 w3;
1552 __le32 w4;
1553 __le32 w5;
1554 __le32 w6;
1555 __le32 w7;
1556 __le32 w8;
1557 __le32 w9;
1558 __le32 w10;
1559 __le32 w11;
1560 __le32 w12;
1561 __le32 w13;
1562 __le32 w14;
1563 __le32 w15;
1564 __le32 w16;
1565 __le32 w17;
1566 __le32 w18;
1567 __le32 w19;
1568 __le32 w20;
1569 __le32 w21;
1570 __le32 w22;
1571 __le32 w23;
1572 __le32 w24;
1573 __le32 w25;
1574 __le32 w26;
1575 __le32 w27;
1576 __le32 w28;
1577 __le32 w29;
1578 } __packed;
1579
1580 #define RTW89_H2C_BCN_UPD_BE_W0_PORT GENMASK(7, 0)
1581 #define RTW89_H2C_BCN_UPD_BE_W0_MBSSID GENMASK(15, 8)
1582 #define RTW89_H2C_BCN_UPD_BE_W0_BAND GENMASK(23, 16)
1583 #define RTW89_H2C_BCN_UPD_BE_W0_GRP_IE_OFST GENMASK(31, 24)
1584 #define RTW89_H2C_BCN_UPD_BE_W1_MACID GENMASK(7, 0)
1585 #define RTW89_H2C_BCN_UPD_BE_W1_SSN_SEL GENMASK(9, 8)
1586 #define RTW89_H2C_BCN_UPD_BE_W1_SSN_MODE GENMASK(11, 10)
1587 #define RTW89_H2C_BCN_UPD_BE_W1_RATE GENMASK(20, 12)
1588 #define RTW89_H2C_BCN_UPD_BE_W1_TXPWR GENMASK(23, 21)
1589 #define RTW89_H2C_BCN_UPD_BE_W1_MACID_EXT GENMASK(31, 24)
1590 #define RTW89_H2C_BCN_UPD_BE_W2_TXINFO_CTRL_EN BIT(0)
1591 #define RTW89_H2C_BCN_UPD_BE_W2_NTX_PATH_EN GENMASK(4, 1)
1592 #define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_A GENMASK(6, 5)
1593 #define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_B GENMASK(8, 7)
1594 #define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_C GENMASK(10, 9)
1595 #define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_D GENMASK(12, 11)
1596 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_A BIT(13)
1597 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_B BIT(14)
1598 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_C BIT(15)
1599 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_D BIT(16)
1600 #define RTW89_H2C_BCN_UPD_BE_W2_CSA_OFST GENMASK(31, 17)
1601 #define RTW89_H2C_BCN_UPD_BE_W3_MLIE_CSA_OFST GENMASK(15, 0)
1602 #define RTW89_H2C_BCN_UPD_BE_W3_CRITICAL_UPD_FLAG_OFST GENMASK(31, 16)
1603 #define RTW89_H2C_BCN_UPD_BE_W4_VAP1_DTIM_CNT_OFST GENMASK(15, 0)
1604 #define RTW89_H2C_BCN_UPD_BE_W4_VAP2_DTIM_CNT_OFST GENMASK(31, 16)
1605 #define RTW89_H2C_BCN_UPD_BE_W5_VAP3_DTIM_CNT_OFST GENMASK(15, 0)
1606 #define RTW89_H2C_BCN_UPD_BE_W5_VAP4_DTIM_CNT_OFST GENMASK(31, 16)
1607 #define RTW89_H2C_BCN_UPD_BE_W6_VAP5_DTIM_CNT_OFST GENMASK(15, 0)
1608 #define RTW89_H2C_BCN_UPD_BE_W6_VAP6_DTIM_CNT_OFST GENMASK(31, 16)
1609 #define RTW89_H2C_BCN_UPD_BE_W7_VAP7_DTIM_CNT_OFST GENMASK(15, 0)
1610 #define RTW89_H2C_BCN_UPD_BE_W7_ECSA_OFST GENMASK(30, 16)
1611 #define RTW89_H2C_BCN_UPD_BE_W7_PROTECTION_KEY_ID BIT(31)
1612
1613 struct rtw89_h2c_tbtt_tuning {
1614 __le32 w0;
1615 __le32 w1;
1616 } __packed;
1617
1618 #define RTW89_H2C_TBTT_TUNING_W0_BAND GENMASK(3, 0)
1619 #define RTW89_H2C_TBTT_TUNING_W0_PORT GENMASK(7, 4)
1620 #define RTW89_H2C_TBTT_TUNING_W1_SHIFT GENMASK(31, 0)
1621
1622 struct rtw89_h2c_pwr_lvl {
1623 __le32 w0;
1624 __le32 w1;
1625 } __packed;
1626
1627 #define RTW89_H2C_PWR_LVL_W0_MACID GENMASK(7, 0)
1628 #define RTW89_H2C_PWR_LVL_W0_BCN_TO_VAL GENMASK(15, 8)
1629 #define RTW89_H2C_PWR_LVL_W0_PS_LVL GENMASK(19, 16)
1630 #define RTW89_H2C_PWR_LVL_W0_TRX_LVL GENMASK(23, 20)
1631 #define RTW89_H2C_PWR_LVL_W0_BCN_TO_LVL GENMASK(27, 24)
1632 #define RTW89_H2C_PWR_LVL_W0_DTIM_TO_VAL GENMASK(31, 28)
1633 #define RTW89_H2C_PWR_LVL_W1_MACID_EXT GENMASK(7, 0)
1634
1635 struct rtw89_h2c_role_maintain {
1636 __le32 w0;
1637 };
1638
1639 #define RTW89_H2C_ROLE_MAINTAIN_W0_MACID GENMASK(7, 0)
1640 #define RTW89_H2C_ROLE_MAINTAIN_W0_SELF_ROLE GENMASK(9, 8)
1641 #define RTW89_H2C_ROLE_MAINTAIN_W0_UPD_MODE GENMASK(12, 10)
1642 #define RTW89_H2C_ROLE_MAINTAIN_W0_WIFI_ROLE GENMASK(16, 13)
1643 #define RTW89_H2C_ROLE_MAINTAIN_W0_BAND GENMASK(18, 17)
1644 #define RTW89_H2C_ROLE_MAINTAIN_W0_PORT GENMASK(21, 19)
1645 #define RTW89_H2C_ROLE_MAINTAIN_W0_MACID_EXT GENMASK(31, 24)
1646
1647 enum rtw89_fw_sta_type { /* value of RTW89_H2C_JOININFO_W1_STA_TYPE */
1648 RTW89_FW_N_AC_STA = 0,
1649 RTW89_FW_AX_STA = 1,
1650 RTW89_FW_BE_STA = 2,
1651 };
1652
1653 struct rtw89_h2c_join {
1654 __le32 w0;
1655 } __packed;
1656
1657 struct rtw89_h2c_join_v1 {
1658 __le32 w0;
1659 __le32 w1;
1660 __le32 w2;
1661 } __packed;
1662
1663 #define RTW89_H2C_JOININFO_W0_MACID GENMASK(7, 0)
1664 #define RTW89_H2C_JOININFO_W0_OP BIT(8)
1665 #define RTW89_H2C_JOININFO_W0_BAND BIT(9)
1666 #define RTW89_H2C_JOININFO_W0_WMM GENMASK(11, 10)
1667 #define RTW89_H2C_JOININFO_W0_TGR BIT(12)
1668 #define RTW89_H2C_JOININFO_W0_ISHESTA BIT(13)
1669 #define RTW89_H2C_JOININFO_W0_DLBW GENMASK(15, 14)
1670 #define RTW89_H2C_JOININFO_W0_TF_MAC_PAD GENMASK(17, 16)
1671 #define RTW89_H2C_JOININFO_W0_DL_T_PE GENMASK(20, 18)
1672 #define RTW89_H2C_JOININFO_W0_PORT_ID GENMASK(23, 21)
1673 #define RTW89_H2C_JOININFO_W0_NET_TYPE GENMASK(25, 24)
1674 #define RTW89_H2C_JOININFO_W0_WIFI_ROLE GENMASK(29, 26)
1675 #define RTW89_H2C_JOININFO_W0_SELF_ROLE GENMASK(31, 30)
1676 #define RTW89_H2C_JOININFO_W1_STA_TYPE GENMASK(2, 0)
1677 #define RTW89_H2C_JOININFO_W1_IS_MLD BIT(3)
1678 #define RTW89_H2C_JOININFO_W1_MAIN_MACID GENMASK(11, 4)
1679 #define RTW89_H2C_JOININFO_W1_MLO_MODE BIT(12)
1680 #define RTW89_H2C_JOININFO_MLO_MODE_MLMR 0
1681 #define RTW89_H2C_JOININFO_MLO_MODE_MLSR 1
1682 #define RTW89_H2C_JOININFO_W1_EMLSR_CAB BIT(13)
1683 #define RTW89_H2C_JOININFO_W1_NSTR_EN BIT(14)
1684 #define RTW89_H2C_JOININFO_W1_INIT_PWR_STATE BIT(15)
1685 #define RTW89_H2C_JOININFO_W1_EMLSR_PADDING GENMASK(18, 16)
1686 #define RTW89_H2C_JOININFO_W1_EMLSR_TRANS_DELAY GENMASK(21, 19)
1687 #define RTW89_H2C_JOININFO_W2_MACID_EXT GENMASK(7, 0)
1688 #define RTW89_H2C_JOININFO_W2_MAIN_MACID_EXT GENMASK(15, 8)
1689
1690 struct rtw89_h2c_notify_dbcc {
1691 __le32 w0;
1692 } __packed;
1693
1694 #define RTW89_H2C_NOTIFY_DBCC_EN BIT(0)
1695
SET_GENERAL_PKT_MACID(void * h2c,u32 val)1696 static inline void SET_GENERAL_PKT_MACID(void *h2c, u32 val)
1697 {
1698 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1699 }
1700
SET_GENERAL_PKT_PROBRSP_ID(void * h2c,u32 val)1701 static inline void SET_GENERAL_PKT_PROBRSP_ID(void *h2c, u32 val)
1702 {
1703 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1704 }
1705
SET_GENERAL_PKT_PSPOLL_ID(void * h2c,u32 val)1706 static inline void SET_GENERAL_PKT_PSPOLL_ID(void *h2c, u32 val)
1707 {
1708 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16));
1709 }
1710
SET_GENERAL_PKT_NULL_ID(void * h2c,u32 val)1711 static inline void SET_GENERAL_PKT_NULL_ID(void *h2c, u32 val)
1712 {
1713 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1714 }
1715
SET_GENERAL_PKT_QOS_NULL_ID(void * h2c,u32 val)1716 static inline void SET_GENERAL_PKT_QOS_NULL_ID(void *h2c, u32 val)
1717 {
1718 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0));
1719 }
1720
SET_GENERAL_PKT_CTS2SELF_ID(void * h2c,u32 val)1721 static inline void SET_GENERAL_PKT_CTS2SELF_ID(void *h2c, u32 val)
1722 {
1723 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8));
1724 }
1725
SET_LOG_CFG_LEVEL(void * h2c,u32 val)1726 static inline void SET_LOG_CFG_LEVEL(void *h2c, u32 val)
1727 {
1728 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1729 }
1730
SET_LOG_CFG_PATH(void * h2c,u32 val)1731 static inline void SET_LOG_CFG_PATH(void *h2c, u32 val)
1732 {
1733 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1734 }
1735
SET_LOG_CFG_COMP(void * h2c,u32 val)1736 static inline void SET_LOG_CFG_COMP(void *h2c, u32 val)
1737 {
1738 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(31, 0));
1739 }
1740
SET_LOG_CFG_COMP_EXT(void * h2c,u32 val)1741 static inline void SET_LOG_CFG_COMP_EXT(void *h2c, u32 val)
1742 {
1743 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(31, 0));
1744 }
1745
1746 struct rtw89_h2c_ba_cam {
1747 __le32 w0;
1748 __le32 w1;
1749 } __packed;
1750
1751 #define RTW89_H2C_BA_CAM_W0_VALID BIT(0)
1752 #define RTW89_H2C_BA_CAM_W0_INIT_REQ BIT(1)
1753 #define RTW89_H2C_BA_CAM_W0_ENTRY_IDX GENMASK(3, 2)
1754 #define RTW89_H2C_BA_CAM_W0_TID GENMASK(7, 4)
1755 #define RTW89_H2C_BA_CAM_W0_MACID GENMASK(15, 8)
1756 #define RTW89_H2C_BA_CAM_W0_BMAP_SIZE GENMASK(19, 16)
1757 #define RTW89_H2C_BA_CAM_W0_SSN GENMASK(31, 20)
1758 #define RTW89_H2C_BA_CAM_W1_UID GENMASK(7, 0)
1759 #define RTW89_H2C_BA_CAM_W1_STD_EN BIT(8)
1760 #define RTW89_H2C_BA_CAM_W1_BAND BIT(9)
1761 #define RTW89_H2C_BA_CAM_W1_ENTRY_IDX_V1 GENMASK(31, 28)
1762
1763 struct rtw89_h2c_ba_cam_v1 {
1764 __le32 w0;
1765 __le32 w1;
1766 } __packed;
1767
1768 #define RTW89_H2C_BA_CAM_V1_W0_VALID BIT(0)
1769 #define RTW89_H2C_BA_CAM_V1_W0_INIT_REQ BIT(1)
1770 #define RTW89_H2C_BA_CAM_V1_W0_TID_MASK GENMASK(7, 4)
1771 #define RTW89_H2C_BA_CAM_V1_W0_MACID_MASK GENMASK(15, 8)
1772 #define RTW89_H2C_BA_CAM_V1_W0_BMAP_SIZE_MASK GENMASK(19, 16)
1773 #define RTW89_H2C_BA_CAM_V1_W0_SSN_MASK GENMASK(31, 20)
1774 #define RTW89_H2C_BA_CAM_V1_W1_UID_VALUE_MASK GENMASK(7, 0)
1775 #define RTW89_H2C_BA_CAM_V1_W1_STD_ENTRY_EN BIT(8)
1776 #define RTW89_H2C_BA_CAM_V1_W1_BAND_SEL BIT(9)
1777 #define RTW89_H2C_BA_CAM_V1_W1_MLD_EN BIT(10)
1778 #define RTW89_H2C_BA_CAM_V1_W1_ENTRY_IDX_MASK GENMASK(31, 24)
1779
1780 struct rtw89_h2c_ba_cam_init {
1781 __le32 w0;
1782 } __packed;
1783
1784 #define RTW89_H2C_BA_CAM_INIT_USERS_MASK GENMASK(7, 0)
1785 #define RTW89_H2C_BA_CAM_INIT_OFFSET_MASK GENMASK(19, 12)
1786 #define RTW89_H2C_BA_CAM_INIT_BAND_SEL BIT(24)
1787
SET_LPS_PARM_MACID(void * h2c,u32 val)1788 static inline void SET_LPS_PARM_MACID(void *h2c, u32 val)
1789 {
1790 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1791 }
1792
SET_LPS_PARM_PSMODE(void * h2c,u32 val)1793 static inline void SET_LPS_PARM_PSMODE(void *h2c, u32 val)
1794 {
1795 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1796 }
1797
SET_LPS_PARM_RLBM(void * h2c,u32 val)1798 static inline void SET_LPS_PARM_RLBM(void *h2c, u32 val)
1799 {
1800 le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16));
1801 }
1802
SET_LPS_PARM_SMARTPS(void * h2c,u32 val)1803 static inline void SET_LPS_PARM_SMARTPS(void *h2c, u32 val)
1804 {
1805 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 20));
1806 }
1807
SET_LPS_PARM_AWAKEINTERVAL(void * h2c,u32 val)1808 static inline void SET_LPS_PARM_AWAKEINTERVAL(void *h2c, u32 val)
1809 {
1810 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1811 }
1812
SET_LPS_PARM_VOUAPSD(void * h2c,u32 val)1813 static inline void SET_LPS_PARM_VOUAPSD(void *h2c, u32 val)
1814 {
1815 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(0));
1816 }
1817
SET_LPS_PARM_VIUAPSD(void * h2c,u32 val)1818 static inline void SET_LPS_PARM_VIUAPSD(void *h2c, u32 val)
1819 {
1820 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(1));
1821 }
1822
SET_LPS_PARM_BEUAPSD(void * h2c,u32 val)1823 static inline void SET_LPS_PARM_BEUAPSD(void *h2c, u32 val)
1824 {
1825 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(2));
1826 }
1827
SET_LPS_PARM_BKUAPSD(void * h2c,u32 val)1828 static inline void SET_LPS_PARM_BKUAPSD(void *h2c, u32 val)
1829 {
1830 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(3));
1831 }
1832
SET_LPS_PARM_LASTRPWM(void * h2c,u32 val)1833 static inline void SET_LPS_PARM_LASTRPWM(void *h2c, u32 val)
1834 {
1835 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8));
1836 }
1837
1838 struct rtw89_h2c_lps_ch_info {
1839 struct {
1840 u8 pri_ch;
1841 u8 central_ch;
1842 u8 bw;
1843 u8 band;
1844 } __packed info[2];
1845
1846 __le32 mlo_dbcc_mode_lps;
1847 } __packed;
1848
1849 struct rtw89_h2c_lps_ml_cmn_info {
1850 u8 fmt_id;
1851 u8 rfe_type;
1852 u8 rsvd0[2];
1853 __le32 mlo_dbcc_mode;
1854 u8 central_ch[RTW89_PHY_NUM];
1855 u8 pri_ch[RTW89_PHY_NUM];
1856 u8 bw[RTW89_PHY_NUM];
1857 u8 band[RTW89_PHY_NUM];
1858 u8 bcn_rate_type[RTW89_PHY_NUM];
1859 u8 rsvd1[2];
1860 __le16 tia_gain[RTW89_PHY_NUM][TIA_GAIN_NUM];
1861 u8 lna_gain[RTW89_PHY_NUM][LNA_GAIN_NUM];
1862 u8 rsvd2[2];
1863 u8 tia_lna_op1db[RTW89_PHY_NUM][LNA_GAIN_NUM + 1];
1864 u8 lna_op1db[RTW89_PHY_NUM][LNA_GAIN_NUM];
1865 u8 dup_bcn_ofst[RTW89_PHY_NUM];
1866 } __packed;
1867
1868 struct rtw89_h2c_trig_cpu_except {
1869 __le32 w0;
1870 } __packed;
1871
1872 #define RTW89_H2C_CPU_EXCEPTION_TYPE GENMASK(31, 0)
1873
RTW89_SET_FWCMD_PKT_DROP_SEL(void * cmd,u32 val)1874 static inline void RTW89_SET_FWCMD_PKT_DROP_SEL(void *cmd, u32 val)
1875 {
1876 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
1877 }
1878
RTW89_SET_FWCMD_PKT_DROP_MACID(void * cmd,u32 val)1879 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID(void *cmd, u32 val)
1880 {
1881 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
1882 }
1883
RTW89_SET_FWCMD_PKT_DROP_BAND(void * cmd,u32 val)1884 static inline void RTW89_SET_FWCMD_PKT_DROP_BAND(void *cmd, u32 val)
1885 {
1886 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
1887 }
1888
RTW89_SET_FWCMD_PKT_DROP_PORT(void * cmd,u32 val)1889 static inline void RTW89_SET_FWCMD_PKT_DROP_PORT(void *cmd, u32 val)
1890 {
1891 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
1892 }
1893
RTW89_SET_FWCMD_PKT_DROP_MBSSID(void * cmd,u32 val)1894 static inline void RTW89_SET_FWCMD_PKT_DROP_MBSSID(void *cmd, u32 val)
1895 {
1896 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(7, 0));
1897 }
1898
RTW89_SET_FWCMD_PKT_DROP_ROLE_A_INFO_TF_TRS(void * cmd,u32 val)1899 static inline void RTW89_SET_FWCMD_PKT_DROP_ROLE_A_INFO_TF_TRS(void *cmd, u32 val)
1900 {
1901 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(15, 8));
1902 }
1903
RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_0(void * cmd,u32 val)1904 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_0(void *cmd, u32 val)
1905 {
1906 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
1907 }
1908
RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_1(void * cmd,u32 val)1909 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_1(void *cmd, u32 val)
1910 {
1911 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(31, 0));
1912 }
1913
RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_2(void * cmd,u32 val)1914 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_2(void *cmd, u32 val)
1915 {
1916 le32p_replace_bits((__le32 *)cmd + 4, val, GENMASK(31, 0));
1917 }
1918
RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_3(void * cmd,u32 val)1919 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_3(void *cmd, u32 val)
1920 {
1921 le32p_replace_bits((__le32 *)cmd + 5, val, GENMASK(31, 0));
1922 }
1923
RTW89_SET_KEEP_ALIVE_ENABLE(void * h2c,u32 val)1924 static inline void RTW89_SET_KEEP_ALIVE_ENABLE(void *h2c, u32 val)
1925 {
1926 le32p_replace_bits((__le32 *)h2c, val, GENMASK(1, 0));
1927 }
1928
RTW89_SET_KEEP_ALIVE_PKT_NULL_ID(void * h2c,u32 val)1929 static inline void RTW89_SET_KEEP_ALIVE_PKT_NULL_ID(void *h2c, u32 val)
1930 {
1931 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1932 }
1933
RTW89_SET_KEEP_ALIVE_PERIOD(void * h2c,u32 val)1934 static inline void RTW89_SET_KEEP_ALIVE_PERIOD(void *h2c, u32 val)
1935 {
1936 le32p_replace_bits((__le32 *)h2c, val, GENMASK(24, 16));
1937 }
1938
RTW89_SET_KEEP_ALIVE_MACID(void * h2c,u32 val)1939 static inline void RTW89_SET_KEEP_ALIVE_MACID(void *h2c, u32 val)
1940 {
1941 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1942 }
1943
RTW89_SET_DISCONNECT_DETECT_ENABLE(void * h2c,u32 val)1944 static inline void RTW89_SET_DISCONNECT_DETECT_ENABLE(void *h2c, u32 val)
1945 {
1946 le32p_replace_bits((__le32 *)h2c, val, BIT(0));
1947 }
1948
RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_EN(void * h2c,u32 val)1949 static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_EN(void *h2c, u32 val)
1950 {
1951 le32p_replace_bits((__le32 *)h2c, val, BIT(1));
1952 }
1953
RTW89_SET_DISCONNECT_DETECT_DISCONNECT(void * h2c,u32 val)1954 static inline void RTW89_SET_DISCONNECT_DETECT_DISCONNECT(void *h2c, u32 val)
1955 {
1956 le32p_replace_bits((__le32 *)h2c, val, BIT(2));
1957 }
1958
RTW89_SET_DISCONNECT_DETECT_MAC_ID(void * h2c,u32 val)1959 static inline void RTW89_SET_DISCONNECT_DETECT_MAC_ID(void *h2c, u32 val)
1960 {
1961 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1962 }
1963
RTW89_SET_DISCONNECT_DETECT_CHECK_PERIOD(void * h2c,u32 val)1964 static inline void RTW89_SET_DISCONNECT_DETECT_CHECK_PERIOD(void *h2c, u32 val)
1965 {
1966 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16));
1967 }
1968
RTW89_SET_DISCONNECT_DETECT_TRY_PKT_COUNT(void * h2c,u32 val)1969 static inline void RTW89_SET_DISCONNECT_DETECT_TRY_PKT_COUNT(void *h2c, u32 val)
1970 {
1971 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1972 }
1973
RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_LIMIT(void * h2c,u32 val)1974 static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_LIMIT(void *h2c, u32 val)
1975 {
1976 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0));
1977 }
1978
1979 struct rtw89_h2c_wow_global {
1980 __le32 w0;
1981 struct rtw89_wow_key_info key_info;
1982 } __packed;
1983
1984 #define RTW89_H2C_WOW_GLOBAL_W0_ENABLE BIT(0)
1985 #define RTW89_H2C_WOW_GLOBAL_W0_DROP_ALL_PKT BIT(1)
1986 #define RTW89_H2C_WOW_GLOBAL_W0_RX_PARSE_AFTER_WAKE BIT(2)
1987 #define RTW89_H2C_WOW_GLOBAL_W0_WAKE_BAR_PULLED BIT(3)
1988 #define RTW89_H2C_WOW_GLOBAL_W0_MAC_ID GENMASK(15, 8)
1989 #define RTW89_H2C_WOW_GLOBAL_W0_PAIRWISE_SEC_ALGO GENMASK(23, 16)
1990 #define RTW89_H2C_WOW_GLOBAL_W0_GROUP_SEC_ALGO GENMASK(31, 24)
1991
1992 #define RTW89_MAX_SUPPORT_NL_NUM 16
1993 struct rtw89_h2c_cfg_nlo {
1994 __le32 w0;
1995 u8 nlo_cnt;
1996 u8 rsvd[3];
1997 __le32 patterncheck;
1998 __le32 rsvd1;
1999 __le32 rsvd2;
2000 u8 ssid_len[RTW89_MAX_SUPPORT_NL_NUM];
2001 u8 chiper[RTW89_MAX_SUPPORT_NL_NUM];
2002 u8 rsvd3[24];
2003 u8 ssid[RTW89_MAX_SUPPORT_NL_NUM][IEEE80211_MAX_SSID_LEN];
2004 } __packed;
2005
2006 #define RTW89_H2C_NLO_W0_ENABLE BIT(0)
2007 #define RTW89_H2C_NLO_W0_IGNORE_CIPHER BIT(2)
2008 #define RTW89_H2C_NLO_W0_MACID GENMASK(31, 24)
2009
RTW89_SET_WOW_WAKEUP_CTRL_PATTERN_MATCH_ENABLE(void * h2c,u32 val)2010 static inline void RTW89_SET_WOW_WAKEUP_CTRL_PATTERN_MATCH_ENABLE(void *h2c, u32 val)
2011 {
2012 le32p_replace_bits((__le32 *)h2c, val, BIT(0));
2013 }
2014
RTW89_SET_WOW_WAKEUP_CTRL_MAGIC_ENABLE(void * h2c,u32 val)2015 static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAGIC_ENABLE(void *h2c, u32 val)
2016 {
2017 le32p_replace_bits((__le32 *)h2c, val, BIT(1));
2018 }
2019
RTW89_SET_WOW_WAKEUP_CTRL_HW_UNICAST_ENABLE(void * h2c,u32 val)2020 static inline void RTW89_SET_WOW_WAKEUP_CTRL_HW_UNICAST_ENABLE(void *h2c, u32 val)
2021 {
2022 le32p_replace_bits((__le32 *)h2c, val, BIT(2));
2023 }
2024
RTW89_SET_WOW_WAKEUP_CTRL_FW_UNICAST_ENABLE(void * h2c,u32 val)2025 static inline void RTW89_SET_WOW_WAKEUP_CTRL_FW_UNICAST_ENABLE(void *h2c, u32 val)
2026 {
2027 le32p_replace_bits((__le32 *)h2c, val, BIT(3));
2028 }
2029
RTW89_SET_WOW_WAKEUP_CTRL_DEAUTH_ENABLE(void * h2c,u32 val)2030 static inline void RTW89_SET_WOW_WAKEUP_CTRL_DEAUTH_ENABLE(void *h2c, u32 val)
2031 {
2032 le32p_replace_bits((__le32 *)h2c, val, BIT(4));
2033 }
2034
RTW89_SET_WOW_WAKEUP_CTRL_REKEYP_ENABLE(void * h2c,u32 val)2035 static inline void RTW89_SET_WOW_WAKEUP_CTRL_REKEYP_ENABLE(void *h2c, u32 val)
2036 {
2037 le32p_replace_bits((__le32 *)h2c, val, BIT(5));
2038 }
2039
RTW89_SET_WOW_WAKEUP_CTRL_EAP_ENABLE(void * h2c,u32 val)2040 static inline void RTW89_SET_WOW_WAKEUP_CTRL_EAP_ENABLE(void *h2c, u32 val)
2041 {
2042 le32p_replace_bits((__le32 *)h2c, val, BIT(6));
2043 }
2044
RTW89_SET_WOW_WAKEUP_CTRL_ALL_DATA_ENABLE(void * h2c,u32 val)2045 static inline void RTW89_SET_WOW_WAKEUP_CTRL_ALL_DATA_ENABLE(void *h2c, u32 val)
2046 {
2047 le32p_replace_bits((__le32 *)h2c, val, BIT(7));
2048 }
2049
RTW89_SET_WOW_WAKEUP_CTRL_MAC_ID(void * h2c,u32 val)2050 static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAC_ID(void *h2c, u32 val)
2051 {
2052 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
2053 }
2054
RTW89_SET_WOW_CAM_UPD_R_W(void * h2c,u32 val)2055 static inline void RTW89_SET_WOW_CAM_UPD_R_W(void *h2c, u32 val)
2056 {
2057 le32p_replace_bits((__le32 *)h2c, val, BIT(0));
2058 }
2059
RTW89_SET_WOW_CAM_UPD_IDX(void * h2c,u32 val)2060 static inline void RTW89_SET_WOW_CAM_UPD_IDX(void *h2c, u32 val)
2061 {
2062 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 1));
2063 }
2064
RTW89_SET_WOW_CAM_UPD_WKFM1(void * h2c,u32 val)2065 static inline void RTW89_SET_WOW_CAM_UPD_WKFM1(void *h2c, u32 val)
2066 {
2067 le32p_replace_bits((__le32 *)h2c + 1, val, GENMASK(31, 0));
2068 }
2069
RTW89_SET_WOW_CAM_UPD_WKFM2(void * h2c,u32 val)2070 static inline void RTW89_SET_WOW_CAM_UPD_WKFM2(void *h2c, u32 val)
2071 {
2072 le32p_replace_bits((__le32 *)h2c + 2, val, GENMASK(31, 0));
2073 }
2074
RTW89_SET_WOW_CAM_UPD_WKFM3(void * h2c,u32 val)2075 static inline void RTW89_SET_WOW_CAM_UPD_WKFM3(void *h2c, u32 val)
2076 {
2077 le32p_replace_bits((__le32 *)h2c + 3, val, GENMASK(31, 0));
2078 }
2079
RTW89_SET_WOW_CAM_UPD_WKFM4(void * h2c,u32 val)2080 static inline void RTW89_SET_WOW_CAM_UPD_WKFM4(void *h2c, u32 val)
2081 {
2082 le32p_replace_bits((__le32 *)h2c + 4, val, GENMASK(31, 0));
2083 }
2084
RTW89_SET_WOW_CAM_UPD_CRC(void * h2c,u32 val)2085 static inline void RTW89_SET_WOW_CAM_UPD_CRC(void *h2c, u32 val)
2086 {
2087 le32p_replace_bits((__le32 *)h2c + 5, val, GENMASK(15, 0));
2088 }
2089
RTW89_SET_WOW_CAM_UPD_NEGATIVE_PATTERN_MATCH(void * h2c,u32 val)2090 static inline void RTW89_SET_WOW_CAM_UPD_NEGATIVE_PATTERN_MATCH(void *h2c, u32 val)
2091 {
2092 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(22));
2093 }
2094
RTW89_SET_WOW_CAM_UPD_SKIP_MAC_HDR(void * h2c,u32 val)2095 static inline void RTW89_SET_WOW_CAM_UPD_SKIP_MAC_HDR(void *h2c, u32 val)
2096 {
2097 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(23));
2098 }
2099
RTW89_SET_WOW_CAM_UPD_UC(void * h2c,u32 val)2100 static inline void RTW89_SET_WOW_CAM_UPD_UC(void *h2c, u32 val)
2101 {
2102 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(24));
2103 }
2104
RTW89_SET_WOW_CAM_UPD_MC(void * h2c,u32 val)2105 static inline void RTW89_SET_WOW_CAM_UPD_MC(void *h2c, u32 val)
2106 {
2107 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(25));
2108 }
2109
RTW89_SET_WOW_CAM_UPD_BC(void * h2c,u32 val)2110 static inline void RTW89_SET_WOW_CAM_UPD_BC(void *h2c, u32 val)
2111 {
2112 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(26));
2113 }
2114
RTW89_SET_WOW_CAM_UPD_VALID(void * h2c,u32 val)2115 static inline void RTW89_SET_WOW_CAM_UPD_VALID(void *h2c, u32 val)
2116 {
2117 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(31));
2118 }
2119
2120 struct rtw89_h2c_wow_gtk_ofld {
2121 __le32 w0;
2122 __le32 w1;
2123 struct rtw89_wow_gtk_info gtk_info;
2124 } __packed;
2125
2126 #define RTW89_H2C_WOW_GTK_OFLD_W0_EN BIT(0)
2127 #define RTW89_H2C_WOW_GTK_OFLD_W0_TKIP_EN BIT(1)
2128 #define RTW89_H2C_WOW_GTK_OFLD_W0_IEEE80211W_EN BIT(2)
2129 #define RTW89_H2C_WOW_GTK_OFLD_W0_PAIRWISE_WAKEUP BIT(3)
2130 #define RTW89_H2C_WOW_GTK_OFLD_W0_NOREKEY_WAKEUP BIT(4)
2131 #define RTW89_H2C_WOW_GTK_OFLD_W0_MAC_ID GENMASK(23, 16)
2132 #define RTW89_H2C_WOW_GTK_OFLD_W0_GTK_RSP_ID GENMASK(31, 24)
2133 #define RTW89_H2C_WOW_GTK_OFLD_W1_PMF_SA_QUERY_ID GENMASK(7, 0)
2134 #define RTW89_H2C_WOW_GTK_OFLD_W1_PMF_BIP_SEC_ALGO GENMASK(9, 8)
2135 #define RTW89_H2C_WOW_GTK_OFLD_W1_ALGO_AKM_SUIT GENMASK(17, 10)
2136
2137 struct rtw89_h2c_arp_offload {
2138 __le32 w0;
2139 __le32 w1;
2140 } __packed;
2141
2142 #define RTW89_H2C_ARP_OFFLOAD_W0_ENABLE BIT(0)
2143 #define RTW89_H2C_ARP_OFFLOAD_W0_ACTION BIT(1)
2144 #define RTW89_H2C_ARP_OFFLOAD_W0_MACID GENMASK(23, 16)
2145 #define RTW89_H2C_ARP_OFFLOAD_W0_PKT_ID GENMASK(31, 24)
2146 #define RTW89_H2C_ARP_OFFLOAD_W1_CONTENT GENMASK(31, 0)
2147
2148 enum rtw89_btc_btf_h2c_class {
2149 BTFC_SET = 0x10,
2150 BTFC_GET = 0x11,
2151 BTFC_FW_EVENT = 0x12,
2152 };
2153
2154 enum rtw89_btc_btf_set {
2155 SET_REPORT_EN = 0x0,
2156 SET_SLOT_TABLE,
2157 SET_MREG_TABLE,
2158 SET_CX_POLICY,
2159 SET_GPIO_DBG,
2160 SET_DRV_INFO,
2161 SET_DRV_EVENT,
2162 SET_BT_WREG_ADDR,
2163 SET_BT_WREG_VAL,
2164 SET_BT_RREG_ADDR,
2165 SET_BT_WL_CH_INFO,
2166 SET_BT_INFO_REPORT,
2167 SET_BT_IGNORE_WLAN_ACT,
2168 SET_BT_TX_PWR,
2169 SET_BT_LNA_CONSTRAIN,
2170 SET_BT_QUERY_DEV_LIST,
2171 SET_BT_QUERY_DEV_INFO,
2172 SET_BT_PSD_REPORT,
2173 SET_H2C_TEST,
2174 SET_IOFLD_RF,
2175 SET_IOFLD_BB,
2176 SET_IOFLD_MAC,
2177 SET_IOFLD_SCBD,
2178 SET_H2C_MACRO,
2179 SET_MAX1,
2180 };
2181
2182 enum rtw89_btc_cxdrvinfo {
2183 CXDRVINFO_INIT = 0,
2184 CXDRVINFO_ROLE,
2185 CXDRVINFO_DBCC,
2186 CXDRVINFO_SMAP,
2187 CXDRVINFO_RFK,
2188 CXDRVINFO_RUN,
2189 CXDRVINFO_CTRL,
2190 CXDRVINFO_SCAN,
2191 CXDRVINFO_TRX, /* WL traffic to WL fw */
2192 CXDRVINFO_TXPWR,
2193 CXDRVINFO_FDDT,
2194 CXDRVINFO_MLO,
2195 CXDRVINFO_OSI,
2196 CXDRVINFO_MAX,
2197 };
2198
2199 enum rtw89_scan_mode {
2200 RTW89_SCAN_IMMEDIATE,
2201 RTW89_SCAN_DELAY,
2202 };
2203
2204 enum rtw89_scan_type {
2205 RTW89_SCAN_ONCE,
2206 RTW89_SCAN_NORMAL,
2207 RTW89_SCAN_NORMAL_SLOW,
2208 RTW89_SCAN_SEAMLESS,
2209 RTW89_SCAN_MAX,
2210 };
2211
RTW89_SET_FWCMD_CXHDR_TYPE(void * cmd,u8 val)2212 static inline void RTW89_SET_FWCMD_CXHDR_TYPE(void *cmd, u8 val)
2213 {
2214 u8p_replace_bits((u8 *)(cmd) + 0, val, GENMASK(7, 0));
2215 }
2216
RTW89_SET_FWCMD_CXHDR_LEN(void * cmd,u8 val)2217 static inline void RTW89_SET_FWCMD_CXHDR_LEN(void *cmd, u8 val)
2218 {
2219 u8p_replace_bits((u8 *)(cmd) + 1, val, GENMASK(7, 0));
2220 }
2221
2222 struct rtw89_h2c_cxhdr {
2223 u8 type;
2224 u8 len;
2225 } __packed;
2226
2227 struct rtw89_h2c_cxhdr_v7 {
2228 u8 type;
2229 u8 ver;
2230 u8 len;
2231 } __packed;
2232
2233 struct rtw89_h2c_cxctrl_v7 {
2234 struct rtw89_h2c_cxhdr_v7 hdr;
2235 struct rtw89_btc_ctrl_v7 ctrl;
2236 } __packed;
2237
2238 #define H2C_LEN_CXDRVHDR sizeof(struct rtw89_h2c_cxhdr)
2239 #define H2C_LEN_CXDRVHDR_V7 sizeof(struct rtw89_h2c_cxhdr_v7)
2240
2241 struct rtw89_btc_wl_role_info_v7_u8 {
2242 u8 connect_cnt;
2243 u8 link_mode;
2244 u8 link_mode_chg;
2245 u8 p2p_2g;
2246
2247 struct rtw89_btc_wl_active_role_v7 active_role[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER];
2248 } __packed;
2249
2250 struct rtw89_btc_wl_role_info_v7_u32 {
2251 __le32 role_map;
2252 __le32 mrole_type;
2253 __le32 mrole_noa_duration;
2254 __le32 dbcc_en;
2255 __le32 dbcc_chg;
2256 __le32 dbcc_2g_phy;
2257 } __packed;
2258
2259 struct rtw89_h2c_cxrole_v7 {
2260 struct rtw89_h2c_cxhdr_v7 hdr;
2261 struct rtw89_btc_wl_role_info_v7_u8 _u8;
2262 struct rtw89_btc_wl_role_info_v7_u32 _u32;
2263 } __packed;
2264
2265 struct rtw89_btc_wl_role_info_v8_u8 {
2266 u8 connect_cnt;
2267 u8 link_mode;
2268 u8 link_mode_chg;
2269 u8 p2p_2g;
2270
2271 u8 pta_req_band;
2272 u8 dbcc_en;
2273 u8 dbcc_chg;
2274 u8 dbcc_2g_phy;
2275
2276 struct rtw89_btc_wl_rlink rlink[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM];
2277 } __packed;
2278
2279 struct rtw89_btc_wl_role_info_v8_u32 {
2280 __le32 role_map;
2281 __le32 mrole_type;
2282 __le32 mrole_noa_duration;
2283 } __packed;
2284
2285 struct rtw89_h2c_cxrole_v8 {
2286 struct rtw89_h2c_cxhdr_v7 hdr;
2287 struct rtw89_btc_wl_role_info_v8_u8 _u8;
2288 struct rtw89_btc_wl_role_info_v8_u32 _u32;
2289 } __packed;
2290
2291 struct rtw89_h2c_cxosi {
2292 struct rtw89_h2c_cxhdr_v7 hdr;
2293 struct rtw89_btc_fbtc_outsrc_set_info osi;
2294 } __packed;
2295
2296 struct rtw89_h2c_cxinit {
2297 struct rtw89_h2c_cxhdr hdr;
2298 u8 ant_type;
2299 u8 ant_num;
2300 u8 ant_iso;
2301 u8 ant_info;
2302 u8 mod_rfe;
2303 u8 mod_cv;
2304 u8 mod_info;
2305 u8 mod_adie_kt;
2306 u8 wl_gch;
2307 u8 info;
2308 u8 rsvd;
2309 u8 rsvd1;
2310 } __packed;
2311
2312 #define RTW89_H2C_CXINIT_ANT_INFO_POS BIT(0)
2313 #define RTW89_H2C_CXINIT_ANT_INFO_DIVERSITY BIT(1)
2314 #define RTW89_H2C_CXINIT_ANT_INFO_BTG_POS GENMASK(3, 2)
2315 #define RTW89_H2C_CXINIT_ANT_INFO_STREAM_CNT GENMASK(7, 4)
2316
2317 #define RTW89_H2C_CXINIT_MOD_INFO_BT_SOLO BIT(0)
2318 #define RTW89_H2C_CXINIT_MOD_INFO_BT_POS BIT(1)
2319 #define RTW89_H2C_CXINIT_MOD_INFO_SW_TYPE BIT(2)
2320 #define RTW89_H2C_CXINIT_MOD_INFO_WA_TYPE GENMASK(5, 3)
2321
2322 #define RTW89_H2C_CXINIT_INFO_WL_ONLY BIT(0)
2323 #define RTW89_H2C_CXINIT_INFO_WL_INITOK BIT(1)
2324 #define RTW89_H2C_CXINIT_INFO_DBCC_EN BIT(2)
2325 #define RTW89_H2C_CXINIT_INFO_CX_OTHER BIT(3)
2326 #define RTW89_H2C_CXINIT_INFO_BT_ONLY BIT(4)
2327
2328 struct rtw89_h2c_cxinit_v7 {
2329 struct rtw89_h2c_cxhdr_v7 hdr;
2330 struct rtw89_btc_init_info_v7 init;
2331 } __packed;
2332
RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(void * cmd,u8 val)2333 static inline void RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(void *cmd, u8 val)
2334 {
2335 u8p_replace_bits((u8 *)(cmd) + 2, val, GENMASK(7, 0));
2336 }
2337
RTW89_SET_FWCMD_CXROLE_LINK_MODE(void * cmd,u8 val)2338 static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE(void *cmd, u8 val)
2339 {
2340 u8p_replace_bits((u8 *)(cmd) + 3, val, GENMASK(7, 0));
2341 }
2342
RTW89_SET_FWCMD_CXROLE_ROLE_NONE(void * cmd,u16 val)2343 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NONE(void *cmd, u16 val)
2344 {
2345 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(0));
2346 }
2347
RTW89_SET_FWCMD_CXROLE_ROLE_STA(void * cmd,u16 val)2348 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_STA(void *cmd, u16 val)
2349 {
2350 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(1));
2351 }
2352
RTW89_SET_FWCMD_CXROLE_ROLE_AP(void * cmd,u16 val)2353 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_AP(void *cmd, u16 val)
2354 {
2355 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(2));
2356 }
2357
RTW89_SET_FWCMD_CXROLE_ROLE_VAP(void * cmd,u16 val)2358 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_VAP(void *cmd, u16 val)
2359 {
2360 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(3));
2361 }
2362
RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(void * cmd,u16 val)2363 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(void *cmd, u16 val)
2364 {
2365 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(4));
2366 }
2367
RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(void * cmd,u16 val)2368 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(void *cmd, u16 val)
2369 {
2370 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(5));
2371 }
2372
RTW89_SET_FWCMD_CXROLE_ROLE_MESH(void * cmd,u16 val)2373 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MESH(void *cmd, u16 val)
2374 {
2375 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(6));
2376 }
2377
RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(void * cmd,u16 val)2378 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(void *cmd, u16 val)
2379 {
2380 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(7));
2381 }
2382
RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(void * cmd,u16 val)2383 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(void *cmd, u16 val)
2384 {
2385 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(8));
2386 }
2387
RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(void * cmd,u16 val)2388 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(void *cmd, u16 val)
2389 {
2390 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(9));
2391 }
2392
RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(void * cmd,u16 val)2393 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(void *cmd, u16 val)
2394 {
2395 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(10));
2396 }
2397
RTW89_SET_FWCMD_CXROLE_ROLE_NAN(void * cmd,u16 val)2398 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NAN(void *cmd, u16 val)
2399 {
2400 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(11));
2401 }
2402
RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(void * cmd,u8 val,int n,u8 offset)2403 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(void *cmd, u8 val, int n, u8 offset)
2404 {
2405 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0));
2406 }
2407
RTW89_SET_FWCMD_CXROLE_ACT_PID(void * cmd,u8 val,int n,u8 offset)2408 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PID(void *cmd, u8 val, int n, u8 offset)
2409 {
2410 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(3, 1));
2411 }
2412
RTW89_SET_FWCMD_CXROLE_ACT_PHY(void * cmd,u8 val,int n,u8 offset)2413 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PHY(void *cmd, u8 val, int n, u8 offset)
2414 {
2415 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4));
2416 }
2417
RTW89_SET_FWCMD_CXROLE_ACT_NOA(void * cmd,u8 val,int n,u8 offset)2418 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA(void *cmd, u8 val, int n, u8 offset)
2419 {
2420 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5));
2421 }
2422
RTW89_SET_FWCMD_CXROLE_ACT_BAND(void * cmd,u8 val,int n,u8 offset)2423 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BAND(void *cmd, u8 val, int n, u8 offset)
2424 {
2425 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(7, 6));
2426 }
2427
RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(void * cmd,u8 val,int n,u8 offset)2428 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(void *cmd, u8 val, int n, u8 offset)
2429 {
2430 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0));
2431 }
2432
RTW89_SET_FWCMD_CXROLE_ACT_BW(void * cmd,u8 val,int n,u8 offset)2433 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BW(void *cmd, u8 val, int n, u8 offset)
2434 {
2435 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, GENMASK(7, 1));
2436 }
2437
RTW89_SET_FWCMD_CXROLE_ACT_ROLE(void * cmd,u8 val,int n,u8 offset)2438 static inline void RTW89_SET_FWCMD_CXROLE_ACT_ROLE(void *cmd, u8 val, int n, u8 offset)
2439 {
2440 u8p_replace_bits((u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0));
2441 }
2442
RTW89_SET_FWCMD_CXROLE_ACT_CH(void * cmd,u8 val,int n,u8 offset)2443 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CH(void *cmd, u8 val, int n, u8 offset)
2444 {
2445 u8p_replace_bits((u8 *)cmd + (9 + (12 + offset) * n), val, GENMASK(7, 0));
2446 }
2447
RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(void * cmd,u16 val,int n,u8 offset)2448 static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(void *cmd, u16 val, int n, u8 offset)
2449 {
2450 le16p_replace_bits((__le16 *)((u8 *)cmd + (10 + (12 + offset) * n)), val, GENMASK(15, 0));
2451 }
2452
RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(void * cmd,u16 val,int n,u8 offset)2453 static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(void *cmd, u16 val, int n, u8 offset)
2454 {
2455 le16p_replace_bits((__le16 *)((u8 *)cmd + (12 + (12 + offset) * n)), val, GENMASK(15, 0));
2456 }
2457
RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(void * cmd,u16 val,int n,u8 offset)2458 static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(void *cmd, u16 val, int n, u8 offset)
2459 {
2460 le16p_replace_bits((__le16 *)((u8 *)cmd + (14 + (12 + offset) * n)), val, GENMASK(15, 0));
2461 }
2462
RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(void * cmd,u16 val,int n,u8 offset)2463 static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(void *cmd, u16 val, int n, u8 offset)
2464 {
2465 le16p_replace_bits((__le16 *)((u8 *)cmd + (16 + (12 + offset) * n)), val, GENMASK(15, 0));
2466 }
2467
RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR(void * cmd,u32 val,int n,u8 offset)2468 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR(void *cmd, u32 val, int n, u8 offset)
2469 {
2470 le32p_replace_bits((__le32 *)((u8 *)cmd + (20 + (12 + offset) * n)), val, GENMASK(31, 0));
2471 }
2472
RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED_V2(void * cmd,u8 val,int n,u8 offset)2473 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED_V2(void *cmd, u8 val, int n, u8 offset)
2474 {
2475 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0));
2476 }
2477
RTW89_SET_FWCMD_CXROLE_ACT_PID_V2(void * cmd,u8 val,int n,u8 offset)2478 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PID_V2(void *cmd, u8 val, int n, u8 offset)
2479 {
2480 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(3, 1));
2481 }
2482
RTW89_SET_FWCMD_CXROLE_ACT_PHY_V2(void * cmd,u8 val,int n,u8 offset)2483 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PHY_V2(void *cmd, u8 val, int n, u8 offset)
2484 {
2485 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4));
2486 }
2487
RTW89_SET_FWCMD_CXROLE_ACT_NOA_V2(void * cmd,u8 val,int n,u8 offset)2488 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_V2(void *cmd, u8 val, int n, u8 offset)
2489 {
2490 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5));
2491 }
2492
RTW89_SET_FWCMD_CXROLE_ACT_BAND_V2(void * cmd,u8 val,int n,u8 offset)2493 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BAND_V2(void *cmd, u8 val, int n, u8 offset)
2494 {
2495 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(7, 6));
2496 }
2497
RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS_V2(void * cmd,u8 val,int n,u8 offset)2498 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS_V2(void *cmd, u8 val, int n, u8 offset)
2499 {
2500 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0));
2501 }
2502
RTW89_SET_FWCMD_CXROLE_ACT_BW_V2(void * cmd,u8 val,int n,u8 offset)2503 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BW_V2(void *cmd, u8 val, int n, u8 offset)
2504 {
2505 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, GENMASK(7, 1));
2506 }
2507
RTW89_SET_FWCMD_CXROLE_ACT_ROLE_V2(void * cmd,u8 val,int n,u8 offset)2508 static inline void RTW89_SET_FWCMD_CXROLE_ACT_ROLE_V2(void *cmd, u8 val, int n, u8 offset)
2509 {
2510 u8p_replace_bits((u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0));
2511 }
2512
RTW89_SET_FWCMD_CXROLE_ACT_CH_V2(void * cmd,u8 val,int n,u8 offset)2513 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CH_V2(void *cmd, u8 val, int n, u8 offset)
2514 {
2515 u8p_replace_bits((u8 *)cmd + (9 + (12 + offset) * n), val, GENMASK(7, 0));
2516 }
2517
RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR_V2(void * cmd,u32 val,int n,u8 offset)2518 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR_V2(void *cmd, u32 val, int n, u8 offset)
2519 {
2520 le32p_replace_bits((__le32 *)((u8 *)cmd + (10 + (12 + offset) * n)), val, GENMASK(31, 0));
2521 }
2522
RTW89_SET_FWCMD_CXROLE_MROLE_TYPE(void * cmd,u32 val,u8 offset)2523 static inline void RTW89_SET_FWCMD_CXROLE_MROLE_TYPE(void *cmd, u32 val, u8 offset)
2524 {
2525 le32p_replace_bits((__le32 *)((u8 *)cmd + offset), val, GENMASK(31, 0));
2526 }
2527
RTW89_SET_FWCMD_CXROLE_MROLE_NOA(void * cmd,u32 val,u8 offset)2528 static inline void RTW89_SET_FWCMD_CXROLE_MROLE_NOA(void *cmd, u32 val, u8 offset)
2529 {
2530 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 4), val, GENMASK(31, 0));
2531 }
2532
RTW89_SET_FWCMD_CXROLE_DBCC_EN(void * cmd,u32 val,u8 offset)2533 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_EN(void *cmd, u32 val, u8 offset)
2534 {
2535 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(0));
2536 }
2537
RTW89_SET_FWCMD_CXROLE_DBCC_CHG(void * cmd,u32 val,u8 offset)2538 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_CHG(void *cmd, u32 val, u8 offset)
2539 {
2540 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(1));
2541 }
2542
RTW89_SET_FWCMD_CXROLE_DBCC_2G_PHY(void * cmd,u32 val,u8 offset)2543 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_2G_PHY(void *cmd, u32 val, u8 offset)
2544 {
2545 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, GENMASK(3, 2));
2546 }
2547
RTW89_SET_FWCMD_CXROLE_LINK_MODE_CHG(void * cmd,u32 val,u8 offset)2548 static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE_CHG(void *cmd, u32 val, u8 offset)
2549 {
2550 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(4));
2551 }
2552
RTW89_SET_FWCMD_CXCTRL_MANUAL(void * cmd,u32 val)2553 static inline void RTW89_SET_FWCMD_CXCTRL_MANUAL(void *cmd, u32 val)
2554 {
2555 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(0));
2556 }
2557
RTW89_SET_FWCMD_CXCTRL_IGNORE_BT(void * cmd,u32 val)2558 static inline void RTW89_SET_FWCMD_CXCTRL_IGNORE_BT(void *cmd, u32 val)
2559 {
2560 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(1));
2561 }
2562
RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN(void * cmd,u32 val)2563 static inline void RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN(void *cmd, u32 val)
2564 {
2565 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(2));
2566 }
2567
RTW89_SET_FWCMD_CXCTRL_TRACE_STEP(void * cmd,u32 val)2568 static inline void RTW89_SET_FWCMD_CXCTRL_TRACE_STEP(void *cmd, u32 val)
2569 {
2570 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(18, 3));
2571 }
2572
RTW89_SET_FWCMD_CXTRX_TXLV(void * cmd,u8 val)2573 static inline void RTW89_SET_FWCMD_CXTRX_TXLV(void *cmd, u8 val)
2574 {
2575 u8p_replace_bits((u8 *)cmd + 2, val, GENMASK(7, 0));
2576 }
2577
RTW89_SET_FWCMD_CXTRX_RXLV(void * cmd,u8 val)2578 static inline void RTW89_SET_FWCMD_CXTRX_RXLV(void *cmd, u8 val)
2579 {
2580 u8p_replace_bits((u8 *)cmd + 3, val, GENMASK(7, 0));
2581 }
2582
RTW89_SET_FWCMD_CXTRX_WLRSSI(void * cmd,u8 val)2583 static inline void RTW89_SET_FWCMD_CXTRX_WLRSSI(void *cmd, u8 val)
2584 {
2585 u8p_replace_bits((u8 *)cmd + 4, val, GENMASK(7, 0));
2586 }
2587
RTW89_SET_FWCMD_CXTRX_BTRSSI(void * cmd,u8 val)2588 static inline void RTW89_SET_FWCMD_CXTRX_BTRSSI(void *cmd, u8 val)
2589 {
2590 u8p_replace_bits((u8 *)cmd + 5, val, GENMASK(7, 0));
2591 }
2592
RTW89_SET_FWCMD_CXTRX_TXPWR(void * cmd,s8 val)2593 static inline void RTW89_SET_FWCMD_CXTRX_TXPWR(void *cmd, s8 val)
2594 {
2595 u8p_replace_bits((u8 *)cmd + 6, val, GENMASK(7, 0));
2596 }
2597
RTW89_SET_FWCMD_CXTRX_RXGAIN(void * cmd,s8 val)2598 static inline void RTW89_SET_FWCMD_CXTRX_RXGAIN(void *cmd, s8 val)
2599 {
2600 u8p_replace_bits((u8 *)cmd + 7, val, GENMASK(7, 0));
2601 }
2602
RTW89_SET_FWCMD_CXTRX_BTTXPWR(void * cmd,s8 val)2603 static inline void RTW89_SET_FWCMD_CXTRX_BTTXPWR(void *cmd, s8 val)
2604 {
2605 u8p_replace_bits((u8 *)cmd + 8, val, GENMASK(7, 0));
2606 }
2607
RTW89_SET_FWCMD_CXTRX_BTRXGAIN(void * cmd,s8 val)2608 static inline void RTW89_SET_FWCMD_CXTRX_BTRXGAIN(void *cmd, s8 val)
2609 {
2610 u8p_replace_bits((u8 *)cmd + 9, val, GENMASK(7, 0));
2611 }
2612
RTW89_SET_FWCMD_CXTRX_CN(void * cmd,u8 val)2613 static inline void RTW89_SET_FWCMD_CXTRX_CN(void *cmd, u8 val)
2614 {
2615 u8p_replace_bits((u8 *)cmd + 10, val, GENMASK(7, 0));
2616 }
2617
RTW89_SET_FWCMD_CXTRX_NHM(void * cmd,s8 val)2618 static inline void RTW89_SET_FWCMD_CXTRX_NHM(void *cmd, s8 val)
2619 {
2620 u8p_replace_bits((u8 *)cmd + 11, val, GENMASK(7, 0));
2621 }
2622
RTW89_SET_FWCMD_CXTRX_BTPROFILE(void * cmd,u8 val)2623 static inline void RTW89_SET_FWCMD_CXTRX_BTPROFILE(void *cmd, u8 val)
2624 {
2625 u8p_replace_bits((u8 *)cmd + 12, val, GENMASK(7, 0));
2626 }
2627
RTW89_SET_FWCMD_CXTRX_RSVD2(void * cmd,u8 val)2628 static inline void RTW89_SET_FWCMD_CXTRX_RSVD2(void *cmd, u8 val)
2629 {
2630 u8p_replace_bits((u8 *)cmd + 13, val, GENMASK(7, 0));
2631 }
2632
RTW89_SET_FWCMD_CXTRX_TXRATE(void * cmd,u16 val)2633 static inline void RTW89_SET_FWCMD_CXTRX_TXRATE(void *cmd, u16 val)
2634 {
2635 le16p_replace_bits((__le16 *)((u8 *)cmd + 14), val, GENMASK(15, 0));
2636 }
2637
RTW89_SET_FWCMD_CXTRX_RXRATE(void * cmd,u16 val)2638 static inline void RTW89_SET_FWCMD_CXTRX_RXRATE(void *cmd, u16 val)
2639 {
2640 le16p_replace_bits((__le16 *)((u8 *)cmd + 16), val, GENMASK(15, 0));
2641 }
2642
RTW89_SET_FWCMD_CXTRX_TXTP(void * cmd,u32 val)2643 static inline void RTW89_SET_FWCMD_CXTRX_TXTP(void *cmd, u32 val)
2644 {
2645 le32p_replace_bits((__le32 *)((u8 *)cmd + 18), val, GENMASK(31, 0));
2646 }
2647
RTW89_SET_FWCMD_CXTRX_RXTP(void * cmd,u32 val)2648 static inline void RTW89_SET_FWCMD_CXTRX_RXTP(void *cmd, u32 val)
2649 {
2650 le32p_replace_bits((__le32 *)((u8 *)cmd + 22), val, GENMASK(31, 0));
2651 }
2652
RTW89_SET_FWCMD_CXTRX_RXERRRA(void * cmd,u32 val)2653 static inline void RTW89_SET_FWCMD_CXTRX_RXERRRA(void *cmd, u32 val)
2654 {
2655 le32p_replace_bits((__le32 *)((u8 *)cmd + 26), val, GENMASK(31, 0));
2656 }
2657
RTW89_SET_FWCMD_CXRFK_STATE(void * cmd,u32 val)2658 static inline void RTW89_SET_FWCMD_CXRFK_STATE(void *cmd, u32 val)
2659 {
2660 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(1, 0));
2661 }
2662
RTW89_SET_FWCMD_CXRFK_PATH_MAP(void * cmd,u32 val)2663 static inline void RTW89_SET_FWCMD_CXRFK_PATH_MAP(void *cmd, u32 val)
2664 {
2665 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(5, 2));
2666 }
2667
RTW89_SET_FWCMD_CXRFK_PHY_MAP(void * cmd,u32 val)2668 static inline void RTW89_SET_FWCMD_CXRFK_PHY_MAP(void *cmd, u32 val)
2669 {
2670 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(7, 6));
2671 }
2672
RTW89_SET_FWCMD_CXRFK_BAND(void * cmd,u32 val)2673 static inline void RTW89_SET_FWCMD_CXRFK_BAND(void *cmd, u32 val)
2674 {
2675 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(9, 8));
2676 }
2677
RTW89_SET_FWCMD_CXRFK_TYPE(void * cmd,u32 val)2678 static inline void RTW89_SET_FWCMD_CXRFK_TYPE(void *cmd, u32 val)
2679 {
2680 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(17, 10));
2681 }
2682
RTW89_SET_FWCMD_PACKET_OFLD_PKT_IDX(void * cmd,u32 val)2683 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_IDX(void *cmd, u32 val)
2684 {
2685 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0));
2686 }
2687
RTW89_SET_FWCMD_PACKET_OFLD_PKT_OP(void * cmd,u32 val)2688 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_OP(void *cmd, u32 val)
2689 {
2690 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(10, 8));
2691 }
2692
RTW89_SET_FWCMD_PACKET_OFLD_PKT_LENGTH(void * cmd,u32 val)2693 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_LENGTH(void *cmd, u32 val)
2694 {
2695 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(31, 16));
2696 }
2697
2698 struct rtw89_h2c_chinfo_elem {
2699 __le32 w0;
2700 __le32 w1;
2701 __le32 w2;
2702 __le32 w3;
2703 __le32 w4;
2704 __le32 w5;
2705 __le32 w6;
2706 } __packed;
2707
2708 #define RTW89_H2C_CHINFO_W0_PERIOD GENMASK(7, 0)
2709 #define RTW89_H2C_CHINFO_W0_DWELL GENMASK(15, 8)
2710 #define RTW89_H2C_CHINFO_W0_CENTER_CH GENMASK(23, 16)
2711 #define RTW89_H2C_CHINFO_W0_PRI_CH GENMASK(31, 24)
2712 #define RTW89_H2C_CHINFO_W1_BW GENMASK(2, 0)
2713 #define RTW89_H2C_CHINFO_W1_ACTION GENMASK(7, 3)
2714 #define RTW89_H2C_CHINFO_W1_NUM_PKT GENMASK(11, 8)
2715 #define RTW89_H2C_CHINFO_W1_TX BIT(12)
2716 #define RTW89_H2C_CHINFO_W1_PAUSE_DATA BIT(13)
2717 #define RTW89_H2C_CHINFO_W1_BAND GENMASK(15, 14)
2718 #define RTW89_H2C_CHINFO_W1_PKT_ID GENMASK(23, 16)
2719 #define RTW89_H2C_CHINFO_W1_DFS BIT(24)
2720 #define RTW89_H2C_CHINFO_W1_TX_NULL BIT(25)
2721 #define RTW89_H2C_CHINFO_W1_RANDOM BIT(26)
2722 #define RTW89_H2C_CHINFO_W1_CFG_TX BIT(27)
2723 #define RTW89_H2C_CHINFO_W1_MACID_TX BIT(29)
2724 #define RTW89_H2C_CHINFO_W2_PKT0 GENMASK(7, 0)
2725 #define RTW89_H2C_CHINFO_W2_PKT1 GENMASK(15, 8)
2726 #define RTW89_H2C_CHINFO_W2_PKT2 GENMASK(23, 16)
2727 #define RTW89_H2C_CHINFO_W2_PKT3 GENMASK(31, 24)
2728 #define RTW89_H2C_CHINFO_W3_PKT4 GENMASK(7, 0)
2729 #define RTW89_H2C_CHINFO_W3_PKT5 GENMASK(15, 8)
2730 #define RTW89_H2C_CHINFO_W3_PKT6 GENMASK(23, 16)
2731 #define RTW89_H2C_CHINFO_W3_PKT7 GENMASK(31, 24)
2732 #define RTW89_H2C_CHINFO_W4_POWER_IDX GENMASK(15, 0)
2733
2734 struct rtw89_h2c_chinfo_elem_be {
2735 __le32 w0;
2736 __le32 w1;
2737 __le32 w2;
2738 __le32 w3;
2739 __le32 w4;
2740 __le32 w5;
2741 __le32 w6;
2742 __le32 w7;
2743 } __packed;
2744
2745 #define RTW89_H2C_CHINFO_BE_W0_PERIOD GENMASK(7, 0)
2746 #define RTW89_H2C_CHINFO_BE_W0_DWELL GENMASK(15, 8)
2747 #define RTW89_H2C_CHINFO_BE_W0_CENTER_CH GENMASK(23, 16)
2748 #define RTW89_H2C_CHINFO_BE_W0_PRI_CH GENMASK(31, 24)
2749 #define RTW89_H2C_CHINFO_BE_W1_BW GENMASK(2, 0)
2750 #define RTW89_H2C_CHINFO_BE_W1_CH_BAND GENMASK(4, 3)
2751 #define RTW89_H2C_CHINFO_BE_W1_DFS BIT(5)
2752 #define RTW89_H2C_CHINFO_BE_W1_PAUSE_DATA BIT(6)
2753 #define RTW89_H2C_CHINFO_BE_W1_TX_NULL BIT(7)
2754 #define RTW89_H2C_CHINFO_BE_W1_RANDOM BIT(8)
2755 #define RTW89_H2C_CHINFO_BE_W1_NOTIFY GENMASK(13, 9)
2756 #define RTW89_H2C_CHINFO_BE_W1_PROBE BIT(14)
2757 #define RTW89_H2C_CHINFO_BE_W1_EARLY_LEAVE_CRIT GENMASK(17, 15)
2758 #define RTW89_H2C_CHINFO_BE_W1_CHKPT_TIMER GENMASK(31, 24)
2759 #define RTW89_H2C_CHINFO_BE_W2_EARLY_LEAVE_TIME GENMASK(7, 0)
2760 #define RTW89_H2C_CHINFO_BE_W2_EARLY_LEAVE_TH GENMASK(15, 8)
2761 #define RTW89_H2C_CHINFO_BE_W2_TX_PKT_CTRL GENMASK(31, 16)
2762 #define RTW89_H2C_CHINFO_BE_W3_PKT0 GENMASK(7, 0)
2763 #define RTW89_H2C_CHINFO_BE_W3_PKT1 GENMASK(15, 8)
2764 #define RTW89_H2C_CHINFO_BE_W3_PKT2 GENMASK(23, 16)
2765 #define RTW89_H2C_CHINFO_BE_W3_PKT3 GENMASK(31, 24)
2766 #define RTW89_H2C_CHINFO_BE_W4_PKT4 GENMASK(7, 0)
2767 #define RTW89_H2C_CHINFO_BE_W4_PKT5 GENMASK(15, 8)
2768 #define RTW89_H2C_CHINFO_BE_W4_PKT6 GENMASK(23, 16)
2769 #define RTW89_H2C_CHINFO_BE_W4_PKT7 GENMASK(31, 24)
2770 #define RTW89_H2C_CHINFO_BE_W5_SW_DEF GENMASK(7, 0)
2771 #define RTW89_H2C_CHINFO_BE_W5_FW_PROBE0_SSIDS GENMASK(31, 16)
2772 #define RTW89_H2C_CHINFO_BE_W6_FW_PROBE0_SHORTSSIDS GENMASK(15, 0)
2773 #define RTW89_H2C_CHINFO_BE_W6_FW_PROBE0_BSSIDS GENMASK(31, 16)
2774 #define RTW89_H2C_CHINFO_BE_W7_PERIOD_V1 GENMASK(15, 0)
2775
2776 struct rtw89_h2c_chinfo {
2777 u8 ch_num;
2778 u8 elem_size;
2779 u8 arg;
2780 u8 rsvd0;
2781 struct rtw89_h2c_chinfo_elem elem[] __counted_by(ch_num);
2782 } __packed;
2783
2784 struct rtw89_h2c_chinfo_be {
2785 u8 ch_num;
2786 u8 elem_size;
2787 u8 arg;
2788 u8 rsvd0;
2789 struct rtw89_h2c_chinfo_elem_be elem[] __counted_by(ch_num);
2790 } __packed;
2791
2792 #define RTW89_H2C_CHINFO_ARG_MAC_IDX_MASK BIT(0)
2793 #define RTW89_H2C_CHINFO_ARG_APPEND_MASK BIT(1)
2794
2795 struct rtw89_h2c_scanofld {
2796 __le32 w0;
2797 __le32 w1;
2798 __le32 w2;
2799 __le32 tsf_high;
2800 __le32 tsf_low;
2801 __le32 w5;
2802 __le32 w6;
2803 } __packed;
2804
2805 #define RTW89_H2C_SCANOFLD_W0_MACID GENMASK(7, 0)
2806 #define RTW89_H2C_SCANOFLD_W0_NORM_CY GENMASK(15, 8)
2807 #define RTW89_H2C_SCANOFLD_W0_PORT_ID GENMASK(18, 16)
2808 #define RTW89_H2C_SCANOFLD_W0_BAND BIT(19)
2809 #define RTW89_H2C_SCANOFLD_W0_OPERATION GENMASK(21, 20)
2810 #define RTW89_H2C_SCANOFLD_W0_TARGET_CH_BAND GENMASK(23, 22)
2811 #define RTW89_H2C_SCANOFLD_W1_NOTIFY_END BIT(0)
2812 #define RTW89_H2C_SCANOFLD_W1_TARGET_CH_MODE BIT(1)
2813 #define RTW89_H2C_SCANOFLD_W1_START_MODE BIT(2)
2814 #define RTW89_H2C_SCANOFLD_W1_SCAN_TYPE GENMASK(4, 3)
2815 #define RTW89_H2C_SCANOFLD_W1_TARGET_CH_BW GENMASK(7, 5)
2816 #define RTW89_H2C_SCANOFLD_W1_TARGET_PRI_CH GENMASK(15, 8)
2817 #define RTW89_H2C_SCANOFLD_W1_TARGET_CENTRAL_CH GENMASK(23, 16)
2818 #define RTW89_H2C_SCANOFLD_W1_PROBE_REQ_PKT_ID GENMASK(31, 24)
2819 #define RTW89_H2C_SCANOFLD_W2_NORM_PD GENMASK(15, 0)
2820 #define RTW89_H2C_SCANOFLD_W2_SLOW_PD GENMASK(23, 16)
2821 #define RTW89_H2C_SCANOFLD_W3_TSF_HIGH GENMASK(31, 0)
2822 #define RTW89_H2C_SCANOFLD_W4_TSF_LOW GENMASK(31, 0)
2823 #define RTW89_H2C_SCANOFLD_W6_SECOND_MACID GENMASK(31, 24)
2824
2825 struct rtw89_h2c_scanofld_be_macc_role {
2826 __le32 w0;
2827 } __packed;
2828
2829 #define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_BAND GENMASK(1, 0)
2830 #define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_PORT GENMASK(4, 2)
2831 #define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_MACID GENMASK(23, 8)
2832 #define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_OPCH_END GENMASK(31, 24)
2833
2834 struct rtw89_h2c_scanofld_be_opch {
2835 __le32 w0;
2836 __le32 w1;
2837 __le32 w2;
2838 __le32 w3;
2839 __le32 w4;
2840 } __packed;
2841
2842 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_MACID GENMASK(15, 0)
2843 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_BAND GENMASK(17, 16)
2844 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_PORT GENMASK(20, 18)
2845 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_POLICY GENMASK(22, 21)
2846 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_TXNULL BIT(23)
2847 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_POLICY_VAL GENMASK(31, 24)
2848 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_DURATION GENMASK(7, 0)
2849 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_CH_BAND GENMASK(9, 8)
2850 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_BW GENMASK(12, 10)
2851 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_NOTIFY GENMASK(14, 13)
2852 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_PRI_CH GENMASK(23, 16)
2853 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_CENTRAL_CH GENMASK(31, 24)
2854 #define RTW89_H2C_SCANOFLD_BE_OPCH_W2_PKTS_CTRL GENMASK(7, 0)
2855 #define RTW89_H2C_SCANOFLD_BE_OPCH_W2_SW_DEF GENMASK(15, 8)
2856 #define RTW89_H2C_SCANOFLD_BE_OPCH_W2_SS GENMASK(18, 16)
2857 #define RTW89_H2C_SCANOFLD_BE_OPCH_W2_TXBCN BIT(19)
2858 #define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT0 GENMASK(7, 0)
2859 #define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT1 GENMASK(15, 8)
2860 #define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT2 GENMASK(23, 16)
2861 #define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT3 GENMASK(31, 24)
2862 #define RTW89_H2C_SCANOFLD_BE_OPCH_W4_DURATION_V1 GENMASK(15, 0)
2863
2864 struct rtw89_h2c_scanofld_be {
2865 __le32 w0;
2866 __le32 w1;
2867 __le32 w2;
2868 __le32 w3;
2869 __le32 w4;
2870 __le32 w5;
2871 __le32 w6;
2872 __le32 w7;
2873 __le32 w8;
2874 __le32 w9; /* Added after SCAN_OFFLOAD_BE_V1 */
2875 /* struct rtw89_h2c_scanofld_be_macc_role (flexible number) */
2876 /* struct rtw89_h2c_scanofld_be_opch (flexible number) */
2877 } __packed;
2878
2879 #define RTW89_H2C_SCANOFLD_BE_W0_OP GENMASK(1, 0)
2880 #define RTW89_H2C_SCANOFLD_BE_W0_SCAN_MODE GENMASK(3, 2)
2881 #define RTW89_H2C_SCANOFLD_BE_W0_REPEAT GENMASK(5, 4)
2882 #define RTW89_H2C_SCANOFLD_BE_W0_NOTIFY_END BIT(6)
2883 #define RTW89_H2C_SCANOFLD_BE_W0_LEARN_CH BIT(7)
2884 #define RTW89_H2C_SCANOFLD_BE_W0_MACID GENMASK(23, 8)
2885 #define RTW89_H2C_SCANOFLD_BE_W0_PORT GENMASK(26, 24)
2886 #define RTW89_H2C_SCANOFLD_BE_W0_BAND GENMASK(28, 27)
2887 #define RTW89_H2C_SCANOFLD_BE_W0_PROBE_WITH_RATE BIT(29)
2888 #define RTW89_H2C_SCANOFLD_BE_W1_NUM_MACC_ROLE GENMASK(7, 0)
2889 #define RTW89_H2C_SCANOFLD_BE_W1_NUM_OP GENMASK(15, 8)
2890 #define RTW89_H2C_SCANOFLD_BE_W1_NORM_PD GENMASK(31, 16)
2891 #define RTW89_H2C_SCANOFLD_BE_W2_SLOW_PD GENMASK(15, 0)
2892 #define RTW89_H2C_SCANOFLD_BE_W2_NORM_CY GENMASK(23, 16)
2893 #define RTW89_H2C_SCANOFLD_BE_W2_OPCH_END GENMASK(31, 24)
2894 #define RTW89_H2C_SCANOFLD_BE_W3_NUM_SSID GENMASK(7, 0)
2895 #define RTW89_H2C_SCANOFLD_BE_W3_NUM_SHORT_SSID GENMASK(15, 8)
2896 #define RTW89_H2C_SCANOFLD_BE_W3_NUM_BSSID GENMASK(23, 16)
2897 #define RTW89_H2C_SCANOFLD_BE_W3_PROBEID GENMASK(31, 24)
2898 #define RTW89_H2C_SCANOFLD_BE_W4_PROBE_5G GENMASK(7, 0)
2899 #define RTW89_H2C_SCANOFLD_BE_W4_PROBE_6G GENMASK(15, 8)
2900 #define RTW89_H2C_SCANOFLD_BE_W4_DELAY_START GENMASK(31, 16)
2901 #define RTW89_H2C_SCANOFLD_BE_W5_MLO_MODE GENMASK(31, 0)
2902 #define RTW89_H2C_SCANOFLD_BE_W6_CHAN_PROHIB_LOW GENMASK(31, 0)
2903 #define RTW89_H2C_SCANOFLD_BE_W7_CHAN_PROHIB_HIGH GENMASK(31, 0)
2904 #define RTW89_H2C_SCANOFLD_BE_W8_PROBE_RATE_2GHZ GENMASK(7, 0)
2905 #define RTW89_H2C_SCANOFLD_BE_W8_PROBE_RATE_5GHZ GENMASK(15, 8)
2906 #define RTW89_H2C_SCANOFLD_BE_W8_PROBE_RATE_6GHZ GENMASK(23, 16)
2907 #define RTW89_H2C_SCANOFLD_BE_W9_SIZE_CFG GENMASK(7, 0)
2908 #define RTW89_H2C_SCANOFLD_BE_W9_SIZE_MACC GENMASK(15, 8)
2909 #define RTW89_H2C_SCANOFLD_BE_W9_SIZE_OP GENMASK(23, 16)
2910
2911 struct rtw89_h2c_fwips {
2912 __le32 w0;
2913 } __packed;
2914
2915 #define RTW89_H2C_FW_IPS_W0_MACID GENMASK(7, 0)
2916 #define RTW89_H2C_FW_IPS_W0_ENABLE BIT(8)
2917
2918 struct rtw89_h2c_mlo_link_cfg {
2919 __le32 w0;
2920 };
2921
2922 #define RTW89_H2C_MLO_LINK_CFG_W0_MACID GENMASK(15, 0)
2923 #define RTW89_H2C_MLO_LINK_CFG_W0_OPTION GENMASK(19, 16)
2924
RTW89_SET_FWCMD_P2P_MACID(void * cmd,u32 val)2925 static inline void RTW89_SET_FWCMD_P2P_MACID(void *cmd, u32 val)
2926 {
2927 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
2928 }
2929
RTW89_SET_FWCMD_P2P_P2PID(void * cmd,u32 val)2930 static inline void RTW89_SET_FWCMD_P2P_P2PID(void *cmd, u32 val)
2931 {
2932 le32p_replace_bits((__le32 *)cmd, val, GENMASK(11, 8));
2933 }
2934
RTW89_SET_FWCMD_P2P_NOAID(void * cmd,u32 val)2935 static inline void RTW89_SET_FWCMD_P2P_NOAID(void *cmd, u32 val)
2936 {
2937 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 12));
2938 }
2939
RTW89_SET_FWCMD_P2P_ACT(void * cmd,u32 val)2940 static inline void RTW89_SET_FWCMD_P2P_ACT(void *cmd, u32 val)
2941 {
2942 le32p_replace_bits((__le32 *)cmd, val, GENMASK(19, 16));
2943 }
2944
RTW89_SET_FWCMD_P2P_TYPE(void * cmd,u32 val)2945 static inline void RTW89_SET_FWCMD_P2P_TYPE(void *cmd, u32 val)
2946 {
2947 le32p_replace_bits((__le32 *)cmd, val, BIT(20));
2948 }
2949
RTW89_SET_FWCMD_P2P_ALL_SLEP(void * cmd,u32 val)2950 static inline void RTW89_SET_FWCMD_P2P_ALL_SLEP(void *cmd, u32 val)
2951 {
2952 le32p_replace_bits((__le32 *)cmd, val, BIT(21));
2953 }
2954
RTW89_SET_FWCMD_NOA_START_TIME(void * cmd,__le32 val)2955 static inline void RTW89_SET_FWCMD_NOA_START_TIME(void *cmd, __le32 val)
2956 {
2957 *((__le32 *)cmd + 1) = val;
2958 }
2959
RTW89_SET_FWCMD_NOA_INTERVAL(void * cmd,__le32 val)2960 static inline void RTW89_SET_FWCMD_NOA_INTERVAL(void *cmd, __le32 val)
2961 {
2962 *((__le32 *)cmd + 2) = val;
2963 }
2964
RTW89_SET_FWCMD_NOA_DURATION(void * cmd,__le32 val)2965 static inline void RTW89_SET_FWCMD_NOA_DURATION(void *cmd, __le32 val)
2966 {
2967 *((__le32 *)cmd + 3) = val;
2968 }
2969
RTW89_SET_FWCMD_NOA_COUNT(void * cmd,u32 val)2970 static inline void RTW89_SET_FWCMD_NOA_COUNT(void *cmd, u32 val)
2971 {
2972 le32p_replace_bits((__le32 *)(cmd) + 4, val, GENMASK(7, 0));
2973 }
2974
RTW89_SET_FWCMD_NOA_CTWINDOW(void * cmd,u32 val)2975 static inline void RTW89_SET_FWCMD_NOA_CTWINDOW(void *cmd, u32 val)
2976 {
2977 u8 ctwnd;
2978
2979 if (!(val & IEEE80211_P2P_OPPPS_ENABLE_BIT))
2980 return;
2981 ctwnd = FIELD_GET(IEEE80211_P2P_OPPPS_CTWINDOW_MASK, val);
2982 le32p_replace_bits((__le32 *)(cmd) + 4, ctwnd, GENMASK(23, 8));
2983 }
2984
RTW89_SET_FWCMD_TSF32_TOGL_BAND(void * cmd,u32 val)2985 static inline void RTW89_SET_FWCMD_TSF32_TOGL_BAND(void *cmd, u32 val)
2986 {
2987 le32p_replace_bits((__le32 *)cmd, val, BIT(0));
2988 }
2989
RTW89_SET_FWCMD_TSF32_TOGL_EN(void * cmd,u32 val)2990 static inline void RTW89_SET_FWCMD_TSF32_TOGL_EN(void *cmd, u32 val)
2991 {
2992 le32p_replace_bits((__le32 *)cmd, val, BIT(1));
2993 }
2994
RTW89_SET_FWCMD_TSF32_TOGL_PORT(void * cmd,u32 val)2995 static inline void RTW89_SET_FWCMD_TSF32_TOGL_PORT(void *cmd, u32 val)
2996 {
2997 le32p_replace_bits((__le32 *)cmd, val, GENMASK(4, 2));
2998 }
2999
RTW89_SET_FWCMD_TSF32_TOGL_EARLY(void * cmd,u32 val)3000 static inline void RTW89_SET_FWCMD_TSF32_TOGL_EARLY(void *cmd, u32 val)
3001 {
3002 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 16));
3003 }
3004
3005 enum rtw89_fw_mcc_c2h_rpt_cfg {
3006 RTW89_FW_MCC_C2H_RPT_OFF = 0,
3007 RTW89_FW_MCC_C2H_RPT_FAIL_ONLY = 1,
3008 RTW89_FW_MCC_C2H_RPT_ALL = 2,
3009 };
3010
3011 struct rtw89_fw_mcc_add_req {
3012 u8 macid;
3013 u8 central_ch_seg0;
3014 u8 central_ch_seg1;
3015 u8 primary_ch;
3016 enum rtw89_bandwidth bandwidth: 4;
3017 u32 group: 2;
3018 u32 c2h_rpt: 2;
3019 u32 dis_tx_null: 1;
3020 u32 dis_sw_retry: 1;
3021 u32 in_curr_ch: 1;
3022 u32 sw_retry_count: 3;
3023 u32 tx_null_early: 4;
3024 u32 btc_in_2g: 1;
3025 u32 pta_en: 1;
3026 u32 rfk_by_pass: 1;
3027 u32 ch_band_type: 2;
3028 u32 rsvd0: 9;
3029 u32 duration;
3030 u8 courtesy_en;
3031 u8 courtesy_num;
3032 u8 courtesy_target;
3033 u8 rsvd1;
3034 };
3035
RTW89_SET_FWCMD_ADD_MCC_MACID(void * cmd,u32 val)3036 static inline void RTW89_SET_FWCMD_ADD_MCC_MACID(void *cmd, u32 val)
3037 {
3038 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
3039 }
3040
RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG0(void * cmd,u32 val)3041 static inline void RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG0(void *cmd, u32 val)
3042 {
3043 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3044 }
3045
RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG1(void * cmd,u32 val)3046 static inline void RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG1(void *cmd, u32 val)
3047 {
3048 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3049 }
3050
RTW89_SET_FWCMD_ADD_MCC_PRIMARY_CH(void * cmd,u32 val)3051 static inline void RTW89_SET_FWCMD_ADD_MCC_PRIMARY_CH(void *cmd, u32 val)
3052 {
3053 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
3054 }
3055
RTW89_SET_FWCMD_ADD_MCC_BANDWIDTH(void * cmd,u32 val)3056 static inline void RTW89_SET_FWCMD_ADD_MCC_BANDWIDTH(void *cmd, u32 val)
3057 {
3058 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(3, 0));
3059 }
3060
RTW89_SET_FWCMD_ADD_MCC_GROUP(void * cmd,u32 val)3061 static inline void RTW89_SET_FWCMD_ADD_MCC_GROUP(void *cmd, u32 val)
3062 {
3063 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(5, 4));
3064 }
3065
RTW89_SET_FWCMD_ADD_MCC_C2H_RPT(void * cmd,u32 val)3066 static inline void RTW89_SET_FWCMD_ADD_MCC_C2H_RPT(void *cmd, u32 val)
3067 {
3068 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(7, 6));
3069 }
3070
RTW89_SET_FWCMD_ADD_MCC_DIS_TX_NULL(void * cmd,u32 val)3071 static inline void RTW89_SET_FWCMD_ADD_MCC_DIS_TX_NULL(void *cmd, u32 val)
3072 {
3073 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(8));
3074 }
3075
RTW89_SET_FWCMD_ADD_MCC_DIS_SW_RETRY(void * cmd,u32 val)3076 static inline void RTW89_SET_FWCMD_ADD_MCC_DIS_SW_RETRY(void *cmd, u32 val)
3077 {
3078 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(9));
3079 }
3080
RTW89_SET_FWCMD_ADD_MCC_IN_CURR_CH(void * cmd,u32 val)3081 static inline void RTW89_SET_FWCMD_ADD_MCC_IN_CURR_CH(void *cmd, u32 val)
3082 {
3083 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(10));
3084 }
3085
RTW89_SET_FWCMD_ADD_MCC_SW_RETRY_COUNT(void * cmd,u32 val)3086 static inline void RTW89_SET_FWCMD_ADD_MCC_SW_RETRY_COUNT(void *cmd, u32 val)
3087 {
3088 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(13, 11));
3089 }
3090
RTW89_SET_FWCMD_ADD_MCC_TX_NULL_EARLY(void * cmd,u32 val)3091 static inline void RTW89_SET_FWCMD_ADD_MCC_TX_NULL_EARLY(void *cmd, u32 val)
3092 {
3093 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(17, 14));
3094 }
3095
RTW89_SET_FWCMD_ADD_MCC_BTC_IN_2G(void * cmd,u32 val)3096 static inline void RTW89_SET_FWCMD_ADD_MCC_BTC_IN_2G(void *cmd, u32 val)
3097 {
3098 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(18));
3099 }
3100
RTW89_SET_FWCMD_ADD_MCC_PTA_EN(void * cmd,u32 val)3101 static inline void RTW89_SET_FWCMD_ADD_MCC_PTA_EN(void *cmd, u32 val)
3102 {
3103 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(19));
3104 }
3105
RTW89_SET_FWCMD_ADD_MCC_RFK_BY_PASS(void * cmd,u32 val)3106 static inline void RTW89_SET_FWCMD_ADD_MCC_RFK_BY_PASS(void *cmd, u32 val)
3107 {
3108 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(20));
3109 }
3110
RTW89_SET_FWCMD_ADD_MCC_CH_BAND_TYPE(void * cmd,u32 val)3111 static inline void RTW89_SET_FWCMD_ADD_MCC_CH_BAND_TYPE(void *cmd, u32 val)
3112 {
3113 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(22, 21));
3114 }
3115
RTW89_SET_FWCMD_ADD_MCC_DURATION(void * cmd,u32 val)3116 static inline void RTW89_SET_FWCMD_ADD_MCC_DURATION(void *cmd, u32 val)
3117 {
3118 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
3119 }
3120
RTW89_SET_FWCMD_ADD_MCC_COURTESY_EN(void * cmd,u32 val)3121 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_EN(void *cmd, u32 val)
3122 {
3123 le32p_replace_bits((__le32 *)cmd + 3, val, BIT(0));
3124 }
3125
RTW89_SET_FWCMD_ADD_MCC_COURTESY_NUM(void * cmd,u32 val)3126 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_NUM(void *cmd, u32 val)
3127 {
3128 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(15, 8));
3129 }
3130
RTW89_SET_FWCMD_ADD_MCC_COURTESY_TARGET(void * cmd,u32 val)3131 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_TARGET(void *cmd, u32 val)
3132 {
3133 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(23, 16));
3134 }
3135
3136 enum rtw89_fw_mcc_old_group_actions {
3137 RTW89_FW_MCC_OLD_GROUP_ACT_NONE = 0,
3138 RTW89_FW_MCC_OLD_GROUP_ACT_REPLACE = 1,
3139 };
3140
3141 struct rtw89_fw_mcc_start_req {
3142 u32 group: 2;
3143 u32 btc_in_group: 1;
3144 u32 old_group_action: 2;
3145 u32 old_group: 2;
3146 u32 rsvd0: 9;
3147 u32 notify_cnt: 3;
3148 u32 rsvd1: 2;
3149 u32 notify_rxdbg_en: 1;
3150 u32 rsvd2: 2;
3151 u32 macid: 8;
3152 u32 tsf_low;
3153 u32 tsf_high;
3154 };
3155
RTW89_SET_FWCMD_START_MCC_GROUP(void * cmd,u32 val)3156 static inline void RTW89_SET_FWCMD_START_MCC_GROUP(void *cmd, u32 val)
3157 {
3158 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3159 }
3160
RTW89_SET_FWCMD_START_MCC_BTC_IN_GROUP(void * cmd,u32 val)3161 static inline void RTW89_SET_FWCMD_START_MCC_BTC_IN_GROUP(void *cmd, u32 val)
3162 {
3163 le32p_replace_bits((__le32 *)cmd, val, BIT(2));
3164 }
3165
RTW89_SET_FWCMD_START_MCC_OLD_GROUP_ACTION(void * cmd,u32 val)3166 static inline void RTW89_SET_FWCMD_START_MCC_OLD_GROUP_ACTION(void *cmd, u32 val)
3167 {
3168 le32p_replace_bits((__le32 *)cmd, val, GENMASK(4, 3));
3169 }
3170
RTW89_SET_FWCMD_START_MCC_OLD_GROUP(void * cmd,u32 val)3171 static inline void RTW89_SET_FWCMD_START_MCC_OLD_GROUP(void *cmd, u32 val)
3172 {
3173 le32p_replace_bits((__le32 *)cmd, val, GENMASK(6, 5));
3174 }
3175
RTW89_SET_FWCMD_START_MCC_NOTIFY_CNT(void * cmd,u32 val)3176 static inline void RTW89_SET_FWCMD_START_MCC_NOTIFY_CNT(void *cmd, u32 val)
3177 {
3178 le32p_replace_bits((__le32 *)cmd, val, GENMASK(18, 16));
3179 }
3180
RTW89_SET_FWCMD_START_MCC_NOTIFY_RXDBG_EN(void * cmd,u32 val)3181 static inline void RTW89_SET_FWCMD_START_MCC_NOTIFY_RXDBG_EN(void *cmd, u32 val)
3182 {
3183 le32p_replace_bits((__le32 *)cmd, val, BIT(21));
3184 }
3185
RTW89_SET_FWCMD_START_MCC_MACID(void * cmd,u32 val)3186 static inline void RTW89_SET_FWCMD_START_MCC_MACID(void *cmd, u32 val)
3187 {
3188 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
3189 }
3190
RTW89_SET_FWCMD_START_MCC_TSF_LOW(void * cmd,u32 val)3191 static inline void RTW89_SET_FWCMD_START_MCC_TSF_LOW(void *cmd, u32 val)
3192 {
3193 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(31, 0));
3194 }
3195
RTW89_SET_FWCMD_START_MCC_TSF_HIGH(void * cmd,u32 val)3196 static inline void RTW89_SET_FWCMD_START_MCC_TSF_HIGH(void *cmd, u32 val)
3197 {
3198 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
3199 }
3200
RTW89_SET_FWCMD_STOP_MCC_MACID(void * cmd,u32 val)3201 static inline void RTW89_SET_FWCMD_STOP_MCC_MACID(void *cmd, u32 val)
3202 {
3203 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
3204 }
3205
RTW89_SET_FWCMD_STOP_MCC_GROUP(void * cmd,u32 val)3206 static inline void RTW89_SET_FWCMD_STOP_MCC_GROUP(void *cmd, u32 val)
3207 {
3208 le32p_replace_bits((__le32 *)cmd, val, GENMASK(9, 8));
3209 }
3210
RTW89_SET_FWCMD_STOP_MCC_PREV_GROUPS(void * cmd,u32 val)3211 static inline void RTW89_SET_FWCMD_STOP_MCC_PREV_GROUPS(void *cmd, u32 val)
3212 {
3213 le32p_replace_bits((__le32 *)cmd, val, BIT(10));
3214 }
3215
RTW89_SET_FWCMD_DEL_MCC_GROUP_GROUP(void * cmd,u32 val)3216 static inline void RTW89_SET_FWCMD_DEL_MCC_GROUP_GROUP(void *cmd, u32 val)
3217 {
3218 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3219 }
3220
RTW89_SET_FWCMD_DEL_MCC_GROUP_PREV_GROUPS(void * cmd,u32 val)3221 static inline void RTW89_SET_FWCMD_DEL_MCC_GROUP_PREV_GROUPS(void *cmd, u32 val)
3222 {
3223 le32p_replace_bits((__le32 *)cmd, val, BIT(2));
3224 }
3225
RTW89_SET_FWCMD_RESET_MCC_GROUP_GROUP(void * cmd,u32 val)3226 static inline void RTW89_SET_FWCMD_RESET_MCC_GROUP_GROUP(void *cmd, u32 val)
3227 {
3228 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3229 }
3230
3231 struct rtw89_fw_mcc_tsf_req {
3232 u8 group: 2;
3233 u8 rsvd0: 6;
3234 u8 macid_x;
3235 u8 macid_y;
3236 u8 rsvd1;
3237 };
3238
RTW89_SET_FWCMD_MCC_REQ_TSF_GROUP(void * cmd,u32 val)3239 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_GROUP(void *cmd, u32 val)
3240 {
3241 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3242 }
3243
RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_X(void * cmd,u32 val)3244 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_X(void *cmd, u32 val)
3245 {
3246 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3247 }
3248
RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_Y(void * cmd,u32 val)3249 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_Y(void *cmd, u32 val)
3250 {
3251 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3252 }
3253
RTW89_SET_FWCMD_MCC_MACID_BITMAP_GROUP(void * cmd,u32 val)3254 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_GROUP(void *cmd, u32 val)
3255 {
3256 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3257 }
3258
RTW89_SET_FWCMD_MCC_MACID_BITMAP_MACID(void * cmd,u32 val)3259 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_MACID(void *cmd, u32 val)
3260 {
3261 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3262 }
3263
RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP_LENGTH(void * cmd,u32 val)3264 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP_LENGTH(void *cmd, u32 val)
3265 {
3266 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3267 }
3268
RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP(void * cmd,u8 * bitmap,u8 len)3269 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP(void *cmd,
3270 u8 *bitmap, u8 len)
3271 {
3272 memcpy((__le32 *)cmd + 1, bitmap, len);
3273 }
3274
RTW89_SET_FWCMD_MCC_SYNC_GROUP(void * cmd,u32 val)3275 static inline void RTW89_SET_FWCMD_MCC_SYNC_GROUP(void *cmd, u32 val)
3276 {
3277 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3278 }
3279
RTW89_SET_FWCMD_MCC_SYNC_MACID_SOURCE(void * cmd,u32 val)3280 static inline void RTW89_SET_FWCMD_MCC_SYNC_MACID_SOURCE(void *cmd, u32 val)
3281 {
3282 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3283 }
3284
RTW89_SET_FWCMD_MCC_SYNC_MACID_TARGET(void * cmd,u32 val)3285 static inline void RTW89_SET_FWCMD_MCC_SYNC_MACID_TARGET(void *cmd, u32 val)
3286 {
3287 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3288 }
3289
RTW89_SET_FWCMD_MCC_SYNC_SYNC_OFFSET(void * cmd,u32 val)3290 static inline void RTW89_SET_FWCMD_MCC_SYNC_SYNC_OFFSET(void *cmd, u32 val)
3291 {
3292 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
3293 }
3294
3295 struct rtw89_fw_mcc_duration {
3296 u32 group: 2;
3297 u32 btc_in_group: 1;
3298 u32 rsvd0: 5;
3299 u32 start_macid: 8;
3300 u32 macid_x: 8;
3301 u32 macid_y: 8;
3302 u32 start_tsf_low;
3303 u32 start_tsf_high;
3304 u32 duration_x;
3305 u32 duration_y;
3306 };
3307
RTW89_SET_FWCMD_MCC_SET_DURATION_GROUP(void * cmd,u32 val)3308 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_GROUP(void *cmd, u32 val)
3309 {
3310 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3311 }
3312
3313 static
RTW89_SET_FWCMD_MCC_SET_DURATION_BTC_IN_GROUP(void * cmd,u32 val)3314 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_BTC_IN_GROUP(void *cmd, u32 val)
3315 {
3316 le32p_replace_bits((__le32 *)cmd, val, BIT(2));
3317 }
3318
3319 static
RTW89_SET_FWCMD_MCC_SET_DURATION_START_MACID(void * cmd,u32 val)3320 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_MACID(void *cmd, u32 val)
3321 {
3322 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3323 }
3324
RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_X(void * cmd,u32 val)3325 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_X(void *cmd, u32 val)
3326 {
3327 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3328 }
3329
RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_Y(void * cmd,u32 val)3330 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_Y(void *cmd, u32 val)
3331 {
3332 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
3333 }
3334
3335 static
RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_LOW(void * cmd,u32 val)3336 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_LOW(void *cmd, u32 val)
3337 {
3338 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(31, 0));
3339 }
3340
3341 static
RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_HIGH(void * cmd,u32 val)3342 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_HIGH(void *cmd, u32 val)
3343 {
3344 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
3345 }
3346
3347 static
RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_X(void * cmd,u32 val)3348 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_X(void *cmd, u32 val)
3349 {
3350 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(31, 0));
3351 }
3352
3353 static
RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_Y(void * cmd,u32 val)3354 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_Y(void *cmd, u32 val)
3355 {
3356 le32p_replace_bits((__le32 *)cmd + 4, val, GENMASK(31, 0));
3357 }
3358
3359 enum rtw89_h2c_mrc_sch_types {
3360 RTW89_H2C_MRC_SCH_BAND0_ONLY = 0,
3361 RTW89_H2C_MRC_SCH_BAND1_ONLY = 1,
3362 RTW89_H2C_MRC_SCH_DUAL_BAND = 2,
3363 };
3364
3365 enum rtw89_h2c_mrc_role_types {
3366 RTW89_H2C_MRC_ROLE_WIFI = 0,
3367 RTW89_H2C_MRC_ROLE_BT = 1,
3368 RTW89_H2C_MRC_ROLE_EMPTY = 2,
3369 };
3370
3371 #define RTW89_MAC_MRC_MAX_ADD_SLOT_NUM 3
3372 #define RTW89_MAC_MRC_MAX_ADD_ROLE_NUM_PER_SLOT 1 /* before MLO */
3373
3374 struct rtw89_fw_mrc_add_slot_arg {
3375 u16 duration; /* unit: TU */
3376 bool courtesy_en;
3377 u8 courtesy_period;
3378 u8 courtesy_target; /* slot idx */
3379
3380 unsigned int role_num;
3381 struct {
3382 enum rtw89_h2c_mrc_role_types role_type;
3383 bool is_master;
3384 bool en_tx_null;
3385 enum rtw89_band band;
3386 enum rtw89_bandwidth bw;
3387 u8 macid;
3388 u8 central_ch;
3389 u8 primary_ch;
3390 u8 null_early; /* unit: TU */
3391
3392 /* if MLD, for macid: [0, chip::support_mld_num)
3393 * otherwise, for macid: [0, 32)
3394 */
3395 u32 macid_main_bitmap;
3396 /* for MLD, bit X maps to macid: X + chip::support_mld_num */
3397 u32 macid_paired_bitmap;
3398 } roles[RTW89_MAC_MRC_MAX_ADD_ROLE_NUM_PER_SLOT];
3399 };
3400
3401 struct rtw89_fw_mrc_add_arg {
3402 u8 sch_idx;
3403 enum rtw89_h2c_mrc_sch_types sch_type;
3404 bool btc_in_sch;
3405
3406 unsigned int slot_num;
3407 struct rtw89_fw_mrc_add_slot_arg slots[RTW89_MAC_MRC_MAX_ADD_SLOT_NUM];
3408 };
3409
3410 struct rtw89_h2c_mrc_add_role {
3411 __le32 w0;
3412 __le32 w1;
3413 __le32 w2;
3414 __le32 macid_main_bitmap;
3415 __le32 macid_paired_bitmap;
3416 } __packed;
3417
3418 #define RTW89_H2C_MRC_ADD_ROLE_W0_MACID GENMASK(15, 0)
3419 #define RTW89_H2C_MRC_ADD_ROLE_W0_ROLE_TYPE GENMASK(23, 16)
3420 #define RTW89_H2C_MRC_ADD_ROLE_W0_IS_MASTER BIT(24)
3421 #define RTW89_H2C_MRC_ADD_ROLE_W0_IS_ALT_ROLE BIT(25)
3422 #define RTW89_H2C_MRC_ADD_ROLE_W0_TX_NULL_EN BIT(26)
3423 #define RTW89_H2C_MRC_ADD_ROLE_W0_ROLE_ALT_EN BIT(27)
3424 #define RTW89_H2C_MRC_ADD_ROLE_W1_CENTRAL_CH_SEG GENMASK(7, 0)
3425 #define RTW89_H2C_MRC_ADD_ROLE_W1_PRI_CH GENMASK(15, 8)
3426 #define RTW89_H2C_MRC_ADD_ROLE_W1_BW GENMASK(19, 16)
3427 #define RTW89_H2C_MRC_ADD_ROLE_W1_CH_BAND_TYPE GENMASK(21, 20)
3428 #define RTW89_H2C_MRC_ADD_ROLE_W1_RFK_BY_PASS BIT(22)
3429 #define RTW89_H2C_MRC_ADD_ROLE_W1_CAN_BTC BIT(23)
3430 #define RTW89_H2C_MRC_ADD_ROLE_W1_NULL_EARLY GENMASK(31, 24)
3431 #define RTW89_H2C_MRC_ADD_ROLE_W2_ALT_PERIOD GENMASK(7, 0)
3432 #define RTW89_H2C_MRC_ADD_ROLE_W2_ALT_ROLE_TYPE GENMASK(15, 8)
3433 #define RTW89_H2C_MRC_ADD_ROLE_W2_ALT_ROLE_MACID GENMASK(23, 16)
3434
3435 struct rtw89_h2c_mrc_add_slot {
3436 __le32 w0;
3437 __le32 w1;
3438 struct rtw89_h2c_mrc_add_role roles[];
3439 } __packed;
3440
3441 #define RTW89_H2C_MRC_ADD_SLOT_W0_DURATION GENMASK(15, 0)
3442 #define RTW89_H2C_MRC_ADD_SLOT_W0_COURTESY_EN BIT(17)
3443 #define RTW89_H2C_MRC_ADD_SLOT_W0_ROLE_NUM GENMASK(31, 24)
3444 #define RTW89_H2C_MRC_ADD_SLOT_W1_COURTESY_PERIOD GENMASK(7, 0)
3445 #define RTW89_H2C_MRC_ADD_SLOT_W1_COURTESY_TARGET GENMASK(15, 8)
3446
3447 struct rtw89_h2c_mrc_add {
3448 __le32 w0;
3449 /* Logically append flexible struct rtw89_h2c_mrc_add_slot, but there
3450 * are other flexible array inside it. We cannot access them correctly
3451 * through this struct. So, in case misusing, we don't really declare
3452 * it here.
3453 */
3454 } __packed;
3455
3456 #define RTW89_H2C_MRC_ADD_W0_SCH_IDX GENMASK(3, 0)
3457 #define RTW89_H2C_MRC_ADD_W0_SCH_TYPE GENMASK(7, 4)
3458 #define RTW89_H2C_MRC_ADD_W0_SLOT_NUM GENMASK(15, 8)
3459 #define RTW89_H2C_MRC_ADD_W0_BTC_IN_SCH BIT(16)
3460
3461 enum rtw89_h2c_mrc_start_actions {
3462 RTW89_H2C_MRC_START_ACTION_START_NEW = 0,
3463 RTW89_H2C_MRC_START_ACTION_REPLACE_OLD = 1,
3464 };
3465
3466 struct rtw89_fw_mrc_start_arg {
3467 u8 sch_idx;
3468 u8 old_sch_idx;
3469 u64 start_tsf;
3470 enum rtw89_h2c_mrc_start_actions action;
3471 };
3472
3473 struct rtw89_h2c_mrc_start {
3474 __le32 w0;
3475 __le32 start_tsf_low;
3476 __le32 start_tsf_high;
3477 } __packed;
3478
3479 #define RTW89_H2C_MRC_START_W0_SCH_IDX GENMASK(3, 0)
3480 #define RTW89_H2C_MRC_START_W0_OLD_SCH_IDX GENMASK(7, 4)
3481 #define RTW89_H2C_MRC_START_W0_ACTION GENMASK(15, 8)
3482
3483 struct rtw89_h2c_mrc_del {
3484 __le32 w0;
3485 } __packed;
3486
3487 #define RTW89_H2C_MRC_DEL_W0_SCH_IDX GENMASK(3, 0)
3488 #define RTW89_H2C_MRC_DEL_W0_DEL_ALL BIT(4)
3489 #define RTW89_H2C_MRC_DEL_W0_STOP_ONLY BIT(5)
3490 #define RTW89_H2C_MRC_DEL_W0_SPECIFIC_ROLE_EN BIT(6)
3491 #define RTW89_H2C_MRC_DEL_W0_STOP_SLOT_IDX GENMASK(15, 8)
3492 #define RTW89_H2C_MRC_DEL_W0_SPECIFIC_ROLE_MACID GENMASK(31, 16)
3493
3494 #define RTW89_MAC_MRC_MAX_REQ_TSF_NUM 2
3495
3496 struct rtw89_fw_mrc_req_tsf_arg {
3497 unsigned int num;
3498 struct {
3499 u8 band;
3500 u8 port;
3501 } infos[RTW89_MAC_MRC_MAX_REQ_TSF_NUM];
3502 };
3503
3504 struct rtw89_h2c_mrc_req_tsf {
3505 u8 req_tsf_num;
3506 u8 infos[] __counted_by(req_tsf_num);
3507 } __packed;
3508
3509 #define RTW89_H2C_MRC_REQ_TSF_INFO_BAND GENMASK(3, 0)
3510 #define RTW89_H2C_MRC_REQ_TSF_INFO_PORT GENMASK(7, 4)
3511
3512 enum rtw89_h2c_mrc_upd_bitmap_actions {
3513 RTW89_H2C_MRC_UPD_BITMAP_ACTION_DEL = 0,
3514 RTW89_H2C_MRC_UPD_BITMAP_ACTION_ADD = 1,
3515 };
3516
3517 struct rtw89_fw_mrc_upd_bitmap_arg {
3518 u8 sch_idx;
3519 u8 macid;
3520 u8 client_macid;
3521 enum rtw89_h2c_mrc_upd_bitmap_actions action;
3522 };
3523
3524 struct rtw89_h2c_mrc_upd_bitmap {
3525 __le32 w0;
3526 __le32 w1;
3527 } __packed;
3528
3529 #define RTW89_H2C_MRC_UPD_BITMAP_W0_SCH_IDX GENMASK(3, 0)
3530 #define RTW89_H2C_MRC_UPD_BITMAP_W0_ACTION BIT(4)
3531 #define RTW89_H2C_MRC_UPD_BITMAP_W0_MACID GENMASK(31, 16)
3532 #define RTW89_H2C_MRC_UPD_BITMAP_W1_CLIENT_MACID GENMASK(15, 0)
3533
3534 struct rtw89_fw_mrc_sync_arg {
3535 u8 offset; /* unit: TU */
3536 struct {
3537 u8 band;
3538 u8 port;
3539 } src, dest;
3540 };
3541
3542 struct rtw89_h2c_mrc_sync {
3543 __le32 w0;
3544 __le32 w1;
3545 } __packed;
3546
3547 #define RTW89_H2C_MRC_SYNC_W0_SYNC_EN BIT(0)
3548 #define RTW89_H2C_MRC_SYNC_W0_SRC_PORT GENMASK(11, 8)
3549 #define RTW89_H2C_MRC_SYNC_W0_SRC_BAND GENMASK(15, 12)
3550 #define RTW89_H2C_MRC_SYNC_W0_DEST_PORT GENMASK(19, 16)
3551 #define RTW89_H2C_MRC_SYNC_W0_DEST_BAND GENMASK(23, 20)
3552 #define RTW89_H2C_MRC_SYNC_W1_OFFSET GENMASK(15, 0)
3553
3554 struct rtw89_fw_mrc_upd_duration_arg {
3555 u8 sch_idx;
3556 u64 start_tsf;
3557
3558 unsigned int slot_num;
3559 struct {
3560 u8 slot_idx;
3561 u16 duration; /* unit: TU */
3562 } slots[RTW89_MAC_MRC_MAX_ADD_SLOT_NUM];
3563 };
3564
3565 struct rtw89_h2c_mrc_upd_duration {
3566 __le32 w0;
3567 __le32 start_tsf_low;
3568 __le32 start_tsf_high;
3569 __le32 slots[];
3570 } __packed;
3571
3572 #define RTW89_H2C_MRC_UPD_DURATION_W0_SCH_IDX GENMASK(3, 0)
3573 #define RTW89_H2C_MRC_UPD_DURATION_W0_SLOT_NUM GENMASK(15, 8)
3574 #define RTW89_H2C_MRC_UPD_DURATION_W0_BTC_IN_SCH BIT(16)
3575 #define RTW89_H2C_MRC_UPD_DURATION_SLOT_SLOT_IDX GENMASK(7, 0)
3576 #define RTW89_H2C_MRC_UPD_DURATION_SLOT_DURATION GENMASK(31, 16)
3577
3578 struct rtw89_h2c_wow_aoac {
3579 __le32 w0;
3580 } __packed;
3581
3582 struct rtw89_h2c_ap_info {
3583 __le32 w0;
3584 } __packed;
3585
3586 #define RTW89_H2C_AP_INFO_W0_PWR_INT_EN BIT(0)
3587
3588 #define RTW89_C2H_HEADER_LEN 8
3589
3590 struct rtw89_c2h_hdr {
3591 __le32 w0;
3592 __le32 w1;
3593 } __packed;
3594
3595 #define RTW89_C2H_HDR_W0_CATEGORY GENMASK(1, 0)
3596 #define RTW89_C2H_HDR_W0_CLASS GENMASK(7, 2)
3597 #define RTW89_C2H_HDR_W0_FUNC GENMASK(15, 8)
3598 #define RTW89_C2H_HDR_W1_LEN GENMASK(13, 0)
3599
3600 struct rtw89_fw_c2h_attr {
3601 u8 category;
3602 u8 class;
3603 u8 func;
3604 u16 len;
3605 u8 is_scan_event: 1;
3606 u8 scan_seq: 2;
3607 };
3608
RTW89_SKB_C2H_CB(struct sk_buff * skb)3609 static inline struct rtw89_fw_c2h_attr *RTW89_SKB_C2H_CB(struct sk_buff *skb)
3610 {
3611 static_assert(sizeof(skb->cb) >= sizeof(struct rtw89_fw_c2h_attr));
3612
3613 return (struct rtw89_fw_c2h_attr *)skb->cb;
3614 }
3615
3616 struct rtw89_c2h_done_ack {
3617 __le32 w0;
3618 __le32 w1;
3619 __le32 w2;
3620 } __packed;
3621
3622 #define RTW89_C2H_DONE_ACK_W2_CAT GENMASK(1, 0)
3623 #define RTW89_C2H_DONE_ACK_W2_CLASS GENMASK(7, 2)
3624 #define RTW89_C2H_DONE_ACK_W2_FUNC GENMASK(15, 8)
3625 #define RTW89_C2H_DONE_ACK_W2_H2C_RETURN GENMASK(23, 16)
3626 #define RTW89_C2H_SCAN_DONE_ACK_RETURN GENMASK(5, 0)
3627 #define RTW89_C2H_DONE_ACK_W2_H2C_SEQ GENMASK(31, 24)
3628
3629 #define RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h) \
3630 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
3631 #define RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h) \
3632 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2))
3633 #define RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h) \
3634 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3635 #define RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h) \
3636 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16))
3637
3638 struct rtw89_fw_c2h_log_fmt {
3639 __le16 signature;
3640 u8 feature;
3641 u8 syntax;
3642 __le32 fmt_id;
3643 u8 file_num;
3644 __le16 line_num;
3645 u8 argc;
3646 union {
3647 DECLARE_FLEX_ARRAY(u8, raw);
3648 DECLARE_FLEX_ARRAY(__le32, argv);
3649 } __packed u;
3650 } __packed;
3651
3652 #define RTW89_C2H_FW_FORMATTED_LOG_MIN_LEN 11
3653 #define RTW89_C2H_FW_LOG_FEATURE_PARA_INT BIT(2)
3654 #define RTW89_C2H_FW_LOG_MAX_PARA_NUM 16
3655 #define RTW89_C2H_FW_LOG_SIGNATURE 0xA5A5
3656 #define RTW89_C2H_FW_LOG_STR_BUF_SIZE 512
3657
3658 struct rtw89_c2h_bcn_upd_done {
3659 struct rtw89_c2h_hdr hdr;
3660 __le32 w2;
3661 } __packed;
3662
3663 #define RTW89_C2H_BCN_UPD_DONE_W2_PORT GENMASK(2, 0)
3664 #define RTW89_C2H_BCN_UPD_DONE_W2_MBSSID GENMASK(6, 3)
3665 #define RTW89_C2H_BCN_UPD_DONE_W2_BAND_IDX BIT(7)
3666
3667 struct rtw89_c2h_mac_bcnfltr_rpt {
3668 __le32 w0;
3669 __le32 w1;
3670 __le32 w2;
3671 } __packed;
3672
3673 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_MACID GENMASK(7, 0)
3674 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_TYPE GENMASK(9, 8)
3675 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_EVENT GENMASK(11, 10)
3676 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_MA GENMASK(23, 16)
3677
3678 struct rtw89_c2h_ra_rpt {
3679 struct rtw89_c2h_hdr hdr;
3680 __le32 w2;
3681 __le32 w3;
3682 } __packed;
3683
3684 #define RTW89_C2H_RA_RPT_W2_MACID GENMASK(15, 0)
3685 #define RTW89_C2H_RA_RPT_W2_RETRY_RATIO GENMASK(23, 16)
3686 #define RTW89_C2H_RA_RPT_W2_MCSNSS_B7 BIT(31)
3687 #define RTW89_C2H_RA_RPT_W3_MCSNSS GENMASK(6, 0)
3688 #define RTW89_C2H_RA_RPT_W3_MD_SEL GENMASK(9, 8)
3689 #define RTW89_C2H_RA_RPT_W3_GILTF GENMASK(12, 10)
3690 #define RTW89_C2H_RA_RPT_W3_BW GENMASK(14, 13)
3691 #define RTW89_C2H_RA_RPT_W3_MD_SEL_B2 BIT(15)
3692 #define RTW89_C2H_RA_RPT_W3_BW_B2 BIT(16)
3693
3694 struct rtw89_c2h_fw_scan_rpt {
3695 struct rtw89_c2h_hdr hdr;
3696 u8 phy_idx;
3697 u8 band;
3698 u8 center_ch;
3699 u8 ofdm_pd_idx; /* in unit of 2 dBm */
3700 #define PD_LOWER_BOUND_BASE 102
3701 s8 cck_pd_idx;
3702 u8 rsvd0;
3703 u8 rsvd1;
3704 u8 rsvd2;
3705 } __packed;
3706
3707 /* For WiFi 6 chips:
3708 * VHT, HE, HT-old: [6:4]: NSS, [3:0]: MCS
3709 * HT-new: [6:5]: NA, [4:0]: MCS
3710 * For WiFi 7 chips (V1):
3711 * HT, VHT, HE, EHT: [7:5]: NSS, [4:0]: MCS
3712 */
3713 #define RTW89_RA_RATE_MASK_NSS GENMASK(6, 4)
3714 #define RTW89_RA_RATE_MASK_MCS GENMASK(3, 0)
3715 #define RTW89_RA_RATE_MASK_NSS_V1 GENMASK(7, 5)
3716 #define RTW89_RA_RATE_MASK_MCS_V1 GENMASK(4, 0)
3717 #define RTW89_RA_RATE_MASK_HT_MCS GENMASK(4, 0)
3718 #define RTW89_MK_HT_RATE(nss, mcs) (FIELD_PREP(GENMASK(4, 3), nss) | \
3719 FIELD_PREP(GENMASK(2, 0), mcs))
3720
3721 #define RTW89_GET_MAC_C2H_PKTOFLD_ID(c2h) \
3722 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0))
3723 #define RTW89_GET_MAC_C2H_PKTOFLD_OP(c2h) \
3724 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(10, 8))
3725 #define RTW89_GET_MAC_C2H_PKTOFLD_LEN(c2h) \
3726 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 16))
3727
3728 struct rtw89_c2h_scanofld {
3729 __le32 w0;
3730 __le32 w1;
3731 __le32 w2;
3732 __le32 w3;
3733 __le32 w4;
3734 __le32 w5;
3735 __le32 w6;
3736 __le32 w7;
3737 __le32 w8;
3738 } __packed;
3739
3740 #define RTW89_C2H_SCANOFLD_W2_PRI_CH GENMASK(7, 0)
3741 #define RTW89_C2H_SCANOFLD_W2_RSN GENMASK(19, 16)
3742 #define RTW89_C2H_SCANOFLD_W2_STATUS GENMASK(23, 20)
3743 #define RTW89_C2H_SCANOFLD_W2_PERIOD GENMASK(31, 24)
3744 #define RTW89_C2H_SCANOFLD_W5_TX_FAIL GENMASK(3, 0)
3745 #define RTW89_C2H_SCANOFLD_W5_AIR_DENSITY GENMASK(7, 4)
3746 #define RTW89_C2H_SCANOFLD_W5_BAND GENMASK(25, 24)
3747 #define RTW89_C2H_SCANOFLD_W5_MAC_IDX BIT(26)
3748 #define RTW89_C2H_SCANOFLD_W6_SW_DEF GENMASK(7, 0)
3749 #define RTW89_C2H_SCANOFLD_W6_EXPECT_PERIOD GENMASK(15, 8)
3750 #define RTW89_C2H_SCANOFLD_W6_FW_DEF GENMASK(23, 16)
3751 #define RTW89_C2H_SCANOFLD_W7_REPORT_TSF GENMASK(31, 0)
3752 #define RTW89_C2H_SCANOFLD_W8_PERIOD_V1 GENMASK(15, 0)
3753 #define RTW89_C2H_SCANOFLD_W8_EXPECT_PERIOD_V1 GENMASK(31, 16)
3754
3755 #define RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h) \
3756 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
3757 #define RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h) \
3758 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3759
3760 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h) \
3761 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
3762 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h) \
3763 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2))
3764 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h) \
3765 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3766
3767 struct rtw89_c2h_mac_tx_rpt {
3768 struct rtw89_c2h_hdr hdr;
3769 __le32 w2;
3770 __le32 w3;
3771 __le32 w4;
3772 __le32 w5;
3773 __le32 w6;
3774 __le32 w7;
3775 } __packed;
3776
3777 #define RTW89_C2H_MAC_TX_RPT_W2_TX_STATE GENMASK(7, 6)
3778 #define RTW89_C2H_MAC_TX_RPT_W2_SW_DEFINE GENMASK(11, 8)
3779 #define RTW89_C2H_MAC_TX_RPT_W5_DATA_TX_CNT GENMASK(13, 8)
3780 #define RTW89_C2H_MAC_TX_RPT_W5_DATA_TX_CNT_V1 GENMASK(15, 10)
3781
3782 struct rtw89_c2h_mac_tx_rpt_v2 {
3783 struct rtw89_c2h_hdr hdr;
3784 __le32 w2;
3785 __le32 w3;
3786 __le32 w4;
3787 __le32 w5;
3788 __le32 w6;
3789 __le32 w7;
3790 __le32 w8;
3791 __le32 w9;
3792 __le32 w10;
3793 __le32 w11;
3794 __le32 w12;
3795 __le32 w13;
3796 __le32 w14;
3797 __le32 w15;
3798 __le32 w16;
3799 __le32 w17;
3800 __le32 w18;
3801 __le32 w19;
3802 } __packed;
3803
3804 #define RTW89_C2H_MAC_TX_RPT_W12_TX_STATE_V2 GENMASK(9, 8)
3805 #define RTW89_C2H_MAC_TX_RPT_W12_SW_DEFINE_V2 GENMASK(15, 12)
3806 #define RTW89_C2H_MAC_TX_RPT_W14_DATA_TX_CNT_V2 GENMASK(15, 10)
3807
3808 struct rtw89_mac_mcc_tsf_rpt {
3809 u32 macid_x;
3810 u32 macid_y;
3811 u32 tsf_x_low;
3812 u32 tsf_x_high;
3813 u32 tsf_y_low;
3814 u32 tsf_y_high;
3815 };
3816
3817 static_assert(sizeof(struct rtw89_mac_mcc_tsf_rpt) <= RTW89_COMPLETION_BUF_SIZE);
3818
3819 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h) \
3820 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0))
3821 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h) \
3822 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3823 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h) \
3824 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(17, 16))
3825 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h) \
3826 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(31, 0))
3827 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h) \
3828 le32_get_bits(*((const __le32 *)(c2h) + 4), GENMASK(31, 0))
3829 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h) \
3830 le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(31, 0))
3831 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h) \
3832 le32_get_bits(*((const __le32 *)(c2h) + 6), GENMASK(31, 0))
3833
3834 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h) \
3835 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(5, 0))
3836 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h) \
3837 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 6))
3838 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h) \
3839 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3840 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h) \
3841 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(31, 0))
3842 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h) \
3843 le32_get_bits(*((const __le32 *)(c2h) + 4), GENMASK(31, 0))
3844
3845 struct rtw89_c2h_mlo_link_cfg_rpt {
3846 struct rtw89_c2h_hdr hdr;
3847 __le32 w2;
3848 } __packed;
3849
3850 #define RTW89_C2H_MLO_LINK_CFG_RPT_W2_MACID GENMASK(15, 0)
3851 #define RTW89_C2H_MLO_LINK_CFG_RPT_W2_STATUS GENMASK(19, 16)
3852
3853 enum rtw89_c2h_mlo_link_status {
3854 RTW89_C2H_MLO_LINK_CFG_IDLE = 0,
3855 RTW89_C2H_MLO_LINK_CFG_DONE = 1,
3856 RTW89_C2H_MLO_LINK_CFG_ISSUE_NULL_FAIL = 2,
3857 RTW89_C2H_MLO_LINK_CFG_TX_NULL_FAIL = 3,
3858 RTW89_C2H_MLO_LINK_CFG_ROLE_NOT_EXIST = 4,
3859 RTW89_C2H_MLO_LINK_CFG_NULL_1_TIMEOUT = 5,
3860 RTW89_C2H_MLO_LINK_CFG_NULL_0_TIMEOUT = 6,
3861 RTW89_C2H_MLO_LINK_CFG_RUNNING = 0xff,
3862 };
3863
3864 struct rtw89_mac_mrc_tsf_rpt {
3865 unsigned int num;
3866 u64 tsfs[RTW89_MAC_MRC_MAX_REQ_TSF_NUM];
3867 };
3868
3869 static_assert(sizeof(struct rtw89_mac_mrc_tsf_rpt) <= RTW89_COMPLETION_BUF_SIZE);
3870
3871 struct rtw89_c2h_mrc_tsf_rpt_info {
3872 __le32 tsf_low;
3873 __le32 tsf_high;
3874 } __packed;
3875
3876 struct rtw89_c2h_mrc_tsf_rpt {
3877 struct rtw89_c2h_hdr hdr;
3878 __le32 w2;
3879 struct rtw89_c2h_mrc_tsf_rpt_info infos[];
3880 } __packed;
3881
3882 #define RTW89_C2H_MRC_TSF_RPT_W2_REQ_TSF_NUM GENMASK(7, 0)
3883
3884 struct rtw89_c2h_mrc_status_rpt {
3885 struct rtw89_c2h_hdr hdr;
3886 __le32 w2;
3887 __le32 tsf_low;
3888 __le32 tsf_high;
3889 } __packed;
3890
3891 #define RTW89_C2H_MRC_STATUS_RPT_W2_STATUS GENMASK(5, 0)
3892 #define RTW89_C2H_MRC_STATUS_RPT_W2_SCH_IDX GENMASK(7, 6)
3893
3894 struct rtw89_c2h_pkt_ofld_rsp {
3895 __le32 w0;
3896 __le32 w1;
3897 __le32 w2;
3898 } __packed;
3899
3900 #define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_ID GENMASK(7, 0)
3901 #define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_OP GENMASK(10, 8)
3902 #define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_LEN GENMASK(31, 16)
3903
3904 struct rtw89_c2h_tx_duty_rpt {
3905 struct rtw89_c2h_hdr c2h_hdr;
3906 __le32 w2;
3907 } __packed;
3908
3909 #define RTW89_C2H_TX_DUTY_RPT_W2_TIMER_ERR GENMASK(2, 0)
3910
3911 struct rtw89_c2h_wow_aoac_report {
3912 struct rtw89_c2h_hdr c2h_hdr;
3913 u8 rpt_ver;
3914 u8 sec_type;
3915 u8 key_idx;
3916 u8 pattern_idx;
3917 u8 rekey_ok;
3918 u8 rsvd1[3];
3919 u8 ptk_tx_iv[8];
3920 u8 eapol_key_replay_count[8];
3921 u8 gtk[32];
3922 u8 ptk_rx_iv[8];
3923 u8 gtk_rx_iv[4][8];
3924 __le64 igtk_key_id;
3925 __le64 igtk_ipn;
3926 u8 igtk[32];
3927 u8 csa_pri_ch;
3928 u8 csa_bw_ch_offset;
3929 u8 csa_ch_band_chsw_failed;
3930 u8 csa_rsvd1;
3931 } __packed;
3932
3933 #define RTW89_C2H_WOW_AOAC_RPT_REKEY_IDX BIT(0)
3934
3935 struct rtw89_c2h_pwr_int_notify {
3936 struct rtw89_c2h_hdr hdr;
3937 __le32 w2;
3938 } __packed;
3939
3940 #define RTW89_C2H_PWR_INT_NOTIFY_W2_MACID GENMASK(15, 0)
3941 #define RTW89_C2H_PWR_INT_NOTIFY_W2_PWR_STATUS BIT(16)
3942
3943 struct rtw89_h2c_tx_duty {
3944 __le32 w0;
3945 __le32 w1;
3946 } __packed;
3947
3948 #define RTW89_H2C_TX_DUTY_W0_PAUSE_INTVL_MASK GENMASK(15, 0)
3949 #define RTW89_H2C_TX_DUTY_W0_TX_INTVL_MASK GENMASK(31, 16)
3950 #define RTW89_H2C_TX_DUTY_W1_STOP BIT(0)
3951
3952 struct rtw89_h2c_bcnfltr {
3953 __le32 w0;
3954 } __packed;
3955
3956 #define RTW89_H2C_BCNFLTR_W0_MON_RSSI BIT(0)
3957 #define RTW89_H2C_BCNFLTR_W0_MON_BCN BIT(1)
3958 #define RTW89_H2C_BCNFLTR_W0_MON_EN BIT(2)
3959 #define RTW89_H2C_BCNFLTR_W0_MODE GENMASK(4, 3)
3960 #define RTW89_H2C_BCNFLTR_W0_BCN_LOSS_CNT_H3 GENMASK(7, 5)
3961 #define RTW89_H2C_BCNFLTR_W0_BCN_LOSS_CNT_L4 GENMASK(11, 8)
3962 #define RTW89_H2C_BCNFLTR_W0_RSSI_HYST GENMASK(15, 12)
3963 #define RTW89_H2C_BCNFLTR_W0_RSSI_THRESHOLD GENMASK(23, 16)
3964 #define RTW89_H2C_BCNFLTR_W0_MAC_ID GENMASK(31, 24)
3965
3966 struct rtw89_h2c_ofld_rssi {
3967 __le32 w0;
3968 __le32 w1;
3969 } __packed;
3970
3971 #define RTW89_H2C_OFLD_RSSI_W0_MACID GENMASK(7, 0)
3972 #define RTW89_H2C_OFLD_RSSI_W0_NUM GENMASK(15, 8)
3973 #define RTW89_H2C_OFLD_RSSI_W1_VAL GENMASK(7, 0)
3974
3975 struct rtw89_h2c_ofld {
3976 __le32 w0;
3977 } __packed;
3978
3979 #define RTW89_H2C_OFLD_W0_MAC_ID GENMASK(7, 0)
3980 #define RTW89_H2C_OFLD_W0_TX_TP GENMASK(17, 8)
3981 #define RTW89_H2C_OFLD_W0_RX_TP GENMASK(27, 18)
3982
3983 #define RTW89_MFW_SIG 0xFF
3984
3985 struct rtw89_mfw_info {
3986 u8 cv;
3987 u8 type; /* enum rtw89_fw_type */
3988 u8 mp;
3989 u8 rsvd;
3990 __le32 shift;
3991 __le32 size;
3992 u8 rsvd2[4];
3993 } __packed;
3994
3995 struct rtw89_mfw_hdr {
3996 u8 sig; /* RTW89_MFW_SIG */
3997 u8 fw_nr;
3998 u8 rsvd0[2];
3999 struct {
4000 u8 major;
4001 u8 minor;
4002 u8 sub;
4003 u8 idx;
4004 } ver;
4005 u8 rsvd1[8];
4006 struct rtw89_mfw_info info[];
4007 } __packed;
4008
4009 struct rtw89_fw_logsuit_hdr {
4010 __le32 rsvd;
4011 __le32 count;
4012 __le32 ids[];
4013 } __packed;
4014
4015 #define RTW89_FW_ELEMENT_ALIGN 16
4016
4017 enum rtw89_fw_element_id {
4018 RTW89_FW_ELEMENT_ID_BBMCU0 = 0,
4019 RTW89_FW_ELEMENT_ID_BBMCU1 = 1,
4020 RTW89_FW_ELEMENT_ID_BB_REG = 2,
4021 RTW89_FW_ELEMENT_ID_BB_GAIN = 3,
4022 RTW89_FW_ELEMENT_ID_RADIO_A = 4,
4023 RTW89_FW_ELEMENT_ID_RADIO_B = 5,
4024 RTW89_FW_ELEMENT_ID_RADIO_C = 6,
4025 RTW89_FW_ELEMENT_ID_RADIO_D = 7,
4026 RTW89_FW_ELEMENT_ID_RF_NCTL = 8,
4027 RTW89_FW_ELEMENT_ID_TXPWR_BYRATE = 9,
4028 RTW89_FW_ELEMENT_ID_TXPWR_LMT_2GHZ = 10,
4029 RTW89_FW_ELEMENT_ID_TXPWR_LMT_5GHZ = 11,
4030 RTW89_FW_ELEMENT_ID_TXPWR_LMT_6GHZ = 12,
4031 RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_2GHZ = 13,
4032 RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_5GHZ = 14,
4033 RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_6GHZ = 15,
4034 RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT = 16,
4035 RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT_RU = 17,
4036 RTW89_FW_ELEMENT_ID_TXPWR_TRK = 18,
4037 RTW89_FW_ELEMENT_ID_RFKLOG_FMT = 19,
4038 RTW89_FW_ELEMENT_ID_REGD = 20,
4039 RTW89_FW_ELEMENT_ID_TXPWR_DA_LMT_2GHZ = 21,
4040 RTW89_FW_ELEMENT_ID_TXPWR_DA_LMT_5GHZ = 22,
4041 RTW89_FW_ELEMENT_ID_TXPWR_DA_LMT_6GHZ = 23,
4042 RTW89_FW_ELEMENT_ID_TXPWR_DA_LMT_RU_2GHZ = 24,
4043 RTW89_FW_ELEMENT_ID_TXPWR_DA_LMT_RU_5GHZ = 25,
4044 RTW89_FW_ELEMENT_ID_TXPWR_DA_LMT_RU_6GHZ = 26,
4045 RTW89_FW_ELEMENT_ID_AFE_PWR_SEQ = 27,
4046 RTW89_FW_ELEMENT_ID_DIAG_MAC = 28,
4047
4048 RTW89_FW_ELEMENT_ID_NUM,
4049 };
4050
4051 #define BITS_OF_RTW89_TXPWR_FW_ELEMENTS_NO_6GHZ \
4052 (BIT(RTW89_FW_ELEMENT_ID_TXPWR_BYRATE) | \
4053 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_2GHZ) | \
4054 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_5GHZ) | \
4055 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_2GHZ) | \
4056 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_5GHZ) | \
4057 BIT(RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT) | \
4058 BIT(RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT_RU))
4059
4060 #define BITS_OF_RTW89_TXPWR_FW_ELEMENTS \
4061 (BITS_OF_RTW89_TXPWR_FW_ELEMENTS_NO_6GHZ | \
4062 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_6GHZ) | \
4063 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_6GHZ))
4064
4065 #define RTW89_AX_GEN_DEF_NEEDED_FW_ELEMENTS_NO_6GHZ \
4066 (BIT(RTW89_FW_ELEMENT_ID_BB_REG) | \
4067 BIT(RTW89_FW_ELEMENT_ID_RADIO_A) | \
4068 BIT(RTW89_FW_ELEMENT_ID_RADIO_B) | \
4069 BIT(RTW89_FW_ELEMENT_ID_RF_NCTL) | \
4070 BIT(RTW89_FW_ELEMENT_ID_TXPWR_TRK) | \
4071 BITS_OF_RTW89_TXPWR_FW_ELEMENTS_NO_6GHZ)
4072
4073 #define RTW89_BE_GEN_DEF_NEEDED_FW_ELEMENTS (BIT(RTW89_FW_ELEMENT_ID_BBMCU0) | \
4074 BIT(RTW89_FW_ELEMENT_ID_BB_REG) | \
4075 BIT(RTW89_FW_ELEMENT_ID_RADIO_A) | \
4076 BIT(RTW89_FW_ELEMENT_ID_RADIO_B) | \
4077 BIT(RTW89_FW_ELEMENT_ID_RF_NCTL) | \
4078 BIT(RTW89_FW_ELEMENT_ID_TXPWR_TRK) | \
4079 BITS_OF_RTW89_TXPWR_FW_ELEMENTS)
4080
4081 struct __rtw89_fw_txpwr_element {
4082 u8 rsvd0;
4083 u8 rsvd1;
4084 u8 rfe_type;
4085 u8 ent_sz;
4086 __le32 num_ents;
4087 u8 content[];
4088 } __packed;
4089
4090 struct __rtw89_fw_regd_element {
4091 u8 rsvd0;
4092 u8 rsvd1;
4093 u8 rsvd2;
4094 u8 ent_sz;
4095 __le32 num_ents;
4096 u8 content[];
4097 } __packed;
4098
4099 enum rtw89_fw_txpwr_trk_type {
4100 __RTW89_FW_TXPWR_TRK_TYPE_6GHZ_START = 0,
4101 RTW89_FW_TXPWR_TRK_TYPE_6GB_N = 0,
4102 RTW89_FW_TXPWR_TRK_TYPE_6GB_P = 1,
4103 RTW89_FW_TXPWR_TRK_TYPE_6GA_N = 2,
4104 RTW89_FW_TXPWR_TRK_TYPE_6GA_P = 3,
4105 __RTW89_FW_TXPWR_TRK_TYPE_6GHZ_MAX = 3,
4106
4107 __RTW89_FW_TXPWR_TRK_TYPE_5GHZ_START = 4,
4108 RTW89_FW_TXPWR_TRK_TYPE_5GB_N = 4,
4109 RTW89_FW_TXPWR_TRK_TYPE_5GB_P = 5,
4110 RTW89_FW_TXPWR_TRK_TYPE_5GA_N = 6,
4111 RTW89_FW_TXPWR_TRK_TYPE_5GA_P = 7,
4112 __RTW89_FW_TXPWR_TRK_TYPE_5GHZ_MAX = 7,
4113
4114 __RTW89_FW_TXPWR_TRK_TYPE_2GHZ_START = 8,
4115 RTW89_FW_TXPWR_TRK_TYPE_2GB_N = 8,
4116 RTW89_FW_TXPWR_TRK_TYPE_2GB_P = 9,
4117 RTW89_FW_TXPWR_TRK_TYPE_2GA_N = 10,
4118 RTW89_FW_TXPWR_TRK_TYPE_2GA_P = 11,
4119 RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_N = 12,
4120 RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_P = 13,
4121 RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_N = 14,
4122 RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_P = 15,
4123 __RTW89_FW_TXPWR_TRK_TYPE_2GHZ_MAX = 15,
4124
4125 RTW89_FW_TXPWR_TRK_TYPE_NR,
4126 };
4127
4128 struct rtw89_fw_txpwr_track_cfg {
4129 const s8 (*delta[RTW89_FW_TXPWR_TRK_TYPE_NR])[DELTA_SWINGIDX_SIZE];
4130 };
4131
4132 #define RTW89_DEFAULT_NEEDED_FW_TXPWR_TRK_6GHZ \
4133 (BIT(RTW89_FW_TXPWR_TRK_TYPE_6GB_N) | \
4134 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GB_P) | \
4135 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GA_N) | \
4136 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GA_P))
4137 #define RTW89_DEFAULT_NEEDED_FW_TXPWR_TRK_5GHZ \
4138 (BIT(RTW89_FW_TXPWR_TRK_TYPE_5GB_N) | \
4139 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GB_P) | \
4140 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GA_N) | \
4141 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GA_P))
4142 #define RTW89_DEFAULT_NEEDED_FW_TXPWR_TRK_2GHZ \
4143 (BIT(RTW89_FW_TXPWR_TRK_TYPE_2GB_N) | \
4144 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GB_P) | \
4145 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GA_N) | \
4146 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GA_P) | \
4147 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_N) | \
4148 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_P) | \
4149 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_N) | \
4150 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_P))
4151
4152 enum rtw89_fw_afe_action {
4153 RTW89_FW_AFE_ACTION_WRITE = 0,
4154 RTW89_FW_AFE_ACTION_DELAY = 1,
4155 RTW89_FW_AFE_ACTION_POLL = 2,
4156 };
4157
4158 enum rtw89_fw_afe_cat {
4159 RTW89_FW_AFE_CAT_BB = 0,
4160 RTW89_FW_AFE_CAT_BB1 = 1,
4161 RTW89_FW_AFE_CAT_MAC = 2,
4162 RTW89_FW_AFE_CAT_MAC1 = 3,
4163 RTW89_FW_AFE_CAT_AFEDIG = 4,
4164 RTW89_FW_AFE_CAT_AFEDIG1 = 5,
4165 };
4166
4167 enum rtw89_fw_afe_class {
4168 RTW89_FW_AFE_CLASS_P0 = 0,
4169 RTW89_FW_AFE_CLASS_P1 = 1,
4170 RTW89_FW_AFE_CLASS_P2 = 2,
4171 RTW89_FW_AFE_CLASS_P3 = 3,
4172 RTW89_FW_AFE_CLASS_P4 = 4,
4173 RTW89_FW_AFE_CLASS_CMN = 5,
4174 };
4175
4176 struct rtw89_fw_element_hdr {
4177 __le32 id; /* enum rtw89_fw_element_id */
4178 __le32 size; /* exclude header size */
4179 u8 ver[4];
4180 __le32 rsvd0;
4181 __le32 rsvd1;
4182 __le32 rsvd2;
4183 union {
4184 struct {
4185 u8 priv[8];
4186 u8 contents[];
4187 } __packed common;
4188 struct {
4189 u8 idx;
4190 u8 rsvd[7];
4191 struct {
4192 __le32 addr;
4193 __le32 data;
4194 } __packed regs[];
4195 } __packed reg2;
4196 struct {
4197 u8 cv;
4198 u8 priv[7];
4199 u8 contents[];
4200 } __packed bbmcu;
4201 struct {
4202 __le32 bitmap; /* bitmap of enum rtw89_fw_txpwr_trk_type */
4203 __le32 rsvd;
4204 s8 contents[][DELTA_SWINGIDX_SIZE];
4205 } __packed txpwr_trk;
4206 struct {
4207 u8 nr;
4208 u8 rsvd[3];
4209 u8 rfk_id; /* enum rtw89_phy_c2h_rfk_log_func */
4210 u8 rsvd1[3];
4211 __le16 offset[];
4212 } __packed rfk_log_fmt;
4213 struct {
4214 u8 rsvd[8];
4215 struct rtw89_phy_afe_info {
4216 __le32 action; /* enum rtw89_fw_afe_action */
4217 __le32 cat; /* enum rtw89_fw_afe_cat */
4218 __le32 class; /* enum rtw89_fw_afe_class */
4219 __le32 addr;
4220 __le32 mask;
4221 __le32 val;
4222 } __packed infos[];
4223 } __packed afe;
4224 struct {
4225 __le32 rule_size;
4226 u8 rsvd[4];
4227 u8 rules_and_msgs[];
4228 } __packed diag_mac;
4229 struct __rtw89_fw_txpwr_element txpwr;
4230 struct __rtw89_fw_regd_element regd;
4231 } __packed u;
4232 } __packed;
4233
4234 struct fwcmd_hdr {
4235 __le32 hdr0;
4236 __le32 hdr1;
4237 };
4238
4239 union rtw89_compat_fw_hdr {
4240 struct rtw89_mfw_hdr mfw_hdr;
4241 struct rtw89_fw_hdr fw_hdr;
4242 };
4243
rtw89_compat_fw_hdr_ver_code(const void * fw_buf)4244 static inline u32 rtw89_compat_fw_hdr_ver_code(const void *fw_buf)
4245 {
4246 const union rtw89_compat_fw_hdr *compat = (typeof(compat))fw_buf;
4247
4248 if (compat->mfw_hdr.sig == RTW89_MFW_SIG)
4249 return RTW89_MFW_HDR_VER_CODE(&compat->mfw_hdr);
4250 else
4251 return RTW89_FW_HDR_VER_CODE(&compat->fw_hdr);
4252 }
4253
rtw89_fw_get_filename(char * buf,size_t size,const char * fw_basename,int fw_format)4254 static inline void rtw89_fw_get_filename(char *buf, size_t size,
4255 const char *fw_basename, int fw_format)
4256 {
4257 if (fw_format <= 0)
4258 snprintf(buf, size, "%s.bin", fw_basename);
4259 else
4260 snprintf(buf, size, "%s-%d.bin", fw_basename, fw_format);
4261 }
4262
4263 #define RTW89_H2C_RF_PAGE_SIZE 500
4264 #define RTW89_H2C_RF_PAGE_NUM 3
4265 struct rtw89_fw_h2c_rf_reg_info {
4266 enum rtw89_rf_path rf_path;
4267 __le32 rtw89_phy_config_rf_h2c[RTW89_H2C_RF_PAGE_NUM][RTW89_H2C_RF_PAGE_SIZE];
4268 u16 curr_idx;
4269 };
4270
4271 #define H2C_SEC_CAM_LEN 24
4272
4273 #define H2C_HEADER_LEN 8
4274 #define H2C_HDR_CAT GENMASK(1, 0)
4275 #define H2C_HDR_CLASS GENMASK(7, 2)
4276 #define H2C_HDR_FUNC GENMASK(15, 8)
4277 #define H2C_HDR_DEL_TYPE GENMASK(19, 16)
4278 #define H2C_HDR_H2C_SEQ GENMASK(31, 24)
4279 #define H2C_HDR_TOTAL_LEN GENMASK(13, 0)
4280 #define H2C_HDR_REC_ACK BIT(14)
4281 #define H2C_HDR_DONE_ACK BIT(15)
4282
4283 #define FWCMD_TYPE_H2C 0
4284
4285 #define H2C_CAT_TEST 0x0
4286
4287 /* CLASS 5 - FW STATUS TEST */
4288 #define H2C_CL_FW_STATUS_TEST 0x5
4289 #define H2C_FUNC_CPU_EXCEPTION 0x1
4290
4291 #define H2C_CAT_MAC 0x1
4292
4293 /* CLASS 0 - FW INFO */
4294 #define H2C_CL_FW_INFO 0x0
4295 #define H2C_FUNC_LOG_CFG 0x0
4296 #define H2C_FUNC_MAC_GENERAL_PKT 0x1
4297
4298 /* CLASS 1 - WOW */
4299 #define H2C_CL_MAC_WOW 0x1
4300 enum rtw89_wow_h2c_func {
4301 H2C_FUNC_KEEP_ALIVE = 0x0,
4302 H2C_FUNC_DISCONNECT_DETECT = 0x1,
4303 H2C_FUNC_WOW_GLOBAL = 0x2,
4304 H2C_FUNC_GTK_OFLD = 0x3,
4305 H2C_FUNC_ARP_OFLD = 0x4,
4306 H2C_FUNC_NLO = 0x7,
4307 H2C_FUNC_WAKEUP_CTRL = 0x8,
4308 H2C_FUNC_WOW_CAM_UPD = 0xC,
4309 H2C_FUNC_AOAC_REPORT_REQ = 0xD,
4310
4311 NUM_OF_RTW89_WOW_H2C_FUNC,
4312 };
4313
4314 #define RTW89_WOW_WAIT_COND(tag, func) \
4315 ((tag) * NUM_OF_RTW89_WOW_H2C_FUNC + (func))
4316
4317 #define RTW89_WOW_WAIT_COND_AOAC \
4318 RTW89_WOW_WAIT_COND(0 /* don't care */, H2C_FUNC_AOAC_REPORT_REQ)
4319
4320 /* CLASS 2 - PS */
4321 #define H2C_CL_MAC_PS 0x2
4322 enum rtw89_ps_h2c_func {
4323 H2C_FUNC_MAC_LPS_PARM = 0x0,
4324 H2C_FUNC_P2P_ACT = 0x1,
4325 H2C_FUNC_IPS_CFG = 0x3,
4326 H2C_FUNC_PS_POWER_LEVEL = 0x7,
4327 H2C_FUNC_TBTT_TUNING = 0xA,
4328
4329 NUM_OF_RTW89_PS_H2C_FUNC,
4330 };
4331
4332 #define RTW89_PS_WAIT_COND(tag, func) \
4333 ((tag) * NUM_OF_RTW89_PS_H2C_FUNC + (func))
4334
4335 #define RTW89_PS_WAIT_COND_IPS_CFG \
4336 RTW89_PS_WAIT_COND(0 /* don't care */, H2C_FUNC_IPS_CFG)
4337
4338 /* CLASS 3 - FW download */
4339 #define H2C_CL_MAC_FWDL 0x3
4340 #define H2C_FUNC_MAC_FWHDR_DL 0x0
4341
4342 /* CLASS 5 - Frame Exchange */
4343 #define H2C_CL_MAC_FR_EXCHG 0x5
4344 #define H2C_FUNC_MAC_CCTLINFO_UD 0x2
4345 #define H2C_FUNC_MAC_BCN_UPD 0x5
4346 #define H2C_FUNC_MAC_DCTLINFO_UD_V1 0x9
4347 #define H2C_FUNC_MAC_CCTLINFO_UD_V1 0xa
4348 #define H2C_FUNC_MAC_DCTLINFO_UD_V2 0xc
4349 #define H2C_FUNC_MAC_BCN_UPD_BE 0xd
4350 #define H2C_FUNC_MAC_CCTLINFO_UD_G7 0x11
4351
4352 /* CLASS 6 - Address CAM */
4353 #define H2C_CL_MAC_ADDR_CAM_UPDATE 0x6
4354 #define H2C_FUNC_MAC_ADDR_CAM_UPD 0x0
4355
4356 /* CLASS 8 - Media Status Report */
4357 #define H2C_CL_MAC_MEDIA_RPT 0x8
4358 #define H2C_FUNC_MAC_JOININFO 0x0
4359 #define H2C_FUNC_MAC_FWROLE_MAINTAIN 0x4
4360 #define H2C_FUNC_NOTIFY_DBCC 0x5
4361
4362 /* CLASS 9 - FW offload */
4363 #define H2C_CL_MAC_FW_OFLD 0x9
4364 enum rtw89_fw_ofld_h2c_func {
4365 H2C_FUNC_PACKET_OFLD = 0x1,
4366 H2C_FUNC_MAC_MACID_PAUSE = 0x8,
4367 H2C_FUNC_USR_EDCA = 0xF,
4368 H2C_FUNC_TSF32_TOGL = 0x10,
4369 H2C_FUNC_OFLD_CFG = 0x14,
4370 H2C_FUNC_ADD_SCANOFLD_CH = 0x16,
4371 H2C_FUNC_SCANOFLD = 0x17,
4372 H2C_FUNC_TX_DUTY = 0x18,
4373 H2C_FUNC_PKT_DROP = 0x1b,
4374 H2C_FUNC_CFG_BCNFLTR = 0x1e,
4375 H2C_FUNC_OFLD_RSSI = 0x1f,
4376 H2C_FUNC_OFLD_TP = 0x20,
4377 H2C_FUNC_MAC_MACID_PAUSE_SLEEP = 0x28,
4378 H2C_FUNC_SCANOFLD_BE = 0x2c,
4379
4380 NUM_OF_RTW89_FW_OFLD_H2C_FUNC,
4381 };
4382
4383 #define RTW89_FW_OFLD_WAIT_COND(tag, func) \
4384 ((tag) * NUM_OF_RTW89_FW_OFLD_H2C_FUNC + (func))
4385
4386 #define RTW89_FW_OFLD_WAIT_COND_PKT_OFLD(pkt_id, pkt_op) \
4387 RTW89_FW_OFLD_WAIT_COND(RTW89_PKT_OFLD_WAIT_TAG(pkt_id, pkt_op), \
4388 H2C_FUNC_PACKET_OFLD)
4389
4390 #define RTW89_SCANOFLD_WAIT_COND_ADD_CH RTW89_FW_OFLD_WAIT_COND(0, H2C_FUNC_ADD_SCANOFLD_CH)
4391
4392 #define RTW89_SCANOFLD_WAIT_COND_START RTW89_FW_OFLD_WAIT_COND(0, H2C_FUNC_SCANOFLD)
4393 #define RTW89_SCANOFLD_WAIT_COND_STOP RTW89_FW_OFLD_WAIT_COND(1, H2C_FUNC_SCANOFLD)
4394 #define RTW89_SCANOFLD_BE_WAIT_COND_START RTW89_FW_OFLD_WAIT_COND(0, H2C_FUNC_SCANOFLD_BE)
4395 #define RTW89_SCANOFLD_BE_WAIT_COND_STOP RTW89_FW_OFLD_WAIT_COND(1, H2C_FUNC_SCANOFLD_BE)
4396
4397
4398 /* CLASS 10 - Security CAM */
4399 #define H2C_CL_MAC_SEC_CAM 0xa
4400 #define H2C_FUNC_MAC_SEC_UPD 0x1
4401
4402 /* CLASS 12 - BA CAM */
4403 #define H2C_CL_BA_CAM 0xc
4404 #define H2C_FUNC_MAC_BA_CAM 0x0
4405 #define H2C_FUNC_MAC_BA_CAM_V1 0x1
4406 #define H2C_FUNC_MAC_BA_CAM_INIT 0x2
4407
4408 /* CLASS 14 - MCC */
4409 #define H2C_CL_MCC 0xe
4410 enum rtw89_mcc_h2c_func {
4411 H2C_FUNC_ADD_MCC = 0x0,
4412 H2C_FUNC_START_MCC = 0x1,
4413 H2C_FUNC_STOP_MCC = 0x2,
4414 H2C_FUNC_DEL_MCC_GROUP = 0x3,
4415 H2C_FUNC_RESET_MCC_GROUP = 0x4,
4416 H2C_FUNC_MCC_REQ_TSF = 0x5,
4417 H2C_FUNC_MCC_MACID_BITMAP = 0x6,
4418 H2C_FUNC_MCC_SYNC = 0x7,
4419 H2C_FUNC_MCC_SET_DURATION = 0x8,
4420
4421 NUM_OF_RTW89_MCC_H2C_FUNC,
4422 };
4423
4424 #define RTW89_MCC_WAIT_COND(group, func) \
4425 ((group) * NUM_OF_RTW89_MCC_H2C_FUNC + (func))
4426
4427 /* CLASS 20 - MLO */
4428 #define H2C_CL_MLO 0x14
4429 enum rtw89_mlo_h2c_func {
4430 H2C_FUNC_MLO_TBL_CFG = 0x0,
4431 H2C_FUNC_MLO_STA_CFG = 0x1,
4432 H2C_FUNC_MLO_TTLM = 0x2,
4433 H2C_FUNC_MLO_DM_CFG = 0x3,
4434 H2C_FUNC_MLO_EMLSR_STA_CFG = 0x4,
4435 H2C_FUNC_MLO_MCMLO_RELINK_DROP = 0x5,
4436 H2C_FUNC_MLO_MCMLO_SN_SYNC = 0x6,
4437 H2C_FUNC_MLO_RELINK = 0x7,
4438 H2C_FUNC_MLO_LINK_CFG = 0x8,
4439 H2C_FUNC_MLO_DM_DBG = 0x9,
4440
4441 NUM_OF_RTW89_MLO_H2C_FUNC,
4442 };
4443
4444 #define RTW89_MLO_WAIT_COND(macid, func) \
4445 ((macid) * NUM_OF_RTW89_MLO_H2C_FUNC + (func))
4446
4447 /* CLASS 24 - MRC */
4448 #define H2C_CL_MRC 0x18
4449 enum rtw89_mrc_h2c_func {
4450 H2C_FUNC_MRC_REQ_TSF = 0x0,
4451 H2C_FUNC_ADD_MRC = 0x1,
4452 H2C_FUNC_START_MRC = 0x2,
4453 H2C_FUNC_DEL_MRC = 0x3,
4454 H2C_FUNC_MRC_SYNC = 0x4,
4455 H2C_FUNC_MRC_UPD_DURATION = 0x5,
4456 H2C_FUNC_MRC_UPD_BITMAP = 0x6,
4457
4458 NUM_OF_RTW89_MRC_H2C_FUNC,
4459 };
4460
4461 /* can consider MRC's sch_idx as MCC's group */
4462 #define RTW89_MRC_WAIT_COND(sch_idx, func) \
4463 ((sch_idx) * NUM_OF_RTW89_MRC_H2C_FUNC + (func))
4464
4465 #define RTW89_MRC_WAIT_COND_REQ_TSF \
4466 RTW89_MRC_WAIT_COND(0 /* don't care */, H2C_FUNC_MRC_REQ_TSF)
4467
4468 /* CLASS 36 - AP */
4469 #define H2C_CL_AP 0x24
4470 #define H2C_FUNC_AP_INFO 0x0
4471
4472 #define H2C_CAT_OUTSRC 0x2
4473
4474 #define H2C_CL_OUTSRC_RA 0x1
4475 #define H2C_FUNC_OUTSRC_RA_MACIDCFG 0x0
4476
4477 #define H2C_CL_OUTSRC_DM 0x2
4478 #define H2C_FUNC_FW_MCC_DIG 0x6
4479 #define H2C_FUNC_FW_LPS_CH_INFO 0xb
4480 #define H2C_FUNC_FW_LPS_ML_CMN_INFO 0xe
4481
4482 #define H2C_CL_OUTSRC_RF_REG_A 0x8
4483 #define H2C_CL_OUTSRC_RF_REG_B 0x9
4484 #define H2C_CL_OUTSRC_RF_FW_NOTIFY 0xa
4485 #define H2C_FUNC_OUTSRC_RF_GET_MCCCH 0x2
4486 #define H2C_FUNC_OUTSRC_RF_PS_INFO 0x10
4487 #define H2C_CL_OUTSRC_RF_FW_RFK 0xb
4488
4489 enum rtw89_rfk_offload_h2c_func {
4490 H2C_FUNC_RFK_TSSI_OFFLOAD = 0x0,
4491 H2C_FUNC_RFK_IQK_OFFLOAD = 0x1,
4492 H2C_FUNC_RFK_DPK_OFFLOAD = 0x3,
4493 H2C_FUNC_RFK_TXGAPK_OFFLOAD = 0x4,
4494 H2C_FUNC_RFK_DACK_OFFLOAD = 0x5,
4495 H2C_FUNC_RFK_RXDCK_OFFLOAD = 0x6,
4496 H2C_FUNC_RFK_PRE_NOTIFY = 0x8,
4497 H2C_FUNC_RFK_TAS_OFFLOAD = 0x9,
4498 };
4499
4500 struct rtw89_fw_h2c_rf_get_mccch {
4501 __le32 ch_0_0;
4502 __le32 ch_0_1;
4503 __le32 ch_1_0;
4504 __le32 ch_1_1;
4505 __le32 current_channel;
4506 } __packed;
4507
4508 struct rtw89_fw_h2c_rf_get_mccch_v0 {
4509 __le32 ch_0;
4510 __le32 ch_1;
4511 __le32 band_0;
4512 __le32 band_1;
4513 __le32 current_channel;
4514 __le32 current_band_type;
4515 } __packed;
4516
4517 struct rtw89_h2c_mcc_dig {
4518 __le32 w0;
4519 __le32 w1;
4520 __le32 w2;
4521 } __packed;
4522
4523 #define RTW89_H2C_MCC_DIG_W0_REG_CNT GENMASK(7, 0)
4524 #define RTW89_H2C_MCC_DIG_W0_DM_EN BIT(8)
4525 #define RTW89_H2C_MCC_DIG_W0_IDX GENMASK(10, 9)
4526 #define RTW89_H2C_MCC_DIG_W0_SET BIT(11)
4527 #define RTW89_H2C_MCC_DIG_W0_PHY0_EN BIT(12)
4528 #define RTW89_H2C_MCC_DIG_W0_PHY1_EN BIT(13)
4529 #define RTW89_H2C_MCC_DIG_W0_CENTER_CH GENMASK(23, 16)
4530 #define RTW89_H2C_MCC_DIG_W0_BAND_TYPE GENMASK(31, 24)
4531 #define RTW89_H2C_MCC_DIG_W1_ADDR_LSB GENMASK(7, 0)
4532 #define RTW89_H2C_MCC_DIG_W1_ADDR_MSB GENMASK(15, 8)
4533 #define RTW89_H2C_MCC_DIG_W1_BMASK_LSB GENMASK(23, 16)
4534 #define RTW89_H2C_MCC_DIG_W1_BMASK_MSB GENMASK(31, 24)
4535 #define RTW89_H2C_MCC_DIG_W2_VAL_LSB GENMASK(7, 0)
4536 #define RTW89_H2C_MCC_DIG_W2_VAL_MSB GENMASK(15, 8)
4537
4538 #define NUM_OF_RTW89_FW_RFK_PATH 2
4539 #define NUM_OF_RTW89_FW_RFK_TBL 3
4540
4541 struct rtw89_h2c_rf_ps_info {
4542 __le32 rf18[NUM_OF_RTW89_FW_RFK_PATH];
4543 __le32 mlo_mode;
4544 u8 pri_ch[NUM_OF_RTW89_FW_RFK_PATH];
4545 } __packed;
4546
4547 struct rtw89_fw_h2c_rfk_pre_info_common {
4548 struct {
4549 __le32 ch[NUM_OF_RTW89_FW_RFK_PATH][NUM_OF_RTW89_FW_RFK_TBL];
4550 __le32 band[NUM_OF_RTW89_FW_RFK_PATH][NUM_OF_RTW89_FW_RFK_TBL];
4551 } __packed dbcc;
4552
4553 __le32 mlo_mode;
4554 struct {
4555 __le32 cur_ch[NUM_OF_RTW89_FW_RFK_PATH];
4556 __le32 cur_band[NUM_OF_RTW89_FW_RFK_PATH];
4557 } __packed tbl;
4558
4559 __le32 phy_idx;
4560 } __packed;
4561
4562 struct rtw89_fw_h2c_rfk_pre_info_v0 {
4563 struct rtw89_fw_h2c_rfk_pre_info_common common;
4564
4565 __le32 cur_band;
4566 __le32 cur_bw;
4567 __le32 cur_center_ch;
4568
4569 __le32 ktbl_sel0;
4570 __le32 ktbl_sel1;
4571 __le32 rfmod0;
4572 __le32 rfmod1;
4573
4574 __le32 mlo_1_1;
4575 __le32 rfe_type;
4576 __le32 drv_mode;
4577
4578 struct {
4579 __le32 ch[NUM_OF_RTW89_FW_RFK_PATH];
4580 __le32 band[NUM_OF_RTW89_FW_RFK_PATH];
4581 } __packed mlo;
4582 } __packed;
4583
4584 struct rtw89_fw_h2c_rfk_pre_info_v1 {
4585 struct rtw89_fw_h2c_rfk_pre_info_common common;
4586 __le32 mlo_1_1;
4587 } __packed;
4588
4589 struct rtw89_fw_h2c_rfk_pre_info {
4590 struct rtw89_fw_h2c_rfk_pre_info_v1 base_v1;
4591 __le32 cur_bandwidth[NUM_OF_RTW89_FW_RFK_PATH];
4592 } __packed;
4593
4594 struct rtw89_h2c_rf_tssi {
4595 __le16 len;
4596 u8 phy;
4597 u8 ch;
4598 u8 bw;
4599 u8 band;
4600 u8 hwtx_en;
4601 u8 cv;
4602 s8 curr_tssi_cck_de[2];
4603 s8 curr_tssi_cck_de_20m[2];
4604 s8 curr_tssi_cck_de_40m[2];
4605 s8 curr_tssi_efuse_cck_de[2];
4606 s8 curr_tssi_ofdm_de[2];
4607 s8 curr_tssi_ofdm_de_20m[2];
4608 s8 curr_tssi_ofdm_de_40m[2];
4609 s8 curr_tssi_ofdm_de_80m[2];
4610 s8 curr_tssi_ofdm_de_160m[2];
4611 s8 curr_tssi_ofdm_de_320m[2];
4612 s8 curr_tssi_efuse_ofdm_de[2];
4613 s8 curr_tssi_ofdm_de_diff_20m[2];
4614 s8 curr_tssi_ofdm_de_diff_80m[2];
4615 s8 curr_tssi_ofdm_de_diff_160m[2];
4616 s8 curr_tssi_ofdm_de_diff_320m[2];
4617 s8 curr_tssi_trim_de[2];
4618 u8 pg_thermal[2];
4619 u8 ftable[2][128];
4620 u8 tssi_mode;
4621 u8 rfe_type;
4622 } __packed;
4623
4624 struct rtw89_h2c_rf_iqk_v0 {
4625 __le32 phy_idx;
4626 __le32 dbcc;
4627 } __packed;
4628
4629 struct rtw89_h2c_rf_iqk {
4630 u8 len;
4631 u8 ktype;
4632 u8 phy;
4633 u8 kpath;
4634 u8 band;
4635 u8 bw;
4636 u8 ch;
4637 u8 cv;
4638 } __packed;
4639
4640 struct rtw89_h2c_rf_dpk {
4641 u8 len;
4642 u8 phy;
4643 u8 dpk_enable;
4644 u8 kpath;
4645 u8 cur_band;
4646 u8 cur_bw;
4647 u8 cur_ch;
4648 u8 dpk_dbg_en;
4649 } __packed;
4650
4651 struct rtw89_h2c_rf_txgapk {
4652 u8 len;
4653 u8 ktype;
4654 u8 phy;
4655 u8 kpath;
4656 u8 band;
4657 u8 bw;
4658 u8 ch;
4659 u8 cv;
4660 } __packed;
4661
4662 struct rtw89_h2c_rf_dack {
4663 __le32 len;
4664 __le32 phy;
4665 __le32 type;
4666 } __packed;
4667
4668 struct rtw89_h2c_rf_rxdck_v0 {
4669 u8 len;
4670 u8 phy;
4671 u8 is_afe;
4672 u8 kpath;
4673 u8 cur_band;
4674 u8 cur_bw;
4675 u8 cur_ch;
4676 u8 rxdck_dbg_en;
4677 } __packed;
4678
4679 struct rtw89_h2c_rf_tas {
4680 __le32 enable;
4681 } __packed;
4682
4683 struct rtw89_h2c_rf_rxdck {
4684 struct rtw89_h2c_rf_rxdck_v0 v0;
4685 u8 is_chl_k;
4686 } __packed;
4687
4688 enum rtw89_rf_log_type {
4689 RTW89_RF_RUN_LOG = 0,
4690 RTW89_RF_RPT_LOG = 1,
4691 };
4692
4693 struct rtw89_c2h_rf_log_hdr {
4694 u8 type; /* enum rtw89_rf_log_type */
4695 __le16 len;
4696 u8 content[];
4697 } __packed;
4698
4699 struct rtw89_c2h_rf_run_log {
4700 __le32 fmt_idx;
4701 __le32 arg[4];
4702 } __packed;
4703
4704 struct rtw89_c2h_rf_iqk_rpt_log {
4705 bool iqk_tx_fail[2];
4706 bool iqk_rx_fail[2];
4707 bool is_iqk_init;
4708 bool is_reload;
4709 bool is_wb_txiqk[2];
4710 bool is_wb_rxiqk[2];
4711 bool is_nbiqk;
4712 bool txiqk_en;
4713 bool rxiqk_en;
4714 bool lok_en;
4715 bool iqk_xym_en;
4716 bool iqk_sram_en;
4717 bool iqk_fft_en;
4718 bool is_fw_iqk;
4719 bool is_iqk_enable;
4720 bool iqk_cfir_en;
4721 bool thermal_rek_en;
4722 u8 iqk_band[2];
4723 u8 iqk_ch[2];
4724 u8 iqk_bw[2];
4725 u8 iqk_times;
4726 u8 version;
4727 u8 phy;
4728 u8 fwk_status;
4729 u8 rsvd;
4730 __le32 reload_cnt;
4731 __le32 iqk_fail_cnt;
4732 __le32 lok_idac[2];
4733 __le32 lok_vbuf[2];
4734 __le32 rftxgain[2][4];
4735 __le32 rfrxgain[2][4];
4736 __le32 tx_xym[2][4];
4737 __le32 rx_xym[2][4];
4738 } __packed;
4739
4740 struct rtw89_c2h_rf_dpk_rpt_log {
4741 u8 ver;
4742 u8 idx[2];
4743 u8 band[2];
4744 u8 bw[2];
4745 u8 ch[2];
4746 u8 path_ok[2];
4747 u8 txagc[2];
4748 u8 ther[2];
4749 u8 gs[2];
4750 u8 dc_i[4];
4751 u8 dc_q[4];
4752 u8 corr_val[2];
4753 u8 corr_idx[2];
4754 u8 is_timeout[2];
4755 u8 rxbb_ov[2];
4756 u8 rsvd;
4757 } __packed;
4758
4759 struct rtw89_c2h_rf_dack_rpt_log {
4760 u8 fwdack_ver;
4761 u8 fwdack_info_ver;
4762 u8 msbk_d[2][2][16];
4763 u8 dadck_d[2][2];
4764 u8 cdack_d[2][2][2];
4765 u8 addck2_hd[2][2][2];
4766 u8 addck2_ld[2][2][2];
4767 u8 adgaink_d[2][2];
4768 u8 biask_hd[2][2];
4769 u8 biask_ld[2][2];
4770 u8 addck_timeout;
4771 u8 cdack_timeout;
4772 u8 dadck_timeout;
4773 u8 msbk_timeout;
4774 u8 adgaink_timeout;
4775 u8 wbadcdck_timeout;
4776 u8 drck_timeout;
4777 u8 dack_fail;
4778 u8 wbdck_d[2];
4779 u8 rck_d;
4780 } __packed;
4781
4782 struct rtw89_c2h_rf_rxdck_rpt_log {
4783 u8 ver;
4784 u8 band[2];
4785 u8 bw[2];
4786 u8 ch[2];
4787 u8 timeout[2];
4788 } __packed;
4789
4790 struct rtw89_c2h_rf_tssi_rpt_log {
4791 s8 alignment_power[2][2][4];
4792 u8 alignment_power_cw_h[2][2][4];
4793 u8 alignment_power_cw_l[2][2][4];
4794 u8 tssi_alimk_state[2][2];
4795 u8 default_txagc_offset[2][2];
4796 } __packed;
4797
4798 struct rtw89_c2h_rf_txgapk_rpt_log {
4799 __le32 r0x8010[2];
4800 __le32 chk_cnt;
4801 u8 track_d[2][17];
4802 u8 power_d[2][17];
4803 u8 is_txgapk_ok;
4804 u8 chk_id;
4805 u8 ver;
4806 u8 rsv1;
4807 } __packed;
4808
4809 struct rtw89_c2h_rfk_report {
4810 struct rtw89_c2h_hdr hdr;
4811 u8 state; /* enum rtw89_rfk_report_state */
4812 u8 version;
4813 } __packed;
4814
4815 struct rtw89_c2h_rf_tas_rpt_log {
4816 __le32 cur_idx;
4817 __le16 txpwr_history[20];
4818 } __packed;
4819
4820 struct rtw89_c2h_rf_tas_info {
4821 struct rtw89_c2h_hdr hdr;
4822 struct rtw89_c2h_rf_tas_rpt_log content;
4823 } __packed;
4824
4825 #define RTW89_FW_RSVD_PLE_SIZE 0x800
4826
4827 #define RTW89_FW_BACKTRACE_INFO_SIZE 8
4828 #define RTW89_VALID_FW_BACKTRACE_SIZE(_size) \
4829 ((_size) % RTW89_FW_BACKTRACE_INFO_SIZE == 0)
4830
4831 #define RTW89_FW_BACKTRACE_MAX_SIZE 512 /* 8 * 64 (entries) */
4832 #define RTW89_FW_BACKTRACE_KEY 0xBACEBACE
4833
4834 #define FWDL_WAIT_CNT 400000
4835 #define FWDL_WAIT_CNT_USB 3200
4836
4837 int rtw89_fw_check_rdy(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type);
4838 int rtw89_fw_recognize(struct rtw89_dev *rtwdev);
4839 int rtw89_fw_recognize_elements(struct rtw89_dev *rtwdev);
4840 const struct firmware *
4841 rtw89_early_fw_feature_recognize(struct device *device,
4842 const struct rtw89_chip_info *chip,
4843 struct rtw89_fw_info *early_fw,
4844 int *used_fw_format);
4845 int rtw89_fw_download(struct rtw89_dev *rtwdev, enum rtw89_fw_type type,
4846 bool include_bb);
4847 void rtw89_load_firmware_work(struct work_struct *work);
4848 void rtw89_unload_firmware(struct rtw89_dev *rtwdev);
4849 int rtw89_wait_firmware_completion(struct rtw89_dev *rtwdev);
4850 int rtw89_fw_log_prepare(struct rtw89_dev *rtwdev);
4851 void rtw89_fw_log_dump(struct rtw89_dev *rtwdev, u8 *buf, u32 len);
4852 void rtw89_h2c_pkt_set_hdr(struct rtw89_dev *rtwdev, struct sk_buff *skb,
4853 u8 type, u8 cat, u8 class, u8 func,
4854 bool rack, bool dack, u32 len);
4855 int rtw89_fw_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev,
4856 struct rtw89_vif_link *rtwvif_link,
4857 struct rtw89_sta_link *rtwsta_link);
4858 int rtw89_fw_h2c_default_cmac_tbl_g7(struct rtw89_dev *rtwdev,
4859 struct rtw89_vif_link *rtwvif_link,
4860 struct rtw89_sta_link *rtwsta_link);
4861 int rtw89_fw_h2c_default_dmac_tbl_v2(struct rtw89_dev *rtwdev,
4862 struct rtw89_vif_link *rtwvif_link,
4863 struct rtw89_sta_link *rtwsta_link);
4864 int rtw89_fw_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev,
4865 struct rtw89_vif_link *rtwvif_link,
4866 struct rtw89_sta_link *rtwsta_link);
4867 int rtw89_fw_h2c_assoc_cmac_tbl_g7(struct rtw89_dev *rtwdev,
4868 struct rtw89_vif_link *rtwvif_link,
4869 struct rtw89_sta_link *rtwsta_link);
4870 int rtw89_fw_h2c_ampdu_cmac_tbl_g7(struct rtw89_dev *rtwdev,
4871 struct rtw89_vif_link *rtwvif_link,
4872 struct rtw89_sta_link *rtwsta_link);
4873 int rtw89_fw_h2c_txtime_cmac_tbl(struct rtw89_dev *rtwdev,
4874 struct rtw89_sta_link *rtwsta_link);
4875 int rtw89_fw_h2c_txtime_cmac_tbl_g7(struct rtw89_dev *rtwdev,
4876 struct rtw89_sta_link *rtwsta_link);
4877 int rtw89_fw_h2c_punctured_cmac_tbl_g7(struct rtw89_dev *rtwdev,
4878 struct rtw89_vif_link *rtwvif_link,
4879 u16 punctured);
4880 int rtw89_fw_h2c_txpath_cmac_tbl(struct rtw89_dev *rtwdev,
4881 struct rtw89_sta_link *rtwsta_link);
4882 int rtw89_fw_h2c_update_beacon(struct rtw89_dev *rtwdev,
4883 struct rtw89_vif_link *rtwvif_link);
4884 int rtw89_fw_h2c_update_beacon_be(struct rtw89_dev *rtwdev,
4885 struct rtw89_vif_link *rtwvif_link);
4886 int rtw89_fw_h2c_tbtt_tuning(struct rtw89_dev *rtwdev,
4887 struct rtw89_vif_link *rtwvif_link, u32 offset);
4888 int rtw89_fw_h2c_pwr_lvl(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link);
4889 int rtw89_fw_h2c_cam(struct rtw89_dev *rtwdev, struct rtw89_vif_link *vif,
4890 struct rtw89_sta_link *rtwsta_link, const u8 *scan_mac_addr,
4891 enum rtw89_upd_mode upd_mode);
4892 int rtw89_fw_h2c_dctl_sec_cam_v1(struct rtw89_dev *rtwdev,
4893 struct rtw89_vif_link *rtwvif_link,
4894 struct rtw89_sta_link *rtwsta_link);
4895 int rtw89_fw_h2c_dctl_sec_cam_v2(struct rtw89_dev *rtwdev,
4896 struct rtw89_vif_link *rtwvif_link,
4897 struct rtw89_sta_link *rtwsta_link);
4898 void rtw89_fw_c2h_irqsafe(struct rtw89_dev *rtwdev, struct sk_buff *c2h);
4899 void rtw89_fw_c2h_work(struct wiphy *wiphy, struct wiphy_work *work);
4900 void rtw89_fw_c2h_purge_obsoleted_scan_events(struct rtw89_dev *rtwdev);
4901 int rtw89_fw_h2c_role_maintain(struct rtw89_dev *rtwdev,
4902 struct rtw89_vif_link *rtwvif_link,
4903 struct rtw89_sta_link *rtwsta_link,
4904 enum rtw89_upd_mode upd_mode);
4905 int rtw89_fw_h2c_join_info(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4906 struct rtw89_sta_link *rtwsta_link, bool dis_conn);
4907 int rtw89_fw_h2c_notify_dbcc(struct rtw89_dev *rtwdev, bool en);
4908 int rtw89_fw_h2c_macid_pause(struct rtw89_dev *rtwdev, u8 sh, u8 grp,
4909 bool pause);
4910 int rtw89_fw_h2c_set_edca(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4911 u8 ac, u32 val);
4912 int rtw89_fw_h2c_set_ofld_cfg(struct rtw89_dev *rtwdev);
4913 int rtw89_fw_h2c_tx_duty(struct rtw89_dev *rtwdev, u8 lv);
4914 int rtw89_fw_h2c_set_bcn_fltr_cfg(struct rtw89_dev *rtwdev,
4915 struct rtw89_vif_link *rtwvif_link,
4916 bool connect);
4917 int rtw89_fw_h2c_rssi_offload(struct rtw89_dev *rtwdev,
4918 struct rtw89_rx_phy_ppdu *phy_ppdu);
4919 int rtw89_fw_h2c_tp_offload(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link);
4920 int rtw89_fw_h2c_ra(struct rtw89_dev *rtwdev, struct rtw89_ra_info *ra, bool csi);
4921 int rtw89_fw_h2c_cxdrv_init(struct rtw89_dev *rtwdev, u8 type);
4922 int rtw89_fw_h2c_cxdrv_init_v7(struct rtw89_dev *rtwdev, u8 type);
4923 int rtw89_fw_h2c_cxdrv_role(struct rtw89_dev *rtwdev, u8 type);
4924 int rtw89_fw_h2c_cxdrv_role_v1(struct rtw89_dev *rtwdev, u8 type);
4925 int rtw89_fw_h2c_cxdrv_role_v2(struct rtw89_dev *rtwdev, u8 type);
4926 int rtw89_fw_h2c_cxdrv_role_v7(struct rtw89_dev *rtwdev, u8 type);
4927 int rtw89_fw_h2c_cxdrv_role_v8(struct rtw89_dev *rtwdev, u8 type);
4928 int rtw89_fw_h2c_cxdrv_osi_info(struct rtw89_dev *rtwdev, u8 type);
4929 int rtw89_fw_h2c_cxdrv_ctrl(struct rtw89_dev *rtwdev, u8 type);
4930 int rtw89_fw_h2c_cxdrv_ctrl_v7(struct rtw89_dev *rtwdev, u8 type);
4931 int rtw89_fw_h2c_cxdrv_trx(struct rtw89_dev *rtwdev, u8 type);
4932 int rtw89_fw_h2c_cxdrv_rfk(struct rtw89_dev *rtwdev, u8 type);
4933 int rtw89_fw_h2c_del_pkt_offload(struct rtw89_dev *rtwdev, u8 id);
4934 int rtw89_fw_h2c_add_pkt_offload(struct rtw89_dev *rtwdev, u8 *id,
4935 struct sk_buff *skb_ofld);
4936 int rtw89_fw_h2c_scan_offload_ax(struct rtw89_dev *rtwdev,
4937 struct rtw89_scan_option *opt,
4938 struct rtw89_vif_link *vif,
4939 bool wowlan);
4940 int rtw89_fw_h2c_scan_offload_be(struct rtw89_dev *rtwdev,
4941 struct rtw89_scan_option *opt,
4942 struct rtw89_vif_link *vif,
4943 bool wowlan);
4944 int rtw89_fw_h2c_rf_reg(struct rtw89_dev *rtwdev,
4945 struct rtw89_fw_h2c_rf_reg_info *info,
4946 u16 len, u8 page);
4947 int rtw89_fw_h2c_rf_ntfy_mcc(struct rtw89_dev *rtwdev);
4948 int rtw89_fw_h2c_rf_ps_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
4949 int rtw89_fw_h2c_rf_pre_ntfy(struct rtw89_dev *rtwdev,
4950 enum rtw89_phy_idx phy_idx);
4951 int rtw89_fw_h2c_mcc_dig(struct rtw89_dev *rtwdev,
4952 enum rtw89_chanctx_idx chanctx_idx,
4953 u8 mcc_role_idx, u8 pd_val, bool en);
4954 int rtw89_fw_h2c_rf_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
4955 const struct rtw89_chan *chan, enum rtw89_tssi_mode tssi_mode);
4956 int rtw89_fw_h2c_rf_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
4957 const struct rtw89_chan *chan);
4958 int rtw89_fw_h2c_rf_dpk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
4959 const struct rtw89_chan *chan);
4960 int rtw89_fw_h2c_rf_txgapk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
4961 const struct rtw89_chan *chan);
4962 int rtw89_fw_h2c_rf_dack(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
4963 const struct rtw89_chan *chan);
4964 int rtw89_fw_h2c_rf_rxdck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
4965 const struct rtw89_chan *chan, bool is_chl_k);
4966 int rtw89_fw_h2c_rf_tas_trigger(struct rtw89_dev *rtwdev, bool enable);
4967 int rtw89_fw_h2c_raw_with_hdr(struct rtw89_dev *rtwdev,
4968 u8 h2c_class, u8 h2c_func, u8 *buf, u16 len,
4969 bool rack, bool dack);
4970 int rtw89_fw_h2c_raw(struct rtw89_dev *rtwdev, const u8 *buf, u16 len);
4971 void rtw89_fw_send_all_early_h2c(struct rtw89_dev *rtwdev);
4972 void __rtw89_fw_free_all_early_h2c(struct rtw89_dev *rtwdev);
4973 void rtw89_fw_free_all_early_h2c(struct rtw89_dev *rtwdev);
4974 int rtw89_fw_h2c_general_pkt(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4975 u8 macid);
4976 void rtw89_fw_release_general_pkt_list_vif(struct rtw89_dev *rtwdev,
4977 struct rtw89_vif_link *rtwvif_link,
4978 bool notify_fw);
4979 void rtw89_fw_release_general_pkt_list(struct rtw89_dev *rtwdev, bool notify_fw);
4980 int rtw89_fw_h2c_ba_cam(struct rtw89_dev *rtwdev,
4981 struct rtw89_vif_link *rtwvif_link,
4982 struct rtw89_sta_link *rtwsta_link,
4983 bool valid, struct ieee80211_ampdu_params *params);
4984 int rtw89_fw_h2c_ba_cam_v1(struct rtw89_dev *rtwdev,
4985 struct rtw89_vif_link *rtwvif_link,
4986 struct rtw89_sta_link *rtwsta_link,
4987 bool valid, struct ieee80211_ampdu_params *params);
4988 void rtw89_fw_h2c_init_dynamic_ba_cam_v0_ext(struct rtw89_dev *rtwdev);
4989 int rtw89_fw_h2c_init_ba_cam_users(struct rtw89_dev *rtwdev, u8 users,
4990 u8 offset, u8 mac_idx);
4991
4992 int rtw89_fw_h2c_lps_parm(struct rtw89_dev *rtwdev,
4993 struct rtw89_lps_parm *lps_param);
4994 int rtw89_fw_h2c_lps_ch_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
4995 int rtw89_fw_h2c_lps_ml_cmn_info(struct rtw89_dev *rtwdev,
4996 struct rtw89_vif *rtwvif);
4997 int rtw89_fw_h2c_fwips(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4998 bool enable);
4999 struct sk_buff *rtw89_fw_h2c_alloc_skb_with_hdr(struct rtw89_dev *rtwdev, u32 len);
5000 struct sk_buff *rtw89_fw_h2c_alloc_skb_no_hdr(struct rtw89_dev *rtwdev, u32 len);
5001 int rtw89_fw_msg_reg(struct rtw89_dev *rtwdev,
5002 struct rtw89_mac_h2c_info *h2c_info,
5003 struct rtw89_mac_c2h_info *c2h_info);
5004 int rtw89_fw_h2c_fw_log(struct rtw89_dev *rtwdev, bool enable);
5005 void rtw89_fw_st_dbg_dump(struct rtw89_dev *rtwdev);
5006 int rtw89_hw_scan_start(struct rtw89_dev *rtwdev,
5007 struct rtw89_vif_link *rtwvif_link,
5008 struct ieee80211_scan_request *scan_req);
5009 void rtw89_hw_scan_complete(struct rtw89_dev *rtwdev,
5010 struct rtw89_vif_link *rtwvif_link,
5011 bool aborted);
5012 int rtw89_hw_scan_offload(struct rtw89_dev *rtwdev,
5013 struct rtw89_vif_link *rtwvif_link,
5014 bool enable);
5015 void rtw89_hw_scan_abort(struct rtw89_dev *rtwdev,
5016 struct rtw89_vif_link *rtwvif_link);
5017 int rtw89_hw_scan_prep_chan_list_ax(struct rtw89_dev *rtwdev,
5018 struct rtw89_vif_link *rtwvif_link);
5019 void rtw89_hw_scan_free_chan_list_ax(struct rtw89_dev *rtwdev);
5020 int rtw89_hw_scan_add_chan_list_ax(struct rtw89_dev *rtwdev,
5021 struct rtw89_vif_link *rtwvif_link);
5022 int rtw89_pno_scan_add_chan_list_ax(struct rtw89_dev *rtwdev,
5023 struct rtw89_vif_link *rtwvif_link);
5024 int rtw89_hw_scan_prep_chan_list_be(struct rtw89_dev *rtwdev,
5025 struct rtw89_vif_link *rtwvif_link);
5026 void rtw89_hw_scan_free_chan_list_be(struct rtw89_dev *rtwdev);
5027 int rtw89_hw_scan_add_chan_list_be(struct rtw89_dev *rtwdev,
5028 struct rtw89_vif_link *rtwvif_link);
5029 int rtw89_pno_scan_add_chan_list_be(struct rtw89_dev *rtwdev,
5030 struct rtw89_vif_link *rtwvif_link);
5031 int rtw89_fw_h2c_trigger_cpu_exception(struct rtw89_dev *rtwdev);
5032 int rtw89_fw_h2c_pkt_drop(struct rtw89_dev *rtwdev,
5033 const struct rtw89_pkt_drop_params *params);
5034 int rtw89_fw_h2c_p2p_act(struct rtw89_dev *rtwdev,
5035 struct rtw89_vif_link *rtwvif_link,
5036 struct ieee80211_p2p_noa_desc *desc,
5037 u8 act, u8 noa_id, u8 ctwindow_oppps);
5038 int rtw89_fw_h2c_tsf32_toggle(struct rtw89_dev *rtwdev,
5039 struct rtw89_vif_link *rtwvif_link,
5040 bool en);
5041 int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
5042 bool enable);
5043 int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev,
5044 struct rtw89_vif_link *rtwvif_link, bool enable);
5045 int rtw89_fw_h2c_cfg_pno(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
5046 bool enable);
5047 int rtw89_fw_h2c_keep_alive(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
5048 bool enable);
5049 int rtw89_fw_h2c_arp_offload(struct rtw89_dev *rtwdev,
5050 struct rtw89_vif_link *rtwvif_link, bool enable);
5051 int rtw89_fw_h2c_disconnect_detect(struct rtw89_dev *rtwdev,
5052 struct rtw89_vif_link *rtwvif_link, bool enable);
5053 int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
5054 bool enable);
5055 int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev,
5056 struct rtw89_vif_link *rtwvif_link, bool enable);
5057 int rtw89_fw_wow_cam_update(struct rtw89_dev *rtwdev,
5058 struct rtw89_wow_cam_info *cam_info);
5059 int rtw89_fw_h2c_wow_gtk_ofld(struct rtw89_dev *rtwdev,
5060 struct rtw89_vif_link *rtwvif_link,
5061 bool enable);
5062 int rtw89_fw_h2c_wow_request_aoac(struct rtw89_dev *rtwdev);
5063 int rtw89_fw_h2c_add_mcc(struct rtw89_dev *rtwdev,
5064 const struct rtw89_fw_mcc_add_req *p);
5065 int rtw89_fw_h2c_start_mcc(struct rtw89_dev *rtwdev,
5066 const struct rtw89_fw_mcc_start_req *p);
5067 int rtw89_fw_h2c_stop_mcc(struct rtw89_dev *rtwdev, u8 group, u8 macid,
5068 bool prev_groups);
5069 int rtw89_fw_h2c_del_mcc_group(struct rtw89_dev *rtwdev, u8 group,
5070 bool prev_groups);
5071 int rtw89_fw_h2c_reset_mcc_group(struct rtw89_dev *rtwdev, u8 group);
5072 int rtw89_fw_h2c_mcc_req_tsf(struct rtw89_dev *rtwdev,
5073 const struct rtw89_fw_mcc_tsf_req *req,
5074 struct rtw89_mac_mcc_tsf_rpt *rpt);
5075 int rtw89_fw_h2c_mcc_macid_bitmap(struct rtw89_dev *rtwdev, u8 group, u8 macid,
5076 u8 *bitmap);
5077 int rtw89_fw_h2c_mcc_sync(struct rtw89_dev *rtwdev, u8 group, u8 source,
5078 u8 target, u8 offset);
5079 int rtw89_fw_h2c_mcc_set_duration(struct rtw89_dev *rtwdev,
5080 const struct rtw89_fw_mcc_duration *p);
5081 int rtw89_fw_h2c_mrc_add(struct rtw89_dev *rtwdev,
5082 const struct rtw89_fw_mrc_add_arg *arg);
5083 int rtw89_fw_h2c_mrc_start(struct rtw89_dev *rtwdev,
5084 const struct rtw89_fw_mrc_start_arg *arg);
5085 int rtw89_fw_h2c_mrc_del(struct rtw89_dev *rtwdev, u8 sch_idx, u8 slot_idx);
5086 int rtw89_fw_h2c_mrc_req_tsf(struct rtw89_dev *rtwdev,
5087 const struct rtw89_fw_mrc_req_tsf_arg *arg,
5088 struct rtw89_mac_mrc_tsf_rpt *rpt);
5089 int rtw89_fw_h2c_mrc_upd_bitmap(struct rtw89_dev *rtwdev,
5090 const struct rtw89_fw_mrc_upd_bitmap_arg *arg);
5091 int rtw89_fw_h2c_mrc_sync(struct rtw89_dev *rtwdev,
5092 const struct rtw89_fw_mrc_sync_arg *arg);
5093 int rtw89_fw_h2c_mrc_upd_duration(struct rtw89_dev *rtwdev,
5094 const struct rtw89_fw_mrc_upd_duration_arg *arg);
5095 int rtw89_fw_h2c_ap_info_refcount(struct rtw89_dev *rtwdev, bool en);
5096 int rtw89_fw_h2c_mlo_link_cfg(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
5097 bool enable);
5098
rtw89_fw_h2c_init_ba_cam(struct rtw89_dev * rtwdev)5099 static inline void rtw89_fw_h2c_init_ba_cam(struct rtw89_dev *rtwdev)
5100 {
5101 const struct rtw89_chip_info *chip = rtwdev->chip;
5102
5103 if (chip->bacam_ver == RTW89_BACAM_V0_EXT)
5104 rtw89_fw_h2c_init_dynamic_ba_cam_v0_ext(rtwdev);
5105 }
5106
rtw89_chip_h2c_default_cmac_tbl(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)5107 static inline int rtw89_chip_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev,
5108 struct rtw89_vif_link *rtwvif_link,
5109 struct rtw89_sta_link *rtwsta_link)
5110 {
5111 const struct rtw89_chip_info *chip = rtwdev->chip;
5112
5113 return chip->ops->h2c_default_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
5114 }
5115
rtw89_chip_h2c_default_dmac_tbl(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)5116 static inline int rtw89_chip_h2c_default_dmac_tbl(struct rtw89_dev *rtwdev,
5117 struct rtw89_vif_link *rtwvif_link,
5118 struct rtw89_sta_link *rtwsta_link)
5119 {
5120 const struct rtw89_chip_info *chip = rtwdev->chip;
5121
5122 if (chip->ops->h2c_default_dmac_tbl)
5123 return chip->ops->h2c_default_dmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
5124
5125 return 0;
5126 }
5127
rtw89_chip_h2c_update_beacon(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)5128 static inline int rtw89_chip_h2c_update_beacon(struct rtw89_dev *rtwdev,
5129 struct rtw89_vif_link *rtwvif_link)
5130 {
5131 const struct rtw89_chip_info *chip = rtwdev->chip;
5132
5133 return chip->ops->h2c_update_beacon(rtwdev, rtwvif_link);
5134 }
5135
rtw89_chip_h2c_assoc_cmac_tbl(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)5136 static inline int rtw89_chip_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev,
5137 struct rtw89_vif_link *rtwvif_link,
5138 struct rtw89_sta_link *rtwsta_link)
5139 {
5140 const struct rtw89_chip_info *chip = rtwdev->chip;
5141
5142 return chip->ops->h2c_assoc_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
5143 }
5144
5145 static inline
rtw89_chip_h2c_ampdu_link_cmac_tbl(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)5146 int rtw89_chip_h2c_ampdu_link_cmac_tbl(struct rtw89_dev *rtwdev,
5147 struct rtw89_vif_link *rtwvif_link,
5148 struct rtw89_sta_link *rtwsta_link)
5149 {
5150 const struct rtw89_chip_info *chip = rtwdev->chip;
5151
5152 if (chip->ops->h2c_ampdu_cmac_tbl)
5153 return chip->ops->h2c_ampdu_cmac_tbl(rtwdev, rtwvif_link,
5154 rtwsta_link);
5155
5156 return 0;
5157 }
5158
rtw89_chip_h2c_ampdu_cmac_tbl(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,struct rtw89_sta * rtwsta)5159 static inline int rtw89_chip_h2c_ampdu_cmac_tbl(struct rtw89_dev *rtwdev,
5160 struct rtw89_vif *rtwvif,
5161 struct rtw89_sta *rtwsta)
5162 {
5163 struct rtw89_vif_link *rtwvif_link;
5164 struct rtw89_sta_link *rtwsta_link;
5165 unsigned int link_id;
5166 int ret;
5167
5168 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) {
5169 rtwvif_link = rtwsta_link->rtwvif_link;
5170 ret = rtw89_chip_h2c_ampdu_link_cmac_tbl(rtwdev, rtwvif_link,
5171 rtwsta_link);
5172 if (ret)
5173 return ret;
5174 }
5175
5176 return 0;
5177 }
5178
5179 static inline
rtw89_chip_h2c_txtime_cmac_tbl(struct rtw89_dev * rtwdev,struct rtw89_sta_link * rtwsta_link)5180 int rtw89_chip_h2c_txtime_cmac_tbl(struct rtw89_dev *rtwdev,
5181 struct rtw89_sta_link *rtwsta_link)
5182 {
5183 const struct rtw89_chip_info *chip = rtwdev->chip;
5184
5185 return chip->ops->h2c_txtime_cmac_tbl(rtwdev, rtwsta_link);
5186 }
5187
5188 static inline
rtw89_chip_h2c_punctured_cmac_tbl(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,u16 punctured)5189 int rtw89_chip_h2c_punctured_cmac_tbl(struct rtw89_dev *rtwdev,
5190 struct rtw89_vif_link *rtwvif_link,
5191 u16 punctured)
5192 {
5193 const struct rtw89_chip_info *chip = rtwdev->chip;
5194
5195 if (!chip->ops->h2c_punctured_cmac_tbl)
5196 return 0;
5197
5198 return chip->ops->h2c_punctured_cmac_tbl(rtwdev, rtwvif_link, punctured);
5199 }
5200
5201 static inline
rtw89_chip_h2c_ba_cam(struct rtw89_dev * rtwdev,struct rtw89_sta * rtwsta,bool valid,struct ieee80211_ampdu_params * params)5202 int rtw89_chip_h2c_ba_cam(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
5203 bool valid, struct ieee80211_ampdu_params *params)
5204 {
5205 const struct rtw89_chip_info *chip = rtwdev->chip;
5206 struct rtw89_vif_link *rtwvif_link;
5207 struct rtw89_sta_link *rtwsta_link;
5208 unsigned int link_id;
5209 int ret;
5210
5211 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) {
5212 rtwvif_link = rtwsta_link->rtwvif_link;
5213 ret = chip->ops->h2c_ba_cam(rtwdev, rtwvif_link, rtwsta_link,
5214 valid, params);
5215 if (ret)
5216 return ret;
5217 }
5218
5219 return 0;
5220 }
5221
5222 /* Must consider compatibility; don't insert new in the mid.
5223 * Fill each field's default value in rtw89_regd_entcpy().
5224 */
5225 struct rtw89_fw_regd_entry {
5226 u8 alpha2_0;
5227 u8 alpha2_1;
5228 u8 rule_2ghz;
5229 u8 rule_5ghz;
5230 u8 rule_6ghz;
5231 __le32 fmap;
5232 } __packed;
5233
5234 /* must consider compatibility; don't insert new in the mid */
5235 struct rtw89_fw_txpwr_byrate_entry {
5236 u8 band;
5237 u8 nss;
5238 u8 rs;
5239 u8 shf;
5240 u8 len;
5241 __le32 data;
5242 u8 bw;
5243 u8 ofdma;
5244 } __packed;
5245
5246 /* must consider compatibility; don't insert new in the mid */
5247 struct rtw89_fw_txpwr_lmt_2ghz_entry {
5248 u8 bw;
5249 u8 nt;
5250 u8 rs;
5251 u8 bf;
5252 u8 regd;
5253 u8 ch_idx;
5254 s8 v;
5255 } __packed;
5256
5257 /* must consider compatibility; don't insert new in the mid */
5258 struct rtw89_fw_txpwr_lmt_5ghz_entry {
5259 u8 bw;
5260 u8 nt;
5261 u8 rs;
5262 u8 bf;
5263 u8 regd;
5264 u8 ch_idx;
5265 s8 v;
5266 } __packed;
5267
5268 /* must consider compatibility; don't insert new in the mid */
5269 struct rtw89_fw_txpwr_lmt_6ghz_entry {
5270 u8 bw;
5271 u8 nt;
5272 u8 rs;
5273 u8 bf;
5274 u8 regd;
5275 u8 reg_6ghz_power;
5276 u8 ch_idx;
5277 s8 v;
5278 } __packed;
5279
5280 /* must consider compatibility; don't insert new in the mid */
5281 struct rtw89_fw_txpwr_lmt_ru_2ghz_entry {
5282 u8 ru;
5283 u8 nt;
5284 u8 regd;
5285 u8 ch_idx;
5286 s8 v;
5287 } __packed;
5288
5289 /* must consider compatibility; don't insert new in the mid */
5290 struct rtw89_fw_txpwr_lmt_ru_5ghz_entry {
5291 u8 ru;
5292 u8 nt;
5293 u8 regd;
5294 u8 ch_idx;
5295 s8 v;
5296 } __packed;
5297
5298 /* must consider compatibility; don't insert new in the mid */
5299 struct rtw89_fw_txpwr_lmt_ru_6ghz_entry {
5300 u8 ru;
5301 u8 nt;
5302 u8 regd;
5303 u8 reg_6ghz_power;
5304 u8 ch_idx;
5305 s8 v;
5306 } __packed;
5307
5308 /* must consider compatibility; don't insert new in the mid */
5309 struct rtw89_fw_tx_shape_lmt_entry {
5310 u8 band;
5311 u8 tx_shape_rs;
5312 u8 regd;
5313 u8 v;
5314 } __packed;
5315
5316 /* must consider compatibility; don't insert new in the mid */
5317 struct rtw89_fw_tx_shape_lmt_ru_entry {
5318 u8 band;
5319 u8 regd;
5320 u8 v;
5321 } __packed;
5322
5323 const struct rtw89_rfe_parms *
5324 rtw89_load_rfe_data_from_fw(struct rtw89_dev *rtwdev,
5325 const struct rtw89_rfe_parms *init);
5326
5327 enum rtw89_wow_wakeup_ver {
5328 RTW89_WOW_REASON_V0,
5329 RTW89_WOW_REASON_V1,
5330 RTW89_WOW_REASON_NUM,
5331 };
5332
5333 #endif
5334