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Searched refs:misc0 (Results 1 – 3 of 3) sorted by relevance

/src/usr.sbin/pciconf/
H A Dcap.c380 cap_secdev_amdiommu_decode_vasize(uint32_t misc0) in cap_secdev_amdiommu_decode_vasize() argument
382 switch (misc0 & PCIM_AMDIOMMU_MISC0_VASIZE_MASK) { in cap_secdev_amdiommu_decode_vasize()
397 cap_secdev_amdiommu_decode_pasize(uint32_t misc0) in cap_secdev_amdiommu_decode_pasize() argument
399 switch (misc0 & PCIM_AMDIOMMU_MISC0_PASIZE_MASK) { in cap_secdev_amdiommu_decode_pasize()
412 cap_secdev_amdiommu_decode_gvasize(uint32_t misc0) in cap_secdev_amdiommu_decode_gvasize() argument
414 switch (misc0 & PCIM_AMDIOMMU_MISC0_GVASIZE_MASK) { in cap_secdev_amdiommu_decode_gvasize()
431 uint32_t misc0, misc1; in cap_secdev() local
474 misc0 = read_config(fd, &p->pc_sel, ptr + PCIR_AMDIOMMU_MISC0, 4); in cap_secdev()
476 misc0 & PCIM_AMDIOMMU_MISC0_MSINUM_MASK, in cap_secdev()
477 (misc0 & PCIM_AMDIOMMU_MISC0_MSINUMPPR_MASK) >> 27, in cap_secdev()
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/src/sys/dev/qlnx/qlnxe/
H A Decore_mcp.c944 SET_MFW_FIELD(load_req.misc0, LOAD_REQ_ROLE, p_in_params->drv_role); in __ecore_mcp_load_req()
945 SET_MFW_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO, in __ecore_mcp_load_req()
947 SET_MFW_FIELD(load_req.misc0, (u64)LOAD_REQ_FORCE, p_in_params->force_cmd); in __ecore_mcp_load_req()
948 SET_MFW_FIELD(load_req.misc0, (u64)LOAD_REQ_FLAGS0, in __ecore_mcp_load_req()
976 load_req.fw_ver, load_req.misc0, in __ecore_mcp_load_req()
977 GET_MFW_FIELD(load_req.misc0, LOAD_REQ_ROLE), in __ecore_mcp_load_req()
978 GET_MFW_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO), in __ecore_mcp_load_req()
979 GET_MFW_FIELD(load_req.misc0, LOAD_REQ_FORCE), in __ecore_mcp_load_req()
980 GET_MFW_FIELD(load_req.misc0, LOAD_REQ_FLAGS0)); in __ecore_mcp_load_req()
998 load_rsp.fw_ver, load_rsp.misc0, in __ecore_mcp_load_req()
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H A Dmcp_public.h1148 u32 misc0; member
1169 u32 misc0; member