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Searched refs:isVGPRClass (Results 1 – 6 of 6) sorted by relevance

/src/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.h210 static bool isVGPRClass(const TargetRegisterClass *RC) { in isVGPRClass() function
H A DSIRegisterInfo.cpp454 if (ST.hasMAIInsts() && (isVGPRClass(RC) || isAGPRClass(RC))) { in getLargestLegalSuperClass()
697 if (RC->isBaseClass() && isVGPRClass(RC)) { in getReservedRegs()
3016 return RC && isVGPRClass(RC); in isVGPR()
3230 if (isVGPRClass(&RC)) in isProperlyAlignedRC()
3250 if (isVGPRClass(RC)) in getProperlyAlignedRC()
H A DGCNSchedStrategy.cpp1379 if (!SRI->isVGPRClass(DAG.MRI.getRegClass(Reg)) || in collectRematerializableInstructions()
H A DSIWholeQuadMode.cpp1456 if (TRI->isVGPRClass(regClass)) { in lowerCopyInstrs()
H A DSIInstrInfo.cpp8476 if (RI.isVGPRClass(NewDstRC) || NewDstRC == &AMDGPU::VReg_1RegClass) in getDestEquivalentVGPRClass()
H A DSIISelLowering.cpp15439 if (SIRegisterInfo::isVGPRClass(RC)) in getRegForInlineAsmConstraint()