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Searched refs:isSubRegister (Results 1 – 16 of 16) sorted by relevance

/src/contrib/llvm-project/llvm/lib/MC/
H A DMCInstrDesc.cpp35 if (ImpDef == Reg || (MRI && MRI->isSubRegister(Reg, ImpDef))) in hasImplicitDefOfPhysReg()
/src/contrib/llvm-project/llvm/lib/CodeGen/AsmPrinter/
H A DDwarfExpression.h63 bool isSubRegister() const { return SubRegSize; } in isSubRegister() function
H A DDwarfExpression.cpp346 assert(!Reg.isSubRegister() && "full register expected"); in addMachineRegExpression()
/src/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCChecker.cpp624 unsigned BadR = RI.isSubRegister(Hexagon::USR, R) ? UsrR : R; in checkRegisters()
637 unsigned BadR = RI.isSubRegister(Hexagon::USR, R) ? UsrR : R; in checkRegisters()
/src/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCRegisterInfo.h468 bool isSubRegister(MCRegister RegA, MCRegister RegB) const { in isSubRegister() function
/src/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRFrameLowering.cpp265 if (STI.getRegisterInfo()->isSubRegister(LiveIn.PhysReg, Reg)) { in spillCalleeSavedRegisters()
/src/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineInstr.cpp1121 Found = TRI->isSubRegister(MOReg, Reg); in findRegisterDefOperandIdx()
2034 if (RegInfo->isSubRegister(IncomingReg, Reg)) in addRegisterKilled()
2098 if (RegInfo->isSubRegister(Reg, MOReg)) in addRegisterDead()
H A DLiveVariables.cpp244 if (TRI->isSubRegister(Reg, DefReg)) { in FindLastPartialDef()
H A DAggressiveAntiDepBreaker.cpp578 bool IsSub = TRI->isSubRegister(SuperReg, Reg); in FindSuitableFreeRegisters()
H A DMachineCopyPropagation.cpp500 if (!TRI->isSubRegister(PreviousSrc, Src)) in isNopCopy()
/src/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsInstrInfo.cpp958 if (TRI->isSuperRegister(Reg, DestReg) || TRI->isSubRegister(Reg, DestReg)) in describeLoadedValue()
/src/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.cpp648 assert(!isSubRegister(ScratchRSrcReg, StackPtrReg)); in getReservedRegs()
654 assert(!isSubRegister(ScratchRSrcReg, FrameReg)); in getReservedRegs()
660 assert(!isSubRegister(ScratchRSrcReg, BasePtrReg)); in getReservedRegs()
H A DSIInstrInfo.cpp4606 return TRI.isSubRegister(SuperVec.getReg(), SubReg.getReg()); in isSubRegOf()
H A DSIISelLowering.cpp15691 assert(!TRI->isSubRegister(Info->getScratchRSrcReg(), in finalizeLowering()
/src/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64LoadStoreOptimizer.cpp2126 if (DestReg == BaseReg || TRI->isSubRegister(BaseReg, DestReg)) in findMatchingUpdateInsnForward()
2197 if (DestReg == BaseReg || TRI->isSubRegister(BaseReg, DestReg)) in findMatchingUpdateInsnBackward()
H A DAArch64InstrInfo.cpp9382 TRI->isSubRegister(DestReg, DescribedReg)) { in describeORRLoadedValue()