| /src/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | LiveRegUnits.h | 52 if (O->isRegMask()) in accumulateUsedDefed()
168 return MOP.isRegMask() || in phys_regs_and_masks()
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| H A D | MachineOperand.h | 353 bool isRegMask() const { return OpKind == MO_RegisterMask; } in isRegMask() function
475 if ((isReg() && isImplicit()) || isRegMask()) in isValidExcessOperand()
660 assert(isRegMask() && "Wrong MachineOperand accessor"); in getRegMask()
737 assert(isRegMask() && "Wrong MachineOperand mutator"); in setRegMask()
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| /src/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | LiveRegUnits.cpp | 53 if (MOP.isRegMask()) { in stepBackward()
80 if (MOP.isRegMask()) { in accumulate()
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| H A D | LivePhysRegs.cpp | 47 if (MOP.isRegMask()) { in removeDefs()
99 } else if (O->isRegMask()) { in stepForward()
110 if (Reg.second->isRegMask() && in stepForward()
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| H A D | RegUsageInfoPropagate.cpp | 68 if (MO.isRegMask()) in setRegMask()
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| H A D | CriticalAntiDepBreaker.cpp | 262 if (MO.isRegMask()) { in ScanInstruction()
366 if (CheckOper.isRegMask() && CheckOper.clobbersPhysReg(NewReg)) in isNewRegClobberedByRefs()
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| H A D | MachineCopyPropagation.cpp | 297 if (MO.isRegMask()) in findAvailBackwardCopy()
329 if (MO.isRegMask()) in findAvailCopy()
358 if (MO.isRegMask()) in findLastSeenDefInCopy()
877 if (MO.isRegMask()) in ForwardCopyPropagateBlock()
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| H A D | MachineCSE.cpp | 246 if (MO.isRegMask() && MO.clobbersPhysReg(Reg)) in isPhysDefTriviallyDead()
389 if (MO.isRegMask()) in PhysRegDefsReach()
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| H A D | MachineInstrBundle.cpp | 341 if (MO.isRegMask() && MO.clobbersPhysReg(Reg)) { in AnalyzePhysRegInBundle()
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| H A D | RDFGraph.cpp | 598 if (Op.isRegMask()) in isClobbering()
994 assert(Op.isReg() || Op.isRegMask()); in makeRegRef()
1317 if (!Op.isRegMask()) in buildStmt()
1791 if (!Op.isReg() && !Op.isRegMask()) in hasUntrackedRef()
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| H A D | RDFRegisters.cpp | 74 if (Op.isRegMask()) in PhysicalRegisterInfo()
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| H A D | ImplicitNullChecks.cpp | 240 auto IsRegMask = [](const MachineOperand &MO) { return MO.isRegMask(); }; in canHandle()
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| H A D | VirtRegMap.cpp | 547 if (MO.isRegMask()) in rewrite()
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| H A D | ShrinkWrap.cpp | 356 } else if (MO.isRegMask()) { in INITIALIZE_PASS_DEPENDENCY()
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| /src/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86VZeroUpper.cpp | 160 if (MI.isCall() && MO.isRegMask() && !clobbersAllYmmAndZmmRegs(MO)) in hasYmmOrZmmReg()
176 if (MO.isRegMask()) in callHasRegMask()
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| H A D | X86PreTileConfig.cpp | 110 MI.operands(), [](MachineOperand &MO) { return MO.isRegMask(); }); in isDestructiveCall()
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| /src/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCCTRLoopsVerify.cpp | 86 } else if (MO.isRegMask()) { in clobbersCTR()
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| /src/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonVLIWPacketizer.cpp | 796 if (MO.isRegMask() && MO.clobbersPhysReg(DepReg)) in canPromoteToNewValueStore()
839 if (CheckDef && MO.isRegMask() && MO.clobbersPhysReg(DepReg)) in isImplicitDependency()
1284 if (!OpJ.isRegMask()) in hasRegMaskDependence()
1291 } else if (OpI.isRegMask()) { in hasRegMaskDependence()
1614 } else if (!Op.isRegMask()) { in isLegalToPacketizeTogether()
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| H A D | RDFDeadCode.cpp | 70 if (Op.isRegMask()) { in isLiveInstr()
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| H A D | HexagonTfrCleanup.cpp | 172 if (Mo->isRegMask()) { in updateImmMap()
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| H A D | HexagonBlockRanges.cpp | 350 if (!Op.isRegMask()) in computeInitialLiveRanges()
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| /src/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64A57FPLoadBalancing.cpp | 560 } else if (U.isRegMask()) { in colorChain()
696 } else if (MO.isRegMask()) { in maybeKillChain()
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| H A D | AArch64CollectLOH.cpp | 498 if (MO.isRegMask()) { in handleNormalInst()
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| /src/contrib/llvm-project/llvm/lib/CodeGen/AsmPrinter/ |
| H A D | DbgEntityHistoryCalculator.cpp | 519 } else if (MO.isRegMask()) { in calculateDbgEntityHistory()
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| /src/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.cpp | 362 if (MO.isRegMask() && MO.clobbersPhysReg(Lanai::SR)) { in optimizeCompareInstr()
|