| /src/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | CallingConvLower.cpp | 77 if (ValAssign.isRegLoc() && TRI.regsOverlap(ValAssign.getLocReg(), Reg)) in IsShadowAllocatedReg()
223 HaveRegParm = Locs.back().isRegLoc(); in getRemainingRegParmsForType()
229 if (Locs[I].isRegLoc()) in getRemainingRegParmsForType()
283 if (Loc1.isRegLoc() && Loc2.isRegLoc()) in resultsCompatible()
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| /src/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMCallLowering.cpp | 121 assert(VA.isRegLoc() && "Value shouldn't be assigned to reg"); in assignValueToReg()
160 assert(VA.isRegLoc() && "Value should be in reg"); in assignCustomValue()
161 assert(NextVA.isRegLoc() && "Value should be in reg"); in assignCustomValue()
294 assert(VA.isRegLoc() && "Value shouldn't be assigned to reg"); in assignValueToReg()
336 assert(VA.isRegLoc() && "Value should be in reg"); in assignCustomValue()
337 assert(NextVA.isRegLoc() && "Value should be in reg"); in assignCustomValue()
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| H A D | ARMFastISel.cpp | 1899 if (VA.isRegLoc() && !VA.needsCustom()) { in ProcessCallArgs()
1905 !VA.isRegLoc() || !ArgLocs[++i].isRegLoc()) in ProcessCallArgs()
1979 if (VA.isRegLoc() && !VA.needsCustom()) { in ProcessCallArgs()
1991 assert(VA.isRegLoc() && NextVA.isRegLoc() && in ProcessCallArgs()
2121 if (!VA.isRegLoc()) in SelectRet()
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| /src/contrib/llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCISelLowering.cpp | 324 if (VA.isRegLoc()) { in LowerCall()
416 if (VA.isRegLoc()) { in lowerCallResult()
521 if (VA.isRegLoc()) { in LowerCallArguments()
672 if (VA.isRegLoc()) in LowerReturn()
700 if (!VA.isRegLoc()) in LowerReturn()
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| /src/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLoweringCall.cpp | 719 assert(VA.isRegLoc() && NextVA.isRegLoc() && in Passv64i1ArgInRegs()
761 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
1016 assert(VA.isRegLoc() && NextVA.isRegLoc() && in getv64i1Argument()
1717 if (VA.isRegLoc()) { in LowerFormalArguments()
1806 !(Ins[I].Flags.isByVal() && VA.isRegLoc())) { in LowerFormalArguments()
2224 } else if (VA.isRegLoc()) { in LowerCall()
2335 if (VA.isRegLoc()) { in LowerCall()
2805 if (!VA.isRegLoc()) in IsEligibleForTailCallOptimization()
2859 if (!VA.isRegLoc()) { in IsEligibleForTailCallOptimization()
2882 if (!VA.isRegLoc()) in IsEligibleForTailCallOptimization()
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| H A D | X86FastISel.cpp | 1236 if (!VA.isRegLoc()) in X86SelectRet()
3436 if (VA.isRegLoc()) { in fastLowerCall()
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| /src/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelLowering.cpp | 305 assert(VA.isRegLoc() && "Expected register VA assignment"); in unpack64()
359 else if (VA.isRegLoc()) in LowerFormalArguments()
456 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
462 assert(VA.isRegLoc() && "Expected return via registers"); in LowerReturn()
578 if (IsF64OnCSKY && VA.isRegLoc()) { in LowerCall()
611 if (VA.isRegLoc()) { in LowerCall()
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| /src/contrib/llvm-project/llvm/lib/Target/Xtensa/ |
| H A D | XtensaISelLowering.cpp | 227 if (VA.isRegLoc()) { in LowerFormalArguments()
340 if (VA.isRegLoc()) in LowerCall()
508 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
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| /src/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CallLowering.cpp | 1147 if (!ArgLoc.isRegLoc()) in parametersInCSRMatch()
1226 if (Loc1.isRegLoc() != Loc2.isRegLoc()) in resultsCompatible()
1229 if (Loc1.isRegLoc()) { in resultsCompatible()
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| /src/contrib/llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFISelLowering.cpp | 349 if (VA.isRegLoc()) { in LowerFormalArguments()
476 if (VA.isRegLoc()) in LowerCall()
563 if (!VA.isRegLoc()) in LowerReturn()
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| /src/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 283 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn_32()
366 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn_64()
464 if (VA.isRegLoc()) { in LowerFormalArguments_32()
642 if (VA.isRegLoc()) { in LowerFormalArguments_64()
979 if (VA.isRegLoc()) { in LowerCall_32()
983 if (NextVA.isRegLoc()) { in LowerCall_32()
1013 if (VA.isRegLoc()) { in LowerCall_32()
1114 assert(RVLocs[i].isRegLoc() && "Can only return in registers!"); in LowerCall_32()
1185 if (!VA.isRegLoc() || (ValTy != MVT::f64 && ValTy != MVT::f128)) in fixupVariableFloatArgs()
1299 if (VA.isRegLoc()) { in LowerCall_64()
[all …]
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| /src/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
| H A D | RISCVCallLowering.cpp | 151 if (VAHi.isRegLoc()) in assignCustomValue()
275 if (VAHi.isRegLoc()) in assignCustomValue()
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| /src/contrib/llvm-project/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 977 if (VA.isRegLoc()) { in LowerCallResult()
1070 if (VA.isRegLoc()) { in LowerCCCCallTo()
1206 if (VA.isRegLoc()) { in LowerCCCArguments()
1373 if (VA.isRegLoc()) in LowerReturn()
1401 if (!VA.isRegLoc()) in LowerReturn()
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| /src/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | CallingConvLower.h | 122 bool isRegLoc() const { return std::holds_alternative<Register>(Data); } in isRegLoc() function
|
| /src/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 680 if (VA.isRegLoc()) { in LowerCall()
725 if (VA.isRegLoc()) in LowerCall()
946 if (VA.isRegLoc()) { in LowerFormalArguments()
1094 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
1269 if (!ArgLocs[i].isRegLoc()) in IsEligibleForTailCallOptimization()
1312 if (!VA.isRegLoc()) { in IsEligibleForTailCallOptimization()
1336 if (!VA.isRegLoc()) in IsEligibleForTailCallOptimization()
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| /src/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.cpp | 455 if (VA.isRegLoc()) { in LowerCCCArguments()
561 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
691 if (VA.isRegLoc()) { in LowerCCCCallTo()
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| /src/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 641 if (VA.isRegLoc()) { in LowerCCCArguments()
763 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
850 if (VA.isRegLoc()) { in LowerCCCCallTo()
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| /src/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 1397 !VA.isRegLoc() || VA.needsCustom()) in processCallArgs()
1504 assert(VA.isRegLoc() && "Can only return in registers!"); in finishCall()
1744 assert(VA.isRegLoc() && "Can only return in registers!"); in SelectRet()
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| H A D | PPCISelLowering.cpp | 4290 if (VA.isRegLoc()) { in LowerFormalArguments_32SVR4()
5361 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerCallResult()
6141 if (VA.isRegLoc()) { in LowerCall_32SVR4()
7268 assert(I != End && ArgLocs[I].isRegLoc() && ArgLocs[I].needsCustom() && in LowerFormalArguments_AIX()
7290 if (I != End && ArgLocs[I].isRegLoc() && ArgLocs[I].needsCustom()) { in LowerFormalArguments_AIX()
7300 if (VA.isRegLoc()) { in LowerFormalArguments_AIX()
7351 assert(VA.isRegLoc() && "MemLocs should already be handled."); in LowerFormalArguments_AIX()
7390 for (; Offset != StackSize && ArgLocs[I].isRegLoc(); in LowerFormalArguments_AIX()
7412 if (VA.isRegLoc() && !VA.needsCustom()) { in LowerFormalArguments_AIX()
7572 while (LoadOffset + PtrByteSize <= ByValSize && ArgLocs[I].isRegLoc()) { in LowerCall_AIX()
[all …]
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| /src/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 1223 if (VA.isRegLoc() && !VA.needsCustom()) { in processCallArgs()
1714 if (!VA.isRegLoc()) in selectRet()
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| H A D | MipsISelLowering.cpp | 3321 if (VA.isRegLoc()) { in LowerCall()
3377 if (VA.isRegLoc()) { in LowerCall()
3537 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerCallResult()
3686 bool IsRegLoc = VA.isRegLoc(); in LowerFormalArguments()
3857 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
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| /src/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 388 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
464 if (VA.isRegLoc()) { in LowerFormalArguments()
721 if (VA.isRegLoc()) { in LowerCall()
|
| /src/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64CallLowering.cpp | 907 if (ArgLoc.isRegLoc()) in areCalleeOutgoingArgsTailCallable()
|
| /src/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 520 if (VA.isRegLoc()) in LowerCall()
850 if (VA.isRegLoc() && ByVal && Flags.getByValSize() <= 8) in LowerFormalArguments()
853 bool InReg = VA.isRegLoc() && in LowerFormalArguments()
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| /src/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 1392 if (VA.isRegLoc()) { in LowerFormalArguments()
1718 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
|