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Searched refs:isRegDefKind (Results 1 – 10 of 10) sorted by relevance

/src/contrib/llvm-project/llvm/include/llvm/IR/
H A DInlineAsm.h328 bool isRegDefKind() const { return getKind() == Kind::RegDef; } in isRegDefKind() function
432 assert((isRegDefKind() || isRegDefEarlyClobberKind() || isRegUseKind()) && in setRegMayBeFolded()
437 assert((isRegDefKind() || isRegDefEarlyClobberKind() || isRegUseKind()) && in getRegMayBeFolded()
/src/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp221 if (!Flag.isRegUseKind() && !Flag.isRegDefKind() && in tryInlineAsm()
239 if (Flag.isRegDefKind() || Flag.isRegDefEarlyClobberKind()) { in tryInlineAsm()
/src/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelDAGToDAG.cpp187 if (!Flag.isRegUseKind() && !Flag.isRegDefKind() && in selectInlineAsm()
205 if (Flag.isRegDefKind() || Flag.isRegDefEarlyClobberKind()) { in selectInlineAsm()
/src/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DInlineAsmLowering.cpp396 if (!MatchedOperandFlag.isRegDefKind() && !MatchedOperandFlag.isRegDefEarlyClobberKind()) { in lowerInlineAsm()
/src/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGFast.cpp500 if (F.isRegDefKind() || F.isRegDefEarlyClobberKind() || in DelayForLiveRegsBottomUp()
H A DScheduleDAGRRList.cpp1377 if (F.isRegDefKind() || F.isRegDefEarlyClobberKind() || in DelayForLiveRegsBottomUp()
H A DSelectionDAGBuilder.cpp9717 (F.isRegDefKind() || F.isRegDefEarlyClobberKind() || F.isMemKind()) && in findMatchingInlineAsmOperand()
10021 if (Flag.isRegDefKind() || Flag.isRegDefEarlyClobberKind()) { in visitInlineAsm()
/src/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineInstr.cpp971 if ((F.isRegUseKind() || F.isRegDefKind() || F.isRegDefEarlyClobberKind()) && in getRegClassConstraint()
1853 if ((F.isRegDefKind() || F.isRegDefEarlyClobberKind() || in print()
2619 if (F.isRegUseKind() || F.isRegDefKind() || F.isRegDefEarlyClobberKind()) in mayFoldInlineAsmRegOp()
H A DTargetInstrInfo.cpp1783 if ((F.isRegDefKind() || F.isRegDefEarlyClobberKind() || F.isRegUseKind()) && in createMIROperandComment()
/src/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp5769 if (!Flag.isRegUseKind() && !Flag.isRegDefKind() && in tryInlineAsm()
5787 if (Flag.isRegDefKind() || Flag.isRegDefEarlyClobberKind()) { in tryInlineAsm()