| /src/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCCodeEmitter.cpp | 590 bool isAdd = true; in EncodeAddrModeOpValues() local
595 isAdd = false; in EncodeAddrModeOpValues()
601 isAdd = false; in EncodeAddrModeOpValues()
605 return isAdd; in EncodeAddrModeOpValues()
971 bool isAdd = true; in getAddrModeImm12OpValue() local
977 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups, STI); in getAddrModeImm12OpValue()
982 isAdd = false; // 'U' bit is set as part of the fixup. in getAddrModeImm12OpValue()
988 isAdd = false; // 'U' bit is set as part of the fixup. in getAddrModeImm12OpValue()
1002 isAdd = false; in getAddrModeImm12OpValue()
1005 isAdd = false; in getAddrModeImm12OpValue()
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| H A D | ARMAsmBackend.cpp | 527 bool isAdd = true; in adjustFixupValue() local
530 isAdd = false; in adjustFixupValue()
536 Value |= isAdd << 23; in adjustFixupValue()
758 bool isAdd = true; in adjustFixupValue() local
761 isAdd = false; in adjustFixupValue()
769 return Value | (isAdd << 23); in adjustFixupValue()
778 bool isAdd = true; in adjustFixupValue() local
781 isAdd = false; in adjustFixupValue()
789 Value |= isAdd << 23; in adjustFixupValue()
805 bool isAdd = true; in adjustFixupValue() local
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| /src/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYInstrInfo16Instr.td | 59 let isCommutable = 1, isAdd = 1 in
64 let isCommutable = 1, isAdd = 1 in
69 let isAdd = 1 in
94 let isAdd = 1, Pattern = [(set mGPR:$rz, (add mGPR:$rZ, oimm8:$imm8))] in
103 let isAdd = 1 in
107 let isAdd = 1 in
117 let isAdd = 1 in
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| H A D | CSKYInstrInfo.td | 524 let isAdd = 1 in
548 let isAdd = 1 in
606 let isCommutable = 1, isAdd = 1 in
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| /src/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | InstrDocsEmitter.cpp | 120 FLAG(isAdd) in EmitInstrDocs()
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| H A D | InstrInfoEmitter.cpp | 1230 if (Inst.isAdd) in emitRecord()
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| /src/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCInstrDesc.h | 279 bool isAdd() const { return Flags & (1ULL << MCID::Add); } in isAdd() function
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| /src/contrib/llvm-project/llvm/utils/TableGen/Common/ |
| H A D | CodeGenInstruction.h | 253 bool isAdd : 1; variable
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| H A D | CodeGenInstruction.cpp | 448 isAdd = R->getValueAsBit("isAdd"); in CodeGenInstruction()
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| /src/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | GenericMachineInstrs.h | 429 bool isAdd() const { in isAdd() function
440 bool isSub() const { return !isAdd(); } in isSub()
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| /src/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 900 bool isAdd; member
3086 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0); in addAM3OffsetOperands()
3332 bool isAdd = Imm >= 0; in addPostIdxImm8Operands() local
3334 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8; in addPostIdxImm8Operands()
3343 bool isAdd = Imm >= 0; in addPostIdxImm8s4Operands() local
3346 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8; in addPostIdxImm8s4Operands()
3353 Inst.addOperand(MCOperand::createImm(PostIdxReg.isAdd)); in addPostIdxRegOperands()
3361 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub; in addPostIdxRegShiftedOperands()
3906 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy, in CreatePostIdxReg() argument
3910 Op->PostIdxReg.isAdd = isAdd; in CreatePostIdxReg()
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| /src/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstrInfo.td | 2924 // {12} isAdd
2942 // {12} isAdd
3034 // {12} isAdd
3053 // {12} isAdd
3070 // {12} isAdd
3089 // {12} isAdd
3206 // {12} isAdd
3224 // {12} isAdd
3368 // {12} isAdd
3387 // {12} isAdd
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| H A D | ARMInstrFormats.td | 814 // {12} isAdd
832 // {12} isAdd
853 // {12} isAdd
906 // {8} isAdd
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| H A D | ARMInstrThumb.td | 966 let isAdd = 1 in {
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| H A D | ARMInstrThumb2.td | 2424 let isAdd = 1 in
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| /src/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonHardwareLoops.cpp | 444 if (DI->getDesc().isAdd()) { in findInductionRegister()
1625 if (DI->getDesc().isAdd()) { in fixupInductionVariable()
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| H A D | HexagonDepInstrInfo.td | 220 let isAdd = 1;
236 let isAdd = 1;
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| /src/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUIGroupLP.cpp | 1379 auto isAdd = [](unsigned Opc) { return Opc == AMDGPU::V_ADD_F32_e32; }; in analyzeDAG() local
1404 if (isAdd(Opc)) in analyzeDAG()
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| /src/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | Target.td | 639 bit isAdd = false; // Is this instruction an add instruction?
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| /src/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 47625 auto combineMulShlAddOrSub = [&](int Mult, int Shift, bool isAdd) { in combineMulSpecial() argument
47630 Result = DAG.getNode(isAdd ? ISD::ADD : ISD::SUB, DL, VT, Result, in combineMulSpecial()
47635 auto combineMulMulAddOrSub = [&](int Mul1, int Mul2, bool isAdd) { in combineMulSpecial() argument
47640 Result = DAG.getNode(isAdd ? ISD::ADD : ISD::SUB, DL, VT, Result, in combineMulSpecial()
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