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Searched refs:isAGPRClass (Results 1 – 10 of 10) sorted by relevance

/src/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNPreRAOptimizations.cpp91 bool IsAGPRDst = TRI->isAGPRClass(MRI->getRegClass(Reg)); in processReg()
113 bool IsAGPRSrc = TRI->isAGPRClass(MRI->getRegClass(SrcReg)); in processReg()
233 (ST.hasGFX90AInsts() || !TRI->isAGPRClass(RC))) in runOnMachineFunction()
H A DSIRegisterInfo.cpp454 if (ST.hasMAIInsts() && (isVGPRClass(RC) || isAGPRClass(RC))) { in getLargestLegalSuperClass()
711 if (RC->isBaseClass() && isAGPRClass(RC)) { in getReservedRegs()
951 if (isAGPRClass(RC) && !ST.hasGFX90AInsts()) in getCrossCopyRegClass()
1351 const bool IsAGPR = !ST.hasGFX90AInsts() && isAGPRClass(RC); in buildSpillLoadStore()
3024 return RC && isAGPRClass(RC); in isAGPR()
3232 if (isAGPRClass(&RC)) in isProperlyAlignedRC()
3252 if (isAGPRClass(RC)) in getProperlyAlignedRC()
H A DSIRegisterInfo.h215 static bool isAGPRClass(const TargetRegisterClass *RC) { in isAGPRClass() function
H A DSIFixSGPRCopies.cpp310 bool IsAGPR = TRI->isAGPRClass(DstRC); in foldVGPRCopyIntoRegSequence()
819 if (HasUses && AllAGPRUses && !TRI->isAGPRClass(RC0)) { in processPHINode()
H A DGCNRegPressure.cpp45 : STI->isAGPRClass(RC) in getRegKind()
H A DSIMachineFunctionInfo.cpp778 if (RC && SIRegisterInfo::isAGPRClass(RC)) { in usesAGPRs()
H A DSIInstrInfo.cpp1064 if (RI.isAGPRClass(RC)) { in copyPhysReg()
1065 if (ST.hasGFX90AInsts() && RI.isAGPRClass(SrcRC)) in copyPhysReg()
1072 } else if (RI.hasVGPRs(RC) && RI.isAGPRClass(SrcRC)) { in copyPhysReg()
1380 if (RI.isAGPRClass(DstRC)) in getMovOpcode()
1713 return TRI.isAGPRClass(RC) ? getAGPRSpillSaveOpcode(Size) in getVectorRegSpillSaveOpcode()
1938 return TRI.isAGPRClass(RC) ? getAGPRSpillRestoreOpcode(Size) in getVectorRegSpillRestoreOpcode()
6610 VRC = RI.isAGPRClass(getOpRegClass(MI, 0)) in legalizeOperands()
6614 VRC = RI.isAGPRClass(getOpRegClass(MI, 0)) in legalizeOperands()
8459 if (RI.isAGPRClass(SrcRC)) { in getDestEquivalentVGPRClass()
8460 if (RI.isAGPRClass(NewDstRC)) in getDestEquivalentVGPRClass()
H A DSILoadStoreOptimizer.cpp1876 return TRI->isAGPRClass(getDataRegClass(*CI.I)) in getTargetRegisterClass()
H A DAMDGPURegisterBankInfo.cpp304 return TRI->isAGPRClass(&RC) ? AMDGPU::AGPRRegBank : AMDGPU::VGPRRegBank; in getRegBankFromRegClass()
H A DSIISelLowering.cpp15443 else if (SIRegisterInfo::isAGPRClass(RC)) in getRegForInlineAsmConstraint()