| /src/sys/contrib/device-tree/src/arm64/st/ |
| H A D | stm32mp231.dtsi | 33 interrupt-parent = <&intc>;
58 interrupt-parent = <&intc>;
135 interrupt-parent = <&intc>;
146 interrupt-parent = <&intc>;
712 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
868 <&intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */
869 <&intc GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
870 <&intc GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
871 <&intc GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
872 <&intc GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
[all …]
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| H A D | stm32mp251.dtsi | 34 interrupt-parent = <&intc>;
61 interrupt-parent = <&intc>;
117 intc: interrupt-controller@4ac00000 { label
148 interrupt-parent = <&intc>;
160 interrupt-parent = <&intc>;
1613 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
1769 <&intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */
1770 <&intc GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
1771 <&intc GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
1772 <&intc GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
[all …]
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| /src/sys/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | mrvl,intc.txt | 5 "mrvl,mmp-intc" on Marvel MMP,
6 "mrvl,mmp2-intc" along with "mrvl,mmp2-mux-intc" on MMP2 or
7 "marvell,mmp3-intc" with "mrvl,mmp2-mux-intc" on MMP3
9 If the interrupt controller is intc, address and length means the range
10 of the whole interrupt controller. The "marvell,mmp3-intc" controller
12 controller is mux-intc, address and length means one register. Since
13 address of mux-intc is in the range of intc. mux-intc is secondary
16 only required in mux-intc interrupt controller.
18 only required in mux-intc interrupt controller.
22 - mrvl,intc-nr-irqs : Specifies the number of interrupts in the interrupt
[all …]
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| H A D | csky,apb-intc.txt | 8 - csky,apb-intc is used in a lot of csky fpgas and socs, it support 64 irq nums.
9 - csky,dual-apb-intc consists of 2 apb-intc and 128 irq nums supported.
10 - csky,gx6605s-intc is gx6605s soc internal irq interrupt controller, 64 irq nums.
13 intc node bindings definition
23 Definition: must be "csky,apb-intc"
24 "csky,dual-apb-intc"
25 "csky,gx6605s-intc"
43 intc: interrupt-controller@500000 {
44 compatible = "csky,apb-intc";
50 intc: interrupt-controller@500000 {
[all …]
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| H A D | ti,omap-intc-irq.txt | 1 Omap2/3 intc controller
3 On TI omap2 and 3 the intc interrupt controller can provide
8 "ti,omap2-intc"
9 "ti,omap3-intc"
10 "ti,dm814-intc"
11 "ti,dm816-intc"
12 "ti,am33xx-intc"
16 source, should be 1 for intc
23 intc: interrupt-controller@48200000 {
24 compatible = "ti,omap3-intc";
|
| H A D | amlogic,meson-gpio-intc.txt | 12 - compatible : must have "amlogic,meson8-gpio-intc" and either
13 "amlogic,meson8-gpio-intc" for meson8 SoCs (S802) or
14 "amlogic,meson8b-gpio-intc" for meson8b SoCs (S805) or
15 "amlogic,meson-gxbb-gpio-intc" for GXBB SoCs (S905) or
16 "amlogic,meson-gxl-gpio-intc" for GXL SoCs (S905X, S912)
17 "amlogic,meson-axg-gpio-intc" for AXG SoCs (A113D, A113X)
18 "amlogic,meson-g12a-gpio-intc" for G12A SoCs (S905D2, S905X2, S905Y2)
19 "amlogic,meson-sm1-gpio-intc" for SM1 SoCs (S905D3, S905X3, S905Y3)
20 "amlogic,meson-a1-gpio-intc" for A1 SoCs (A113L)
21 "amlogic,meson-s4-gpio-intc" for S4 SoCs (S802X2, S905Y4, S805X2G, S905W2)
[all …]
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| H A D | qca,ath79-misc-intc.txt | 7 - compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-misc-intc" or
8 "qca,<soctype>-cpu-intc", "qca,ar7240-misc-intc"
24 compatible = "qca,ar9132-misc-intc", "qca,ar7100-misc-intc";
37 compatible = "qca,ar9331-misc-intc", qca,ar7240-misc-intc";
|
| H A D | ti,omap2-intc.txt | 9 "ti,omap2-intc"
15 - ti,intc-size: Number of interrupts handled by the interrupt controller.
16 - reg: physical base address and size of the intc registers map.
20 intc: interrupt-controller@1 {
21 compatible = "ti,omap2-intc";
24 ti,intc-size = <96>;
|
| H A D | ti,cp-intc.txt | 10 "ti,cp-intc"
16 - ti,intc-size: Number of interrupts handled by the interrupt controller.
17 - reg: physical base address and size of the intc registers map.
21 intc: interrupt-controller@1 {
22 compatible = "ti,cp-intc";
25 ti,intc-size = <101>;
|
| H A D | sifive,plic-1.0.0.txt | 39 to should be a riscv,cpu-intc node, which has a riscv node as parent.
51 &cpu0-intc 11
52 &cpu1-intc 11 &cpu1-intc 9
53 &cpu2-intc 11 &cpu2-intc 9
54 &cpu3-intc 11 &cpu3-intc 9
55 &cpu4-intc 11 &cpu4-intc 9>;
|
| /src/sys/contrib/device-tree/src/arm/arm/ |
| H A D | arm-realview-pba8.dts | 45 interrupt-parent = <&intc>;
51 intc: interrupt-controller@1e000000 { label
62 interrupt-parent = <&intc>;
67 interrupt-parent = <&intc>;
80 interrupt-parent = <&intc>;
85 interrupt-parent = <&intc>;
90 interrupt-parent = <&intc>;
95 interrupt-parent = <&intc>;
100 interrupt-parent = <&intc>;
105 interrupt-parent = <&intc>;
[all …]
|
| H A D | arm-realview-pbx-a9.dts | 89 interrupt-parent = <&intc>;
96 interrupt-parent = <&intc>;
102 interrupt-parent = <&intc>;
109 intc: interrupt-controller@1f000000 { label
120 interrupt-parent = <&intc>;
125 interrupt-parent = <&intc>;
130 interrupt-parent = <&intc>;
135 interrupt-parent = <&intc>;
140 interrupt-parent = <&intc>;
145 interrupt-parent = <&intc>;
[all …]
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| H A D | arm-realview-eb.dts | 51 intc: interrupt-controller@10040000 { label
68 interrupt-parent = <&intc>;
73 interrupt-parent = <&intc>;
78 interrupt-parent = <&intc>;
83 interrupt-parent = <&intc>;
89 interrupt-parent = <&intc>;
94 interrupt-parent = <&intc>;
99 interrupt-parent = <&intc>;
104 interrupt-parent = <&intc>;
109 interrupt-parent = <&intc>;
[all …]
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| H A D | arm-realview-eb-mp.dtsi | 41 intc: interrupt-controller@1f000100 { label
58 interrupt-parent = <&intc>;
65 interrupt-parent = <&intc>;
94 interrupt-parent = <&intc>;
101 interrupt-parent = <&intc>;
108 interrupt-parent = <&intc>;
123 interrupt-parent = <&intc>;
128 interrupt-parent = <&intc>;
133 interrupt-parent = <&intc>;
138 interrupt-parent = <&intc>;
[all …]
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| /src/sys/contrib/device-tree/src/mips/ingenic/ |
| H A D | jz4770.dtsi | 31 intc: interrupt-controller@10001000 { label
32 compatible = "ingenic,jz4770-intc";
92 interrupt-parent = <&intc>;
133 interrupt-parent = <&intc>;
155 interrupt-parent = <&intc>;
170 interrupt-parent = <&intc>;
185 interrupt-parent = <&intc>;
200 interrupt-parent = <&intc>;
215 interrupt-parent = <&intc>;
230 interrupt-parent = <&intc>;
[all …]
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| H A D | jz4780.dtsi | 41 intc: interrupt-controller@10001000 { label
42 compatible = "ingenic,jz4780-intc";
113 interrupt-parent = <&intc>;
153 interrupt-parent = <&intc>;
180 interrupt-parent = <&intc>;
195 interrupt-parent = <&intc>;
210 interrupt-parent = <&intc>;
225 interrupt-parent = <&intc>;
240 interrupt-parent = <&intc>;
255 interrupt-parent = <&intc>;
[all …]
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| H A D | x1000.dtsi | 32 intc: interrupt-controller@10001000 { label
33 compatible = "ingenic,x1000-intc", "ingenic,jz4780-intc";
121 interrupt-parent = <&intc>;
149 interrupt-parent = <&intc>;
173 interrupt-parent = <&intc>;
188 interrupt-parent = <&intc>;
203 interrupt-parent = <&intc>;
218 interrupt-parent = <&intc>;
227 interrupt-parent = <&intc>;
240 interrupt-parent = <&intc>;
[all …]
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| H A D | x1830.dtsi | 32 intc: interrupt-controller@10001000 { label
33 compatible = "ingenic,x1830-intc", "ingenic,jz4780-intc";
114 interrupt-parent = <&intc>;
144 interrupt-parent = <&intc>;
168 interrupt-parent = <&intc>;
183 interrupt-parent = <&intc>;
198 interrupt-parent = <&intc>;
213 interrupt-parent = <&intc>;
222 interrupt-parent = <&intc>;
235 interrupt-parent = <&intc>;
[all …]
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| H A D | jz4740.dtsi | 31 intc: interrupt-controller@10001000 { label
32 compatible = "ingenic,jz4740-intc";
81 interrupt-parent = <&intc>;
111 interrupt-parent = <&intc>;
136 interrupt-parent = <&intc>;
151 interrupt-parent = <&intc>;
166 interrupt-parent = <&intc>;
181 interrupt-parent = <&intc>;
192 interrupt-parent = <&intc>;
219 interrupt-parent = <&intc>;
[all …]
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| H A D | jz4725b.dtsi | 31 intc: interrupt-controller@10001000 { label
32 compatible = "ingenic,jz4725b-intc", "ingenic,jz4740-intc";
81 interrupt-parent = <&intc>;
120 interrupt-parent = <&intc>;
145 interrupt-parent = <&intc>;
160 interrupt-parent = <&intc>;
175 interrupt-parent = <&intc>;
190 interrupt-parent = <&intc>;
204 interrupt-parent = <&intc>;
228 interrupt-parent = <&intc>;
[all …]
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| /src/sys/dts/arm/ |
| H A D | versatilepb.dts | 17 intc: interrupt-controller { label
37 interrupt-parent = <&intc>;
46 interrupt-parent = <&intc>;
55 interrupt-parent = <&intc>;
64 interrupt-parent = <&intc>;
80 interrupt-parent = <&intc>;
88 interrupt-parent = <&intc>;
99 interrupt-parent = <&intc>;
|
| /src/sys/contrib/device-tree/src/arm/xilinx/ |
| H A D | zynq-7000.dtsi | 55 interrupt-parent = <&intc>;
107 interrupt-parent = <&intc>;
114 interrupt-parent = <&intc>;
125 interrupt-parent = <&intc>;
137 interrupt-parent = <&intc>;
149 interrupt-parent = <&intc>;
158 interrupt-parent = <&intc>;
170 interrupt-parent = <&intc>;
178 intc: interrupt-controller@f8f01000 { label
234 interrupt-parent = <&intc>;
[all …]
|
| /src/sys/contrib/device-tree/src/arm/marvell/ |
| H A D | mmp3.dtsi | 49 compatible = "marvell,mmp3-intc";
54 mrvl,intc-nr-irqs = <64>;
58 compatible = "mrvl,mmp2-mux-intc";
64 mrvl,intc-nr-irqs = <4>;
68 compatible = "mrvl,mmp2-mux-intc";
74 mrvl,intc-nr-irqs = <2>;
78 compatible = "mrvl,mmp2-mux-intc";
84 mrvl,intc-nr-irqs = <3>;
88 compatible = "mrvl,mmp2-mux-intc";
94 mrvl,intc-nr-irqs = <3>;
[all …]
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| /src/sys/contrib/device-tree/src/mips/realtek/ |
| H A D | rtl930x.dtsi | 51 interrupt-parent = <&intc>;
117 intc: interrupt-controller@3000 { label
118 compatible = "realtek,rtl9300-intc", "realtek,rtl-intc";
140 interrupt-parent = <&intc>;
154 interrupt-parent = <&intc>;
168 interrupt-parent = <&intc>;
175 interrupt-parent = <&intc>;
189 interrupt-parent = <&intc>;
206 interrupt-parent = <&intc>;
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| H A D | rtl838x.dtsi | 63 interrupt-parent = <&intc>;
80 interrupt-parent = <&intc>;
91 intc: interrupt-controller@3000 { label
92 compatible = "realtek,rtl8380-intc", "realtek,rtl-intc";
110 interrupt-parent = <&intc>;
125 interrupt-parent = <&intc>;
|