| /src/contrib/llvm-project/llvm/lib/MC/ |
| H A D | MCInstrDesc.cpp | 34 for (MCPhysReg ImpDef : implicit_defs()) in hasImplicitDefOfPhysReg()
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| /src/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ScheduleDAGFast.cpp | 425 assert(!MCID.implicit_defs().empty() && in getPhysicalRegisterVT()
428 for (MCPhysReg ImpDef : MCID.implicit_defs()) { in getPhysicalRegisterVT()
525 for (MCPhysReg Reg : MCID.implicit_defs()) in DelayForLiveRegsBottomUp()
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| H A D | FastISel.cpp | 2065 .addReg(II.implicit_defs()[0]); in fastEmitInst_r()
2090 .addReg(II.implicit_defs()[0]); in fastEmitInst_rr()
2117 .addReg(II.implicit_defs()[0]); in fastEmitInst_rrr()
2140 .addReg(II.implicit_defs()[0]); in fastEmitInst_ri()
2165 .addReg(II.implicit_defs()[0]); in fastEmitInst_rii()
2185 .addReg(II.implicit_defs()[0]); in fastEmitInst_f()
2211 .addReg(II.implicit_defs()[0]); in fastEmitInst_rri()
2228 .addReg(II.implicit_defs()[0]); in fastEmitInst_i()
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| H A D | InstrEmitter.cpp | 1051 bool HasPhysRegOuts = NumResults > NumDefs && !II.implicit_defs().empty() && in EmitMachineNode()
1061 II.getNumOperands() + II.implicit_defs().size() + NumImpUses && in EmitMachineNode()
1161 Register Reg = II.implicit_defs()[i - NumDefs]; in EmitMachineNode()
1202 if (!UsedRegs.empty() || !II.implicit_defs().empty() || II.hasOptionalDef()) in EmitMachineNode()
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| H A D | ScheduleDAGRRList.cpp | 1281 assert(!MCID.implicit_defs().empty() && in getPhysicalRegisterVT()
1284 for (MCPhysReg ImpDef : MCID.implicit_defs()) { in getPhysicalRegisterVT()
1435 for (MCPhysReg Reg : MCID.implicit_defs()) in DelayForLiveRegsBottomUp()
2861 TII->get(SU->getNode()->getMachineOpcode()).implicit_defs(); in canClobberReachingPhysRegUse()
2897 ArrayRef<MCPhysReg> ImpDefs = TII->get(N->getMachineOpcode()).implicit_defs(); in canClobberPhysRegDefs()
2904 TII->get(SUNode->getMachineOpcode()).implicit_defs(); in canClobberPhysRegDefs()
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| H A D | ScheduleDAGSDNodes.cpp | 468 !TII->get(N->getMachineOpcode()).implicit_defs().empty()) { in AddSchedEdges()
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| /src/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCInstrDesc.h | 579 ArrayRef<MCPhysReg> implicit_defs() const { in implicit_defs() function
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| /src/contrib/llvm-project/llvm/lib/MCA/ |
| H A D | InstrBuilder.cpp | 318 unsigned NumImplicitDefs = MCDesc.implicit_defs().size(); in populateWrites()
375 Write.RegisterID = MCDesc.implicit_defs()[CurrentDef]; in populateWrites()
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| /src/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenMux.cpp | 163 for (MCPhysReg R : D.implicit_defs()) in getDefsUses()
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| /src/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCTargetDesc.cpp | 437 unsigned NumImplicitDefs = Desc.implicit_defs().size(); in clearsSuperRegisters()
474 const MCPhysReg Reg = Desc.implicit_defs()[I]; in clearsSuperRegisters()
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| /src/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIShrinkInstructions.cpp | 224 MI.getDesc().implicit_defs().size(), in copyExtraImplicitOps()
626 MI.getDesc().implicit_defs().size(), in dropInstructionKeepingImpDefs()
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| H A D | SIFoldOperands.cpp | 1183 Desc.implicit_defs().size(); in mutateCopyOp()
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| H A D | SIInstrInfo.cpp | 4116 return is_contained(MI.getDesc().implicit_defs(), AMDGPU::MODE); in modifiesModeRegister()
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| /src/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86MCTargetDesc.cpp | 538 unsigned NumImplicitDefs = Desc.implicit_defs().size(); in clearsSuperRegisters()
577 const MCPhysReg Reg = Desc.implicit_defs()[I]; in clearsSuperRegisters()
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| /src/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCChecker.cpp | 109 for (MCPhysReg R : MCID.implicit_defs()) { in init()
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| /src/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 313 .addReg(II.implicit_defs()[0])); in fastEmitInst_r()
340 .addReg(II.implicit_defs()[0])); in fastEmitInst_rr()
365 .addReg(II.implicit_defs()[0])); in fastEmitInst_ri()
384 .addReg(II.implicit_defs()[0])); in fastEmitInst_i()
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| H A D | Thumb2SizeReduction.cpp | 256 return is_contained(MCID.implicit_defs(), ARM::CPSR); in HasImplicitCPSRDef()
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| /src/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RDFGraph.cpp | 619 if (D.implicit_defs().empty() && D.implicit_uses().empty()) in isFixedReg()
629 Op.isDef() ? D.implicit_defs() : D.implicit_uses(); in isFixedReg()
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| H A D | MachineInstr.cpp | 89 for (MCPhysReg ImpDef : MCID->implicit_defs()) in addImplicitDefUseOperands()
105 if (unsigned NumOps = MCID->getNumOperands() + MCID->implicit_defs().size() + in MachineInstr()
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| /src/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstr.h | 639 return getNumExplicitDefs() + MCID->implicit_defs().size();
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| /src/contrib/llvm-project/llvm/lib/CodeGen/MIRParser/ |
| H A D | MIParser.cpp | 1439 for (MCPhysReg ImpDef : MCID.implicit_defs()) in verifyImplicitOperands()
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| /src/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FastISel.cpp | 4063 .addReg(II.implicit_defs()[0]); in fastEmitInst_rrrr()
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| /src/contrib/llvm-project/llvm/lib/MC/MCParser/ |
| H A D | AsmParser.cpp | 6085 llvm::append_range(ClobberRegs, Desc.implicit_defs()); in parseMSInlineAsm()
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| H A D | MasmParser.cpp | 7438 llvm::append_range(ClobberRegs, Desc.implicit_defs()); in parseMSInlineAsm()
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| /src/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 2734 for (MCPhysReg ImpDef : NewDesc.implicit_defs()) { in optimizeCompareInstr()
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