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Searched refs:getSchedClassDesc (Results 1 – 12 of 12) sorted by relevance

/src/contrib/llvm-project/llvm/lib/MC/
H A DMCSchedule.cpp60 const MCSchedClassDesc &SCDesc = *getSchedClassDesc(SchedClass); in computeInstrLatency()
73 const MCSchedClassDesc *SCDesc = getSchedClassDesc(SchedClass); in computeInstrLatency()
80 SCDesc = getSchedClassDesc(SchedClass); in computeInstrLatency()
116 const MCSchedClassDesc *SCDesc = getSchedClassDesc(SchedClass); in getReciprocalThroughput()
126 SCDesc = getSchedClassDesc(SchedClass); in getReciprocalThroughput()
/src/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64StorePairSuppress.cpp88 SchedModel.getMCSchedModel()->getSchedClassDesc(SCIdx); in shouldAddSTPToBlock()
92 SchedModel.getMCSchedModel()->getSchedClassDesc(SCIdx2); in shouldAddSTPToBlock()
H A DAArch64SIMDInstrOpt.cpp231 SchedModel.getMCSchedModel()->getSchedClassDesc(SCIdx); in shouldReplaceInst()
243 SCDescRepl = SchedModel.getMCSchedModel()->getSchedClassDesc( in shouldReplaceInst()
/src/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetSchedule.cpp124 const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SchedClass); in resolveSchedClass()
135 SCDesc = SchedModel.getSchedClassDesc(SchedClass); in resolveSchedClass()
329 const MCSchedClassDesc &SCDesc = *SchedModel.getSchedClassDesc(SchedClass); in computeReciprocalThroughput()
H A DMachineCombiner.cpp422 const MCSchedClassDesc *SC = SchedModel.getSchedClassDesc(Idx); in instr2instrSC()
H A DMachinePipeliner.cpp1147 STI->getSchedModel().getSchedClassDesc(SchedClass); in minFuncUnits()
1190 STI->getSchedModel().getSchedClassDesc(SchedClass); in calcCriticalResources()
/src/contrib/llvm-project/llvm/tools/llvm-mca/Views/
H A DInstructionInfoView.cpp130 while (SchedClassID && SM.getSchedClassDesc(SchedClassID)->isVariant()) in collectData()
134 const MCSchedClassDesc &SCDesc = *SM.getSchedClassDesc(SchedClassID); in collectData()
/src/contrib/llvm-project/llvm/lib/MCA/
H A DInstrBuilder.cpp272 const MCSchedClassDesc &SCDesc = *SM.getSchedClassDesc(SchedClassID); in populateWrites()
547 while (SchedClassID && SM.getSchedClassDesc(SchedClassID)->isVariant()) in getVariantSchedClassID()
573 bool IsVariant = SM.getSchedClassDesc(SchedClassID)->isVariant(); in createInstrDescImpl()
587 const MCSchedClassDesc &SCDesc = *SM.getSchedClassDesc(SchedClassID); in createInstrDescImpl()
704 *STI.getSchedModel().getSchedClassDesc(D.SchedClassID); in createInstruction()
/src/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCSchedule.h360 const MCSchedClassDesc *getSchedClassDesc(unsigned SchedClassIdx) const { in getSchedClassDesc() function
/src/contrib/llvm-project/llvm/lib/MCA/HardwareUnits/
H A DRegisterFile.cpp508 const MCSchedClassDesc *SC = SM.getSchedClassDesc(RD.SchedClassID); in collectWrites()
576 const MCSchedClassDesc *SC = SM.getSchedClassDesc(RD.SchedClassID); in checkRAWHazards()
639 const MCSchedClassDesc *SC = SM.getSchedClassDesc(RD.SchedClassID); in addRegisterRead()
/src/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FixupInstTuning.cpp90 *ST, *(SM->getSchedClassDesc(TII->get(Opcode).getSchedClass()))); in processInstruction()
96 *ST, *(SM->getSchedClassDesc(TII->get(Opcode).getSchedClass()))); in processInstruction()
/src/contrib/llvm-project/llvm/lib/MC/MCDisassembler/
H A DDisassembler.cpp210 const MCSchedClassDesc *SCDesc = SCModel.getSchedClassDesc(SCClass); in getLatency()