| /src/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SDNodeDbgValue.h | 48 unsigned getResNo() const { in getResNo() function 90 return getSDNode() == Other.getSDNode() && getResNo() == Other.getResNo();
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| H A D | SelectionDAGPrinter.cpp | 64 std::advance(NI, I.getNode()->getOperand(I.getOperand()).getResNo()); in getEdgeTarget() 131 GW.emitEdge(nullptr, -1, G->getRoot().getNode(), G->getRoot().getResNo(), in addCustomGraphFeatures()
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| H A D | ScheduleDAGSDNodes.cpp | 126 unsigned ResNo = User->getOperand(2).getResNo(); in CheckForPhysRegDependency() 241 if (I.getUse().getResNo() != Chain.getResNo()) in ClusterNeighboringLoads() 479 unsigned DefIdx = N->getOperand(i).getResNo(); in AddSchedEdges() 659 unsigned DefIdx = Use->getOperand(OpIdx).getResNo(); in computeOperandLatency() 749 VRBaseMap.count({L.getSDNode(), L.getResNo()}) == 0) in ProcessSDDbgValues()
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| H A D | ResourcePriorityQueue.cpp | 131 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in numberRCValSuccInSU() 335 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in rawRegPressureDelta() 485 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in scheduledNode()
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| H A D | InstrEmitter.cpp | 113 User->getOperand(2).getResNo() == ResNo) { in EmitCopyFromReg() 123 if (Op.getNode() != Node || Op.getResNo() != ResNo) in EmitCopyFromReg() 125 MVT VT = Node->getSimpleValueType(Op.getResNo()); in EmitCopyFromReg() 232 User->getOperand(2).getResNo() == i) { in CreateVirtualRegisters() 768 SDValue V = SDValue(Op.getSDNode(), Op.getResNo()); in AddDbgValueLocationOps() 864 SDValue Op = SDValue(Node, DbgOperand.getResNo()); in EmitDbgInstrRef()
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| H A D | SelectionDAG.cpp | 697 ID.AddInteger(Op.getResNo()); in AddNodeIDOperands() 706 ID.AddInteger(Op.getResNo()); in AddNodeIDOperands() 3174 return computeKnownBits(Op.getOperand(Op.getResNo()), DemandedElts, in computeKnownBits() 3492 assert((Op.getResNo() == 0 || Op.getResNo() == 1) && "Unknown result"); in computeKnownBits() 3496 if (Op.getResNo() == 0) in computeKnownBits() 3503 assert((Op.getResNo() == 0 || Op.getResNo() == 1) && "Unknown result"); in computeKnownBits() 3507 if (Op.getResNo() == 0) in computeKnownBits() 3560 if (Op.getResNo() != 1) in computeKnownBits() 3651 assert((Op.getResNo() == 0 || Op.getResNo() == 1) && "Unknown result"); in computeKnownBits() 3672 if (Op.getResNo() == 0) in computeKnownBits() [all …]
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| H A D | SelectionDAGAddressAnalysis.cpp | 244 if (LSBase->isIndexed() && Base.getResNo() == IndexResNo) in matchLSNode()
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| H A D | SelectionDAGDumper.cpp | 957 OS << "SDNODE=" << PrintNodeId(*Op.getSDNode()) << ':' << Op.getResNo(); in print() 1066 if (unsigned RN = Value.getResNo()) in printOperand()
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| H A D | SelectionDAGBuilder.cpp | 985 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), &Parts[Part], in getCopyToRegs() 1216 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(), in handleDebugDeclare() 1649 SDDbgOperand::fromNode(N.getNode(), N.getResNo())); in handleDebugValue() 2219 SDValue Val = RetOp.getValue(RetOp.getResNo() + i); in visitRet() 2265 SDValue(RetOp.getNode(), RetOp.getResNo() + j), in visitRet() 3803 EVT VT = LHSVal.getNode()->getValueType(LHSVal.getResNo() + i); in visitSelect() 3805 DAG.getNode(OpCode, dl, VT, LHSVal.getValue(LHSVal.getResNo() + i)); in visitSelect() 3812 Ops.push_back(SDValue(LHSVal.getNode(), LHSVal.getResNo() + i)); in visitSelect() 3813 Ops.push_back(SDValue(RHSVal.getNode(), RHSVal.getResNo() + i)); in visitSelect() 3816 LHSVal.getNode()->getValueType(LHSVal.getResNo() + i), Ops, Flags); in visitSelect() [all …]
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| H A D | ScheduleDAGFast.cpp | 224 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in CopyAndMoveSuccessors()
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| H A D | LegalizeTypes.cpp | 93 if (UI.getUse().getResNo() == i) in PerformExpensiveChecks()
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| H A D | LegalizeVectorOps.cpp | 245 return SDValue(Result, Op.getResNo()); in TranslateLegalizeResults() 259 return Results[Op.getResNo()]; in RecursivelyLegalizeResults()
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| H A D | DAGCombiner.cpp | 3086 if (V.getResNo() != 1) in getAsCarry() 3210 N1.getResNo() == 0) in visitADDLikeCommutative() 3467 if (Carry1.getResNo() != 1 || Carry0.getResNo() != 1) in combineUADDO_CARRYDiamond() 3646 (N0.getOpcode() == ISD::UADDO && N0.getResNo() == 0 && in visitUADDO_CARRYLike() 4090 N0.getResNo() == 0 && N0.hasOneUse()) in visitSUB() 7086 N0.getOperand(0).getResNo() == 0) || in visitAND() 7087 (N0.getOpcode() == ISD::LOAD && N0.getResNo() == 0)) { in visitAND() 12961 if (UI.getUse().getResNo() != N0.getResNo()) in ExtendUsesToFormExtLoad() 12996 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { in ExtendUsesToFormExtLoad() 13511 if (UI.getUse().getResNo() != 0 || User == N0.getNode()) in foldSextSetcc() [all …]
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| /src/contrib/llvm-project/llvm/utils/TableGen/Common/ |
| H A D | DAGISelMatcher.cpp | 362 if (CT->getResNo() >= getOpcode().getNumResults()) in isContradictoryImpl() 365 MVT::SimpleValueType NodeType = getOpcode().getKnownType(CT->getResNo()); in isContradictoryImpl()
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| H A D | DAGISelMatcher.h | 528 unsigned getResNo() const { return ResNo; } in getResNo() function
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| /src/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | DAGISelMatcherOpt.cpp | 53 CT->getResNo() == 0) // CheckChildType checks res #0 in ContractNodes() 405 CTM->getResNo() != 0 || in FactorNodes()
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| H A D | DAGISelMatcherEmitter.cpp | 643 if (cast<CheckTypeMatcher>(N)->getResNo() == 0) { in EmitMatcher() 655 OS << "OPC_CheckTypeRes, " << cast<CheckTypeMatcher>(N)->getResNo() << ", " in EmitMatcher()
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| /src/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | SelectionDAGNodes.h | 156 unsigned getResNo() const { return ResNo; } 254 (unsigned)((uintptr_t)Val.getNode() >> 9)) + Val.getResNo(); 316 unsigned getResNo() const { return Val.getResNo(); } 3262 return (Op.getResNo() == 1 &&
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| H A D | SDPatternMatch.h | 149 return P.match(Ctx, N) && N->hasNUsesOfValue(NumUses, N.getResNo()); in match()
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| /src/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 1575 if (Op0 != N->getOperand(1) || !Op0->hasNUsesOfValue(2, Op0.getResNo()) || in PostprocessISelDAG() 2571 if (N.getResNo() != 0) break; in matchAddressRecursively() 3282 if (UI.getUse().getResNo() != Flags.getResNo()) in onlyUsesZeroFlag() 3292 if (FlagUI.getUse().getResNo() != 1) continue; in onlyUsesZeroFlag() 3318 if (UI.getUse().getResNo() != Flags.getResNo()) in hasNoSignFlagUses() 3328 if (FlagUI.getUse().getResNo() != 1) continue; in hasNoSignFlagUses() 3374 if (UI.getUse().getResNo() != Flags.getResNo()) in hasNoCarryFlagUses() 3387 if (FlagUI.getUse().getResNo() != 1) in hasNoCarryFlagUses() 3431 if (StoredVal.getResNo() != 0) return false; in isFusableLoadOpStorePattern() 3807 Op.getNode()->hasNUsesOfValue(NUses, Op.getResNo()); in matchBitExtract()
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| H A D | X86InstrFragments.td | 684 N->getOperand(0).getResNo() == 1);
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| /src/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 1911 if (Op.getResNo() != 0 || NeedOF || NeedCF) { in EmitTest() 2237 if (Op.getResNo() == 1 && in isM68kLogicalCmp() 2243 if (Op.getResNo() == 2 && Opc == M68kISD::UMUL) in isM68kLogicalCmp() 2463 Cond.getOperand(0).getResNo() == 1 && in LowerBRCOND()
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| /src/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 3064 CmpOp0.getResNo() == 0 && CmpOp0->hasNUsesOfValue(1, 0) && in getCmp() 3069 CmpOp0.getResNo() == CmpOp0->getNumValues() - 1 && in getCmp() 3429 return Res.getValue(Op.getResNo()); in lowerSTRICT_FSETCC() 6811 if (UI.getUse().getResNo() != 0) in isI128MovedToParts() 6847 if (UI.getUse().getResNo() != 0) in isF128MovedToParts() 6934 else if (UI.getUse().getResNo() == 0) in combineLOAD() 6946 Ops.push_back((Op.getNode() == N && Op.getResNo() == 0) ? Extract0 : Op); in combineLOAD() 7966 if (Op.getResNo() == 1 && isIntrinsicWithCC(Op, tmp0, tmp1)) { in computeKnownBitsForTargetNode() 7971 if (Op.getResNo() != 0 || VT == MVT::Untyped) in computeKnownBitsForTargetNode() 8078 if (Op.getResNo() != 0) in ComputeNumSignBitsForTargetNode()
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| H A D | SystemZISelDAGToDAG.cpp | 1308 if (StoredVal.getResNo() != 0) in isFusableLoadOpStorePattern()
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| /src/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 5140 if (Cond.getResNo() == 1 && in LowerSELECT() 5722 if (Cond.getResNo() == 1 && in LowerBRCOND() 5773 if (LHS.getResNo() == 1 && (isOneConstant(RHS) || isNullConstant(RHS)) && in LowerBR_CC() 13741 VecRed.getResNo() != 0 || in PerformADDVecReduce() 15155 Op0.getResNo() == 0 && Op1.getResNo() == 1) in PerformVMOVDRRCombine() 15536 unsigned ResNo = Op0.getResNo(); in PerformExtractEltToVMOVRRD() 15546 V->getOperand(0).getResNo() == ResNo; in PerformExtractEltToVMOVRRD() 16172 if (UI.getUse().getResNo() != Addr.getResNo() || in CombineBaseUpdate() 16195 if (UI.getUse().getResNo() != Base.getResNo() || User == Addr.getNode() || in CombineBaseUpdate() 16277 UI.getUse().getResNo() != Addr.getResNo()) in PerformMVEVLDCombine() [all …]
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