| /src/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyMachineFunctionInfo.cpp | 51 MVT RegisterVT = TLI.getRegisterType(Ctx, VT); in computeLegalValueVTs()
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| /src/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FunctionLoweringInfo.cpp | 388 MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT); in CreateRegs()
451 IntVT = TLI->getRegisterType(PN->getContext(), IntVT); in ComputePHILiveOutRegInfo()
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| H A D | FastISel.cpp | 1015 MVT RegisterVT = TLI.getRegisterType(CLI.RetTy->getContext(), VT); in lowerCallTo()
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| H A D | LegalizeDAG.cpp | 873 EVT LoadVT = TLI.getRegisterType(SrcVT.getSimpleVT()); in LegalizeLoadOps()
899 EVT ILoadVT = TLI.getRegisterType(IDestVT.getSimpleVT()); in LegalizeLoadOps()
1583 MVT LoadTy = TLI.getRegisterType(MVT::i8); in getSignAsIntValue()
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| H A D | SelectionDAGBuilder.cpp | 868 : TLI.getRegisterType(Context, ValueVT); in RegsForValue()
10816 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), RetVT); in LowerCallTo()
11461 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]); in LowerArguments()
11651 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT); in LowerArguments()
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| H A D | TargetLowering.cpp | 9819 MVT RegVT = getRegisterType(*DAG.getContext(), intVT); in expandUnalignedLoad()
9967 MVT RegVT = getRegisterType( in expandUnalignedStore()
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| H A D | LegalizeIntegerTypes.cpp | 1860 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT); in PromoteIntRes_VAARG()
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| /src/contrib/llvm-project/llvm/include/llvm/DebugInfo/PDB/Native/ |
| H A D | NativeRawSymbol.h | 104 uint32_t getRegisterType() const override;
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| /src/contrib/llvm-project/llvm/include/llvm/DebugInfo/PDB/DIA/ |
| H A D | DIARawSymbol.h | 99 uint32_t getRegisterType() const override;
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| /src/contrib/llvm-project/llvm/include/llvm/DebugInfo/PDB/ |
| H A D | IPDBRawSymbol.h | 125 virtual uint32_t getRegisterType() const = 0;
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| /src/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 1711 MVT getRegisterType(MVT VT) const { in getRegisterType() function
1717 MVT getRegisterType(LLVMContext &Context, EVT VT) const { in getRegisterType() function
1719 return getRegisterType(VT.getSimpleVT()); in getRegisterType()
1729 return getRegisterType(Context, getTypeToTransformTo(Context, VT)); in getRegisterType()
1761 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
1772 return getRegisterType(Context, VT); in getRegisterTypeForCallingConv()
4812 EVT MinVT = getRegisterType(MVT::i32); in getTypeForExtReturn()
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| /src/contrib/llvm-project/llvm/lib/DebugInfo/PDB/Native/ |
| H A D | NativeRawSymbol.cpp | 250 uint32_t NativeRawSymbol::getRegisterType() const { in getRegisterType() function in NativeRawSymbol
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| /src/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 1108 MVT DestVT = TLI->getRegisterType(NewVT); in getVectorTypeBreakdownMVT()
1565 RegisterVT = getRegisterType(Context, IntermediateVT); in getVectorTypeBreakdown()
1591 MVT DestVT = getRegisterType(Context, NewVT); in getVectorTypeBreakdown()
1631 return getRegisterType(Context, ConditionVT); in getPreferredSwitchConditionType()
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| /src/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVISelLowering.cpp | 54 return getRegisterType(Context, VT); in getRegisterTypeForCallingConv()
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| /src/contrib/llvm-project/llvm/lib/DebugInfo/PDB/DIA/ |
| H A D | DIARawSymbol.cpp | 746 uint32_t DIARawSymbol::getRegisterType() const { in getRegisterType() function in DIARawSymbol
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| /src/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 104 return getRegisterType(Context, VT); in getRegisterTypeForCallingConv()
109 return getRegisterType(Context, VT.getVectorElementType()); in getRegisterTypeForCallingConv()
135 RegisterVT = getRegisterType(Context, IntermediateVT); in getVectorTypeBreakdownForCallingConv()
4056 EVT MinVT = getRegisterType(Cond ? MVT::i64 : MVT::i32); in getTypeForExtReturn()
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| H A D | MipsSEISelLowering.cpp | 783 .getRegisterType(*DAG.getContext(), VT) in shouldTransformMulToShiftsAddsSubs()
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| /src/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLoweringCall.cpp | 993 EVT MinVT = getRegisterType(Context, ReturnMVT); in getTypeForExtReturn()
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| /src/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 28676 RegisterVT = getRegisterType(Context, NewVT); in getVectorTypeBreakdownForCallingConv()
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