| /src/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetFrameLoweringImpl.cpp | 52 const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo(); in getFrameIndexReference()
85 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); in getCalleeSaves()
99 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); in determineCalleeSaves()
152 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); in allocateScavengingFrameIndexesNearIncomingSP()
180 const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo(); in getDwarfFrameBase()
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| /src/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCCodeEmitter.cpp | 547 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg); in getMachineOpValue()
587 Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); in EncodeAddrModeOpValues()
922 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); in getThumbAddrModeRegRegOpValue()
923 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg()); in getThumbAddrModeRegRegOpValue()
981 Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); in getAddrModeImm12OpValue()
987 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. in getAddrModeImm12OpValue()
1058 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(M0.getReg()); in getMveAddrModeRQOpValue()
1059 unsigned Qm = CTX.getRegisterInfo()->getEncodingValue(M1.getReg()); in getMveAddrModeRQOpValue()
1078 unsigned Qm = CTX.getRegisterInfo()->getEncodingValue(M0.getReg()); in getMveAddrModeQOpValue()
1112 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. in getT2AddrModeImm8s4OpValue()
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| /src/contrib/llvm-project/llvm/lib/Target/XCore/ |
| H A D | XCoreMachineFunctionInfo.cpp | 46 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); in createLRSpillSlot()
64 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); in createFPSpillSlot()
77 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); in createEHSpillSlot()
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| H A D | XCoreSubtarget.h | 59 const TargetRegisterInfo *getRegisterInfo() const override { in getRegisterInfo() function
60 return &InstrInfo.getRegisterInfo(); in getRegisterInfo()
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| /src/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsFrameLowering.cpp | 95 const TargetRegisterInfo *TRI = STI.getRegisterInfo(); in hasFP()
104 const TargetRegisterInfo *TRI = STI.getRegisterInfo(); in hasBP()
116 const TargetRegisterInfo &TRI = *STI.getRegisterInfo(); in estimateStackSize()
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| /src/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXPeephole.cpp | 98 MF.getSubtarget<NVPTXSubtarget>().getRegisterInfo(); in isCVTAToLocalCombinationCandidate()
117 MF.getSubtarget<NVPTXSubtarget>().getRegisterInfo(); in CombineCVTAToLocal()
154 MF.getSubtarget<NVPTXSubtarget>().getRegisterInfo(); in runOnMachineFunction()
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| H A D | NVPTXSubtarget.h | 66 const NVPTXRegisterInfo *getRegisterInfo() const override { in getRegisterInfo() function
67 return &InstrInfo.getRegisterInfo(); in getRegisterInfo()
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| /src/contrib/llvm-project/llvm/lib/Target/CSKY/MCTargetDesc/ |
| H A D | CSKYMCCodeEmitter.cpp | 239 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()); in getMachineOpValue()
258 unsigned Imm = Ctx.getRegisterInfo()->getEncodingValue(Rz) - in getRegSeqImmOpValue()
259 Ctx.getRegisterInfo()->getEncodingValue(Ry); in getRegSeqImmOpValue()
261 return ((Ctx.getRegisterInfo()->getEncodingValue(Ry) << 5) | Imm); in getRegSeqImmOpValue()
269 Ctx.getRegisterInfo()->getEncodingValue(MI.getOperand(Op).getReg()); in getRegisterSeqOpValue()
271 Ctx.getRegisterInfo()->getEncodingValue(MI.getOperand(Op + 1).getReg()); in getRegisterSeqOpValue()
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| /src/contrib/llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCSubtarget.h | 58 const ARCRegisterInfo *getRegisterInfo() const override { in getRegisterInfo() function
59 return &InstrInfo.getRegisterInfo(); in getRegisterInfo()
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| /src/contrib/llvm-project/llvm/lib/Target/Xtensa/ |
| H A D | XtensaSubtarget.h | 54 const XtensaRegisterInfo *getRegisterInfo() const override { in getRegisterInfo() function
55 return &InstrInfo.getRegisterInfo(); in getRegisterInfo()
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| /src/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiSubtarget.h | 54 const LanaiRegisterInfo *getRegisterInfo() const override { in getRegisterInfo() function
55 return &InstrInfo.getRegisterInfo(); in getRegisterInfo()
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| /src/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VESubtarget.h | 55 const VERegisterInfo *getRegisterInfo() const override { in getRegisterInfo() function
56 return &InstrInfo.getRegisterInfo(); in getRegisterInfo()
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| /src/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430Subtarget.h | 67 const MSP430RegisterInfo *getRegisterInfo() const override { in getRegisterInfo() function
68 return &getInstrInfo()->getRegisterInfo(); in getRegisterInfo()
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| /src/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcSubtarget.h | 60 const SparcRegisterInfo *getRegisterInfo() const override { in getRegisterInfo() function
61 return &InstrInfo.getRegisterInfo(); in getRegisterInfo()
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| /src/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRSubtarget.h | 52 const AVRRegisterInfo *getRegisterInfo() const override { in getRegisterInfo() function
53 return &InstrInfo.getRegisterInfo(); in getRegisterInfo()
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| /src/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblySubtarget.h | 84 const WebAssemblyRegisterInfo *getRegisterInfo() const override { in getRegisterInfo() function
85 return &getInstrInfo()->getRegisterInfo(); in getRegisterInfo()
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| /src/contrib/llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFSubtarget.h | 108 const BPFRegisterInfo *getRegisterInfo() const override { in getRegisterInfo() function
109 return &InstrInfo.getRegisterInfo(); in getRegisterInfo()
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| /src/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchFrameLowering.cpp | 35 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); in hasFP()
45 const TargetRegisterInfo *TRI = STI.getRegisterInfo(); in hasBP()
143 const LoongArchRegisterInfo *RI = STI.getRegisterInfo(); in processFunctionBeforeFrameFinalized()
184 const LoongArchRegisterInfo *RI = STI.getRegisterInfo(); in emitPrologue()
308 const LoongArchRegisterInfo *RI = STI.getRegisterInfo(); in emitEpilogue()
457 const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo(); in getFrameIndexReference()
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| /src/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SILowerSGPRSpills.cpp | 92 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); in insertCSRSaves()
94 const SIRegisterInfo *RI = ST.getRegisterInfo(); in insertCSRSaves()
135 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); in insertCSRRestores()
137 const SIRegisterInfo *RI = ST.getRegisterInfo(); in insertCSRRestores()
312 TRI = &TII->getRegisterInfo(); in runOnMachineFunction()
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| H A D | SILowerI1Copies.h | 76 return TII->getRegisterInfo().isSGPRReg(*MRI, Reg) && in isLaneMaskReg()
77 TII->getRegisterInfo().getRegSizeInBits(Reg, *MRI) == in isLaneMaskReg()
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| H A D | R600Subtarget.h | 60 const R600RegisterInfo *getRegisterInfo() const override { in getRegisterInfo() function
61 return &InstrInfo.getRegisterInfo(); in getRegisterInfo()
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| H A D | SIFrameLowering.cpp | 80 const SIRegisterInfo *TRI = ST.getRegisterInfo(); in getVGPRSpillLaneOrTempRegister()
182 const SIRegisterInfo *TRI = &TII->getRegisterInfo(); in buildGitPtr()
387 const SIRegisterInfo *TRI = &TII->getRegisterInfo(); in emitEntryFunctionFlatScratchInit()
542 const SIRegisterInfo *TRI = &TII->getRegisterInfo(); in getEntryFunctionReservedScratchRsrcReg()
612 const SIRegisterInfo *TRI = &TII->getRegisterInfo(); in emitEntryFunctionPrologue()
736 const SIRegisterInfo *TRI = &TII->getRegisterInfo(); in emitEntryFunctionScratchRsrcRegSetup()
897 const SIRegisterInfo &TRI = TII->getRegisterInfo(); in buildScratchExecCopy()
928 const SIRegisterInfo &TRI = TII->getRegisterInfo(); in emitCSRSpillStores()
1014 const SIRegisterInfo &TRI = TII->getRegisterInfo(); in emitCSRSpillRestores()
1086 const SIRegisterInfo &TRI = TII->getRegisterInfo(); in emitPrologue()
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| /src/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZSubtarget.h | 77 const SystemZRegisterInfo *getRegisterInfo() const override { in getRegisterInfo() function
78 return &InstrInfo.getRegisterInfo(); in getRegisterInfo()
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| /src/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVFrameLowering.cpp | 65 const llvm::RISCVRegisterInfo *TRI = STI.getRegisterInfo(); in emitSCSPrologue()
127 Register RAReg = STI.getRegisterInfo()->getRARegister(); in emitSCSEpilogue()
160 nullptr, STI.getRegisterInfo()->getDwarfRegNum(SCSPReg, /*IsEH*/ true))); in emitSCSEpilogue()
313 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); in hasFP()
323 const TargetRegisterInfo *TRI = STI.getRegisterInfo(); in hasBP()
356 const TargetRegisterInfo *TRI = STI.getRegisterInfo(); in determineFrameLayout()
436 const RISCVRegisterInfo &RI = *STI.getRegisterInfo(); in adjustStackForRVV()
529 const RISCVRegisterInfo *RI = STI.getRegisterInfo(); in emitPrologue()
721 const RISCVRegisterInfo *RI = STI.getRegisterInfo(); in emitPrologue()
760 const RISCVRegisterInfo *RI = STI.getRegisterInfo(); in emitEpilogue()
[all …]
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| /src/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVSubtarget.h | 124 const SPIRVRegisterInfo *getRegisterInfo() const override { in getRegisterInfo() function
125 return &InstrInfo.getRegisterInfo(); in getRegisterInfo()
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