| /src/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIPostRABundler.cpp | 154 if (I->getNumExplicitDefs() != 0) in runOnMachineFunction()
166 if (I->getNumExplicitDefs() != 0) in runOnMachineFunction()
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| H A D | AMDGPUInstrInfo.cpp | 31 return I.getOperand(I.getNumExplicitDefs()).getIntrinsicID(); in getIntrinsicID()
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| H A D | SIFixSGPRCopies.cpp | 953 } else if (Inst->getNumExplicitDefs() != 0) { in analyzeVGPRToSGPRCopy()
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| H A D | AMDGPULegalizerInfo.cpp | 4692 const unsigned FirstSrcOpIdx = MI.getNumExplicitDefs(); in legalizeUnsignedDIV_REM()
4718 const unsigned FirstSrcOpIdx = MI.getNumExplicitDefs(); in legalizeSignedDIV_REM()
5926 assert(MI.getNumExplicitDefs() == 1 || MI.getNumExplicitDefs() == 2); in legalizeBufferLoad()
5927 bool IsTFE = MI.getNumExplicitDefs() == 2; in legalizeBufferLoad()
6321 const unsigned NumDefs = MI.getNumExplicitDefs(); in legalizeImageIntrinsic()
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| H A D | AMDGPURegisterBankInfo.cpp | 324 for (unsigned I = 0, E = MI.getNumExplicitDefs(); I != E; ++I) { in addMappingFromTable()
1220 const int NumDefs = MI.getNumExplicitDefs(); in applyMappingImage()
3588 RsrcIdx += MI.getNumExplicitDefs() + 1; in getImageMapping()
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| H A D | SIFoldOperands.cpp | 2027 if (!ST->hasGFX90AInsts() || MI.getNumExplicitDefs() != 1) in tryFoldLoad()
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| /src/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstr.h | 639 return getNumExplicitDefs() + MCID->implicit_defs().size();
673 unsigned getNumExplicitDefs() const;
724 operands_begin() + getNumExplicitDefs());
729 operands_begin() + getNumExplicitDefs());
734 return make_range(operands_begin() + getNumExplicitDefs(), operands_end());
738 return make_range(operands_begin() + getNumExplicitDefs(), operands_end());
741 return make_range(operands_begin() + getNumExplicitDefs(),
745 return make_range(operands_begin() + getNumExplicitDefs(),
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| /src/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVVectorPeephole.cpp | 231 unsigned MaskOpIdx = I->MaskOpIdx + MI.getNumExplicitDefs(); in convertToUnmasked()
237 unsigned PassthruOpIdx = MI.getNumExplicitDefs(); in convertToUnmasked()
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| H A D | RISCVOptWInstrs.cpp | 137 if (MI->getNumExplicitDefs() != 1) in hasAllNBitUsers()
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| H A D | RISCVAsmPrinter.cpp | 979 if (OpNo == MI->getNumExplicitDefs() && MO.isReg() && MO.isTied()) { in lowerRISCVVMachineInstrToMCInst()
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| H A D | RISCVInsertVSETVLI.cpp | 427 if (RISCVII::hasSEWOp(TSFlags) && MI.getNumExplicitDefs() == 0) { in getDemanded()
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| /src/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyMCInstLower.cpp | 171 unsigned NumVariadicDefs = MI->getNumExplicitDefs() - Desc.getNumDefs(); in lower()
269 OutMI.insert(OutMI.begin(), MCOperand::createImm(MI->getNumExplicitDefs())); in lower()
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| H A D | WebAssemblyUtilities.cpp | 92 return MI.getOperand(MI.getNumExplicitDefs()); in getCalleeOp()
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| /src/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVDuplicatesTracker.cpp | 93 if (MI.getNumExplicitDefs() > 0 && in buildDepsGraph()
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| H A D | SPIRVInstructionSelector.cpp | 1425 for (unsigned i = I.getNumExplicitDefs(); i < I.getNumExplicitOperands(); ++i) in selectConstVector()
1472 for (unsigned i = OpDef->getNumExplicitDefs(); i < OpDef->getNumOperands(); in isConstReg()
1506 unsigned OpIdx = I.getNumExplicitDefs(); in selectSplatVector()
1914 for (unsigned i = I.getNumExplicitDefs() + 1; i < Lim; ++i) { in wrapIntoSpecConstantOp()
1990 bool IsNull = I.getNumExplicitDefs() + 1 == I.getNumExplicitOperands(); in selectIntrinsic()
2011 MIB.addUse(I.getOperand(I.getNumExplicitDefs() + 1).getReg()); in selectIntrinsic()
2012 for (unsigned i = I.getNumExplicitDefs() + 2; in selectIntrinsic()
2068 int64_t Size = I.getOperand(I.getNumExplicitDefs() + 1).getImm(); in selectIntrinsic()
2069 Register PtrReg = I.getOperand(I.getNumExplicitDefs() + 2).getReg(); in selectIntrinsic()
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| H A D | SPIRVPreLegalizer.cpp | 136 unsigned NumOp = MI.getNumExplicitDefs() + AssignNameOperandShift; in foldConstantsIntoIntrinsics()
529 MI.getNumExplicitOperands() - MI.getNumExplicitDefs(); in generateAssignInstrs()
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| /src/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMFixCortexA57AES1742098Pass.cpp | 288 assert(MI.getNumExplicitOperands() == 3 && MI.getNumExplicitDefs() == 1 && in analyzeMF()
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| /src/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchOptWInstrs.cpp | 116 if (MI->getNumExplicitDefs() != 1) in hasAllNBitUsers()
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| /src/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | GenericMachineInstrs.h | 512 return getOperand(getNumExplicitDefs()).getIntrinsicID(); in getIntrinsicID()
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| /src/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineCSE.cpp | 812 MI->getNumExplicitDefs() != 1) in isPRECandidate()
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| H A D | TwoAddressInstructionPass.cpp | 799 assert(mi->getNumExplicitDefs() == 1); in convertInstTo3Addr()
800 assert(NewMI->getNumExplicitDefs() == 1); in convertInstTo3Addr()
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| H A D | TargetInstrInfo.cpp | 1608 if (MI.getNumExplicitDefs() != 1) in describeLoadedValue()
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| H A D | MachineInstr.cpp | 809 unsigned MachineInstr::getNumExplicitDefs() const { in getNumExplicitDefs() function in MachineInstr
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| /src/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | GISelKnownBits.cpp | 62 assert(MI.getNumExplicitDefs() == 1 && in getKnownBits()
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| /src/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64RegisterBankInfo.cpp | 1108 Idx += MI.getNumExplicitDefs(); in getInstrMapping()
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