| /src/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VECustomDAG.cpp | 419 return DAG.getNOT(DL, Res, Res.getValueType()); in getConstantMask()
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| /src/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 1610 SDValue New = TLO.DAG.getNOT(dl, Op0, VT); in SimplifyDemandedBits() 1632 SDValue Not = TLO.DAG.getNOT(dl, Op0.getOperand(0), VT); in SimplifyDemandedBits() 4061 SDValue NotX = DAG.getNOT(SDLoc(X), X, OpVT); in foldSetCCWithAnd() 5282 SDValue Not = DAG.getNOT(dl, N1, OpVT); in SimplifySetCC() 5387 N0 = DAG.getNOT(dl, Temp, OpVT); in SimplifySetCC() 5396 Temp = DAG.getNOT(dl, N0, OpVT); in SimplifySetCC() 5403 Temp = DAG.getNOT(dl, N1, OpVT); in SimplifySetCC() 5410 Temp = DAG.getNOT(dl, N0, OpVT); in SimplifySetCC() 5417 Temp = DAG.getNOT(dl, N1, OpVT); in SimplifySetCC() 8016 Z = DAG.getNOT(DL, Z, ShVT); in expandFunnelShift() [all …]
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| H A D | LegalizeVectorOps.cpp | 1191 SDValue NotMask = DAG.getNOT(DL, Mask, MaskTy); in ExpandSELECT() 1454 SDValue NotMask = DAG.getNOT(DL, Mask, VT); in ExpandVSELECT()
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| H A D | DAGCombiner.cpp | 2697 SDValue Not = DAG.getNOT(DL, X, X.getValueType()); in visitADDLike() 2847 SDValue Not = DAG.getNOT(DL, N0.getOperand(0), VT); in visitADDLike() 2855 SDValue Not = DAG.getNOT(DL, N0.getOperand(1), VT); in visitADDLike() 3159 SDValue Not = DAG.getNOT(DL, N0.getOperand(0), VT); in visitADDLikeCommutative() 3948 return DAG.getNode(ISD::AND, DL, VT, N0, DAG.getNOT(DL, B, VT)); in visitSUB() 3979 return DAG.getNode(ISD::ADD, DL, VT, A, DAG.getNOT(DL, B, VT)); in visitSUB() 6056 SDValue Mask = DAG.getNOT(DL, Diff, OpVT); in foldLogicOfSetCCs() 6314 SDValue NotOp = DAG.getNOT(DL, LHS0, OpVT); in foldAndOrOfSETCC() 7829 return DAG.getNOT(DL, DAG.getNode(ISD::OR, DL, VT, Lo, Hi), VT); in visitORCommutative() 9359 SDValue NotX = DAG.getNOT(DL, X, VT); in unfoldMaskedMerge() [all …]
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| H A D | SelectionDAG.cpp | 1580 SDValue SelectionDAG::getNOT(const SDLoc &DL, SDValue Val, EVT VT) { in getNOT() function in SelectionDAG 6196 return getNOT(DL, N1, N1.getValueType()); in getNode() 6990 return getNode(ISD::AND, DL, VT, N1, getNOT(DL, N2, VT)); in getNode() 10208 SDValue NotF1 = getNOT(DL, F1, VTList.VTs[0]); in getNode()
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| H A D | LegalizeDAG.cpp | 3766 Tmp1 = DAG.getNOT(dl, Node->getOperand(1), VT); in ExpandNode()
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| H A D | LegalizeIntegerTypes.cpp | 4540 SignsMatch = DAG.getNOT(dl, SignsMatch, VT); in ExpandIntRes_SADDSUBO()
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| /src/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 1522 DAG.getNOT(DL, Bit, ResTy)); in lowerMSABitClear() 2083 return DAG.getNOT(DL, Res, Res->getValueType(0)); in lowerINTRINSIC_WO_CHAIN() 2089 return DAG.getNOT(DL, Res, Res->getValueType(0)); in lowerINTRINSIC_WO_CHAIN()
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| /src/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 2315 Res = DAG.getNOT(DL, Res, Res.getValueType()); in LowerSELECT() 2388 return DAG.getNOT(DL, Res, Res.getValueType()); in LowerSELECT()
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| /src/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelLowering.cpp | 1083 DstMask = DAG.getNOT(DL, DstMask, MVT::i32); in lowerPrivateTruncStore()
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| H A D | AMDGPUISelLowering.cpp | 2433 SDValue Not = DAG.getNOT(SL, Shr, MVT::i64); in LowerFTRUNC()
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| H A D | SIISelLowering.cpp | 7268 DAG.getNOT(SL, BFM, IntVT), BCVec); in lowerINSERT_VECTOR_ELT()
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| /src/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | SelectionDAG.h | 1029 SDValue getNOT(const SDLoc &DL, SDValue Val, EVT VT);
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| /src/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 22389 V = DAG.getNOT(DL, V, VT); in LowerVectorAllEqual() 22428 V = DAG.getNOT(DL, V, MaskVT); in LowerVectorAllEqual() 23551 Result = DAG.getNOT(dl, Result, VT); in LowerVSETCC() 23648 Result = DAG.getNOT(dl, Result, MVT::v4i32); in LowerVSETCC() 23671 Result = DAG.getNOT(dl, Result, MVT::v4i32); in LowerVSETCC() 23691 Result = DAG.getNOT(dl, Result, VT); in LowerVSETCC() 24234 Shift = DAG.getNOT(DL, Shift, VT); in LowerSELECT() 24310 return DAG.getNOT(DL, Res, Res.getValueType()); in LowerSELECT() 45549 AndN = DAG.getNode(ISD::AND, DL, CondVT, DAG.getNOT(DL, Cond, CondVT), in combineVSelectWithAllOnesOrZeros() 45642 Cond = DAG.getNOT(DL, Cond, MVT::i1); in combineSelectOfTwoConstants() [all …]
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| H A D | X86ISelDAGToDAG.cpp | 930 Complement = CurDAG->getNOT(dl, Complement, VT); in PreprocessISelDAG()
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| /src/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 2870 Ret = DAG.getNOT(DL, Ret, MVT::i1); in performSETCCCombine()
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| /src/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 3681 DAG.getNOT(DL, Bit, ResTy)); in lowerVectorBitClear() 3971 return DAG.getNOT(DL, Res, Res->getValueType(0)); in performINTRINSIC_WO_CHAINCombine()
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| /src/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 4166 DAG.getSelect(dl, VTy, HiIsZero, Lo, DAG.getNOT(dl, Lo, VTy)); in LowerINTRINSIC_WO_CHAIN() 6825 Merged = DAG.getNOT(dl, Merged, CmpVT); in LowerVSETCC() 6867 Result = DAG.getNOT(dl, Result, VT); in LowerVSETCC() 6879 Result = DAG.getNOT(dl, Result, VT); in LowerVSETCC() 6921 Result = DAG.getNOT(dl, Result, VT); in LowerVSETCC() 6955 Result = DAG.getNOT(dl, Result, VT); in LowerVSETCC()
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| /src/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 10485 Shift = DAG.getNOT(dl, Shift, VT); in LowerSELECT_CC() 14989 return DAG.getNOT(dl, Fcmeq, VT); in EmitVectorComparison() 15033 return DAG.getNOT(dl, Cmeq, VT); in EmitVectorComparison() 15155 Cmp = DAG.getNOT(dl, Cmp, Cmp.getValueType()); in LowerVSETCC() 19404 return DAG.getNOT( in performConcatVectorsCombine() 25017 SDValue InvMask = DAG.getNOT(DL, Mask, VT); in performBSPExpandForSVE()
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| /src/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 11337 return DAG.getNOT(Dl, Rev, MVT::i1); in getDataClassTest() 11356 SDValue Normal(DAG.getNOT( in getDataClassTest() 11364 Sign = DAG.getNOT(Dl, Sign, MVT::i1); in getDataClassTest()
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| /src/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 11049 SDValue Res = DAG.getNOT(DL, OEQ, VT); in lowerVectorStrictFSetcc() 13808 SDValue And = DAG.getNOT(DL, Shl, MVT::i64); in performXORCombine()
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