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Searched refs:getLocVT (Results 1 – 25 of 35) sorted by relevance

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/src/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVCallLowering.cpp107 if ((VA.getLocVT() == MVT::i64 && VA.getValVT() == MVT::f32) || in assignValueToReg()
108 ((VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::i64) && in assignValueToReg()
110 LLT DstTy = LLT::scalar(VA.getLocVT().getSizeInBits()); in assignValueToReg()
130 assert(VALo.getLocVT() == MVT::i32 && VAHi.getLocVT() == MVT::i32 && in assignCustomValue()
139 LLT MemTy(VAHi.getLocVT()); in assignCustomValue()
256 assert(VALo.getLocVT() == MVT::i32 && VAHi.getLocVT() == MVT::i32 && in assignCustomValue()
264 LLT MemTy(VAHi.getLocVT()); in assignCustomValue()
/src/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp288 assert(VA.getLocVT() == MVT::v2i32); in LowerReturn_32()
301 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_32()
310 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_32()
373 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
376 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
379 OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
405 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_64()
466 assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32); in LowerFormalArguments_32()
492 WholeValue = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), WholeValue); in LowerFormalArguments_32()
499 if (VA.getLocVT() == MVT::f32) in LowerFormalArguments_32()
[all …]
/src/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLoweringCall.cpp772 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy); in LowerReturn()
774 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy); in LowerReturn()
777 ValToCopy = lowerMasksToReg(ValToCopy, VA.getLocVT(), dl, DAG); in LowerReturn()
779 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy); in LowerReturn()
782 ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy); in LowerReturn()
1110 EVT CopyVT = VA.getLocVT(); in LowerCallResult()
1145 RoundAfterCopy = (CopyVT != VA.getLocVT()); in LowerCallResult()
1169 ((VA.getLocVT() == MVT::i64) || (VA.getLocVT() == MVT::i32) || in LowerCallResult()
1170 (VA.getLocVT() == MVT::i16) || (VA.getLocVT() == MVT::i8))) { in LowerCallResult()
1172 Val = lowerRegToMasks(Val, VA.getValVT(), VA.getLocVT(), dl, DAG); in LowerCallResult()
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H A DX86FastISel.cpp3366 assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() && in fastLowerCall()
3372 bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), ArgReg, in fastLowerCall()
3375 ArgVT = VA.getLocVT(); in fastLowerCall()
3379 assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() && in fastLowerCall()
3392 bool Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), ArgReg, in fastLowerCall()
3395 ArgVT = VA.getLocVT(); in fastLowerCall()
3399 assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() && in fastLowerCall()
3401 bool Emitted = X86FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(), ArgReg, in fastLowerCall()
3404 Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), ArgReg, in fastLowerCall()
3407 Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), ArgReg, in fastLowerCall()
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/src/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp312 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
315 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
318 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
523 EVT RegVT = VA.getLocVT(); in LowerCallArguments()
540 unsigned ObjSize = VA.getLocVT().getStoreSize(); in LowerCallArguments()
549 ArgIn = DAG.getLoad(VA.getLocVT(), dl, Chain, FIN, in LowerCallArguments()
680 unsigned ObjSize = VA.getLocVT().getStoreSize(); in LowerReturn()
708 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/src/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelLowering.cpp201 EVT LocVT = VA.getLocVT(); in convertValVTToLocVT()
234 EVT LocVT = VA.getLocVT(); in unpackFromRegLoc()
265 EVT LocVT = VA.getLocVT(); in unpackFromMemLoc()
290 assert(VA.getLocVT() == MVT::i32 && in unpack64()
355 bool IsF64OnCSKY = VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64; in LowerFormalArguments()
458 bool IsF64OnCSKY = VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64; in LowerReturn()
485 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
576 bool IsF64OnCSKY = VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64; in LowerCall()
724 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), Glue); in LowerCall()
729 bool IsF64OnCSKY = VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64; in LowerCall()
/src/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp351 EVT RegVT = VA.getLocVT(); in LowerFormalArguments()
390 InVals.push_back(DAG.getConstant(0, DL, VA.getLocVT())); in LowerFormalArguments()
465 Arg = DAG.getNode(ISD::SIGN_EXTEND, CLI.DL, VA.getLocVT(), Arg); in LowerCall()
468 Arg = DAG.getNode(ISD::ZERO_EXTEND, CLI.DL, VA.getLocVT(), Arg); in LowerCall()
471 Arg = DAG.getNode(ISD::ANY_EXTEND, CLI.DL, VA.getLocVT(), Arg); in LowerCall()
571 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/src/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsCallLowering.cpp173 assert(VALo.getLocVT() == MVT::i32 && VAHi.getLocVT() == MVT::i32 && in assignCustomValue()
265 assert(VALo.getLocVT() == MVT::i32 && VAHi.getLocVT() == MVT::i32 && in assignCustomValue()
H A DMipsISelLowering.cpp3294 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); in LowerCall()
3369 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); in LowerCall()
3371 ISD::SHL, DL, VA.getLocVT(), Arg, in LowerCall()
3372 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); in LowerCall()
3540 RVLocs[i].getLocVT(), InGlue); in LowerCallResult()
3546 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); in LowerCallResult()
3550 Shift, DL, VA.getLocVT(), Val, in LowerCallResult()
3551 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); in LowerCallResult()
3568 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val, in LowerCallResult()
3574 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val, in LowerCallResult()
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/src/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.cpp397 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn()
400 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn()
403 OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn()
411 assert(VA.getLocVT() == MVT::i64); in LowerReturn()
429 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
470 MF.addLiveIn(VA.getLocReg(), getRegClassFor(VA.getLocVT())); in LowerFormalArguments()
471 SDValue Arg = DAG.getCopyFromReg(Chain, DL, VReg, VA.getLocVT()); in LowerFormalArguments()
477 Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg, in LowerFormalArguments()
481 Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg, in LowerFormalArguments()
490 assert(VA.getLocVT() == MVT::i64); in LowerFormalArguments()
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/src/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp457 EVT RegVT = VA.getLocVT(); in LowerCCCArguments()
489 unsigned ObjSize = VA.getLocVT().getSizeInBits() / 8; in LowerCCCArguments()
493 << VA.getLocVT() << "\n"; in LowerCCCArguments()
502 VA.getLocVT(), DL, Chain, FIN, in LowerCCCArguments()
567 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
673 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg); in LowerCCCCallTo()
676 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg); in LowerCCCCallTo()
679 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg); in LowerCCCCallTo()
/src/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp643 EVT RegVT = VA.getLocVT(); in LowerCCCArguments()
681 MVT PtrVT = VA.getLocVT(); in LowerCCCArguments()
687 unsigned ObjSize = VA.getLocVT().getSizeInBits()/8; in LowerCCCArguments()
690 << VA.getLocVT() << "\n"; in LowerCCCArguments()
699 VA.getLocVT(), dl, Chain, FIN, in LowerCCCArguments()
771 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
838 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
841 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
844 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
/src/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1058 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
1061 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
1064 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
1208 EVT RegVT = VA.getLocVT(); in LowerCCCArguments()
1228 unsigned ObjSize = VA.getLocVT().getSizeInBits()/8; in LowerCCCArguments()
1231 << VA.getLocVT() << "\n"; in LowerCCCArguments()
1241 ArgIn = DAG.getLoad(VA.getLocVT(), dl, Chain, FIN, in LowerCCCArguments()
1381 unsigned ObjSize = VA.getLocVT().getSizeInBits() / 8; in LowerReturn()
1409 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/src/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMCallLowering.cpp125 assert(VA.getLocVT().getSizeInBits() <= 64 && "Unsupported location size"); in assignValueToReg()
298 uint64_t LocSize = VA.getLocVT().getFixedSizeInBits(); in assignValueToReg()
H A DARMCallingConv.cpp178 assert(PendingMembers[0].getLocVT() == LocVT); in CC_ARM_AAPCS_Custom_Aggregate()
H A DARMFastISel.cpp1903 if (VA.getLocVT() != MVT::f64 || in ProcessCallArgs()
1953 MVT DestVT = VA.getLocVT(); in ProcessCallArgs()
1962 MVT DestVT = VA.getLocVT(); in ProcessCallArgs()
1969 unsigned BC = fastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, Arg); in ProcessCallArgs()
1972 ArgVT = VA.getLocVT(); in ProcessCallArgs()
1985 assert(VA.getLocVT() == MVT::f64 && in ProcessCallArgs()
H A DARMISelLowering.cpp2221 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 && in LowerCallResult()
2229 (VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2f64)) { in LowerCallResult()
2244 if (VA.getLocVT() == MVT::v2f64) { in LowerCallResult()
2264 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(), in LowerCallResult()
2283 Val = MoveToHPR(dl, DAG, VA.getLocVT(), VA.getValVT(), Val); in LowerCallResult()
2291 VA.getLocVT().isScalarInteger() && Arg.ArgVT.bitsLT(MVT::i32)) in LowerCallResult()
2311 int Size = VA.getLocVT().getFixedSizeInBits() / 8; in computeAddrForCallArg()
2515 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
2518 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
2521 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
[all …]
/src/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp369 if (VA.getLocVT().getSizeInBits() > Arg.getValueType().getSizeInBits()) { in MatchingStackOffset()
443 ValVT = VA.getLocVT(); in LowerMemArgument()
646 EVT RegVT = VA.getLocVT(); in LowerCall()
735 uint32_t OpSize = (VA.getLocVT().getSizeInBits() + 7) / 8; in LowerCall()
897 EVT CopyVT = VA.getLocVT(); in LowerCallResult()
947 EVT RegVT = VA.getLocVT(); in LowerFormalArguments()
1100 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), ValToCopy); in LowerReturn()
1102 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), ValToCopy); in LowerReturn()
1105 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), ValToCopy); in LowerReturn()
1107 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), ValToCopy); in LowerReturn()
[all …]
/src/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaISelLowering.cpp228 EVT RegVT = VA.getLocVT(); in LowerFormalArguments()
462 SDValue RetValue = DAG.getCopyFromReg(Chain, DL, Reg, VA.getLocVT(), Glue); in LowerCall()
514 RetOps.push_back(DAG.getRegister(Register, VA.getLocVT())); in LowerReturn()
/src/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp234 Val = DAG.getBitcast(VA.getLocVT(), Val); in LowerReturn()
237 Val = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Val); in LowerReturn()
240 Val = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Val); in LowerReturn()
243 Val = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Val); in LowerReturn()
251 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
483 Arg = DAG.getBitcast(VA.getLocVT(), Arg); in LowerCall()
486 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
489 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
492 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
503 LargestAlignSeen, Align(VA.getLocVT().getStoreSizeInBits() / 8)); in LowerCall()
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/src/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DCallingConvLower.h132 MVT getLocVT() const { return LocVT; } in getLocVT() function
/src/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64CallLowering.cpp79 : LLT(VA.getLocVT()); in getStackValueStoreTypeHack()
178 LLT LocTy(VA.getLocVT()); in assignValueToAddress()
320 MVT LocVT = VA.getLocVT(); in assignValueToAddress()
/src/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp782 const MVT LocVT = VA.getLocVT(); in handleAssignments()
1295 LLT LocTy{VA.getLocVT()}; in extendRegister()
1386 const MVT LocVT = VA.getLocVT(); in assignValueToReg()
/src/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallLowering.cpp36 if (VA.getLocVT().getSizeInBits() < 32) { in extendRegisterMin32()
124 if (VA.getLocVT().getSizeInBits() < 32) { in assignValueToReg()
132 buildExtensionHint(VA, Copy.getReg(0), LLT(VA.getLocVT())); in assignValueToReg()
/src/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp1482 Value = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Value, in convertLocVTToValVT()
1485 Value = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Value, in convertLocVTToValVT()
1493 assert(VA.getLocVT() == MVT::i64); in convertLocVTToValVT()
1509 return DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Value); in convertValVTToLocVT()
1511 return DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Value); in convertValVTToLocVT()
1513 return DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Value); in convertValVTToLocVT()
1515 assert(VA.getLocVT() == MVT::i64 || VA.getLocVT() == MVT::i128); in convertValVTToLocVT()
1520 if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i64) in convertValVTToLocVT()
1522 MVT BitCastToType = VA.getValVT().isVector() && VA.getLocVT() == MVT::i64 in convertValVTToLocVT()
1524 : VA.getLocVT(); in convertValVTToLocVT()
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