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Searched refs:getLocReg (Results 1 – 25 of 34) sorted by relevance

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/src/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMCallLowering.cpp122 assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?"); in assignValueToReg()
173 assignValueToReg(NewRegs[0], VA.getLocReg(), VA); in assignCustomValue()
174 assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA); in assignCustomValue()
178 assignValueToReg(NewRegs[0], VA.getLocReg(), VA); in assignCustomValue()
179 assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA); in assignCustomValue()
295 assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?"); in assignValueToReg()
342 assignValueToReg(NewRegs[0], VA.getLocReg(), VA); in assignCustomValue()
343 assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA); in assignCustomValue()
H A DARMFastISel.cpp1981 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(Arg); in ProcessCallArgs()
1982 RegArgs.push_back(VA.getLocReg()); in ProcessCallArgs()
1995 TII.get(ARM::VMOVRRD), VA.getLocReg()) in ProcessCallArgs()
1996 .addReg(NextVA.getLocReg(), RegState::Define) in ProcessCallArgs()
1998 RegArgs.push_back(VA.getLocReg()); in ProcessCallArgs()
1999 RegArgs.push_back(NextVA.getLocReg()); in ProcessCallArgs()
2045 .addReg(RVLocs[0].getLocReg()) in FinishCall()
2046 .addReg(RVLocs[1].getLocReg())); in FinishCall()
2048 UsedRegs.push_back(RVLocs[0].getLocReg()); in FinishCall()
2049 UsedRegs.push_back(RVLocs[1].getLocReg()); in FinishCall()
[all …]
/src/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLoweringCall.cpp730 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo)); in Passv64i1ArgInRegs()
731 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Hi)); in Passv64i1ArgInRegs()
765 MF.getRegInfo().disableCalleeSavedRegister(VA.getLocReg()); in LowerReturn()
789 if (!Subtarget.hasSSE1() && X86::FR32XRegClass.contains(VA.getLocReg())) { in LowerReturn()
793 X86::FR64XRegClass.contains(VA.getLocReg()) && in LowerReturn()
803 if (VA.getLocReg() == X86::FP0 || in LowerReturn()
804 VA.getLocReg() == X86::FP1) { in LowerReturn()
809 RetVals.push_back(std::make_pair(VA.getLocReg(), ValToCopy)); in LowerReturn()
818 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { in LowerReturn()
839 MF.getRegInfo().disableCalleeSavedRegister(RVLocs[I].getLocReg()); in LowerReturn()
[all …]
H A DX86FastISel.cpp1241 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) in X86SelectRet()
1270 Register DstReg = VA.getLocReg(); in X86SelectRet()
1279 RetRegs.push_back(VA.getLocReg()); in X86SelectRet()
3438 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg); in fastLowerCall()
3439 OutRegs.push_back(VA.getLocReg()); in fastLowerCall()
3593 Register SrcReg = VA.getLocReg(); in fastLowerCall()
3612 InRegs.push_back(VA.getLocReg()); in fastLowerCall()
/src/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsCallLowering.cpp177 auto CopyLo = MIRBuilder.buildCopy(LLT::scalar(32), VALo.getLocReg()); in assignCustomValue()
178 auto CopyHi = MIRBuilder.buildCopy(LLT::scalar(32), VAHi.getLocReg()); in assignCustomValue()
186 markPhysRegUsed(VALo.getLocReg()); in assignCustomValue()
187 markPhysRegUsed(VAHi.getLocReg()); in assignCustomValue()
283 MIRBuilder.buildCopy(VALo.getLocReg(), Lo); in assignCustomValue()
284 MIRBuilder.buildCopy(VAHi.getLocReg(), Hi); in assignCustomValue()
288 MIRBuilder.buildCopy(VALo.getLocReg(), Lo); in assignCustomValue()
289 MIRBuilder.buildCopy(VAHi.getLocReg(), Hi); in assignCustomValue()
H A DMipsFastISel.cpp1225 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg); in processCallArgs()
1226 CLI.OutRegs.push_back(VA.getLocReg()); in processCallArgs()
1296 ResultReg).addReg(RVLocs[0].getLocReg()); in finishCall()
1297 CLI.InRegs.push_back(RVLocs[0].getLocReg()); in finishCall()
1722 Register DestReg = VA.getLocReg(); in selectRet()
1763 RetRegs.push_back(VA.getLocReg()); in selectRet()
H A DMipsISelLowering.cpp3336 Register LocRegLo = VA.getLocReg(); in LowerCall()
3337 Register LocRegHigh = ArgLocs[++i].getLocReg(); in LowerCall()
3378 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
3382 if (Mips::AFGR64RegClass.contains(VA.getLocReg())) in LowerCall()
3388 CSInfo.ArgRegPairs.emplace_back(VA.getLocReg(), i); in LowerCall()
3539 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(), in LowerCallResult()
3706 Register ArgReg = VA.getLocReg(); in LowerFormalArguments()
3728 addLiveIn(DAG.getMachineFunction(), NextVA.getLocReg(), RC); in LowerFormalArguments()
3896 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Glue); in LowerReturn()
3900 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/src/contrib/llvm-project/llvm/lib/CodeGen/
H A DCallingConvLower.cpp77 if (ValAssign.isRegLoc() && TRI.regsOverlap(ValAssign.getLocReg(), Reg)) in IsShadowAllocatedReg()
230 Regs.push_back(MCPhysReg(Locs[I].getLocReg())); in getRemainingRegParmsForType()
284 return Loc1.getLocReg() == Loc2.getLocReg(); in resultsCompatible()
/src/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelLowering.cpp255 RegInfo.addLiveIn(VA.getLocReg(), VReg); in unpackFromRegLoc()
308 RegInfo.addLiveIn(VA.getLocReg(), LoVReg); in unpack64()
311 if (VA.getLocReg() == CSKY::R3) { in unpack64()
320 RegInfo.addLiveIn(VA.getLocReg() + 1, HiVReg); in unpack64()
468 Register RegLo = VA.getLocReg(); in LowerReturn()
481 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Glue); in LowerReturn()
485 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
585 Register RegLo = VA.getLocReg(); in LowerCall()
613 RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue)); in LowerCall()
724 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), Glue); in LowerCall()
[all …]
/src/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp299 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part0, Glue); in LowerReturn_32()
301 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_32()
303 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part1, in LowerReturn_32()
306 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Glue); in LowerReturn_32()
310 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_32()
393 if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) { in LowerReturn_64()
401 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Glue); in LowerReturn_64()
405 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_64()
469 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi); in LowerFormalArguments_32()
482 Register loReg = MF.addLiveIn(NextVA.getLocReg(), in LowerFormalArguments_32()
[all …]
/src/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVCallLowering.cpp150 assignValueToReg(NewRegs[0], VALo.getLocReg(), VALo); in assignCustomValue()
152 assignValueToReg(NewRegs[1], VAHi.getLocReg(), VAHi); in assignCustomValue()
274 assignValueToReg(NewRegs[0], VALo.getLocReg(), VALo); in assignCustomValue()
276 assignValueToReg(NewRegs[1], VAHi.getLocReg(), VAHi); in assignCustomValue()
/src/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp325 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
419 DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getValVT(), Glue); in lowerCallResult()
532 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCallArguments()
703 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Glue); in LowerReturn()
708 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/src/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp366 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
477 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
566 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Glue); in LowerReturn()
571 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
604 Chain = DAG.getCopyFromReg(Chain, DL, Val.getLocReg(), in LowerCallResult()
/src/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaISelLowering.cpp238 unsigned Register = MF.addLiveIn(VA.getLocReg(), RC); in LowerFormalArguments()
342 RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue)); in LowerCall()
461 unsigned Reg = VA.getLocReg(); in LowerCall()
511 unsigned Register = VA.getLocReg(); in LowerReturn()
/src/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp942 Handler.assignValueToReg(ArgReg, VA.getLocReg(), VA); in handleAssignments()
945 Handler.assignValueToReg(ArgReg, VA.getLocReg(), VA); in handleAssignments()
1150 MCRegister PhysReg = ArgLoc.getLocReg(); in parametersInCSRMatch()
1231 if (Loc1.getLocReg() != Loc2.getLocReg()) in resultsCompatible()
/src/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp461 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCCCArguments()
563 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Glue); in LowerReturn()
567 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
692 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCCCCallTo()
789 Chain = DAG.getCopyFromReg(Chain, DL, RVLocs[I].getLocReg(), in LowerCallResult()
/src/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp655 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCCCArguments()
765 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), in LowerReturn()
771 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
851 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCCCCallTo()
949 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), in LowerCallResult()
/src/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp978 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getValVT(), in LowerCallResult()
1071 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCCCCallTo()
1220 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCCCArguments()
1404 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Glue); in LowerReturn()
1409 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/src/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DCallingConvLower.h128 Register getLocReg() const { return std::get<Register>(Data); } in getLocReg() function
/src/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp1403 Register Reg = MF.addLiveIn(VA.getLocReg(), RC); in LowerFormalArguments()
1558 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
1664 Chain = DAG.getCopyFromReg(Chain, dl, RVLoc.getLocReg(), RVLoc.getValVT(), in LowerCallResult()
1720 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Glue); in LowerReturn()
1724 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/src/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp681 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
900 Chain = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), CopyVT, InGlue) in LowerCallResult()
954 Register Reg = MF.addLiveIn(VA.getLocReg(), RC); in LowerFormalArguments()
1111 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), ValToCopy, Glue); in LowerReturn()
1113 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
1338 Register Reg = VA.getLocReg(); in IsEligibleForTailCallOptimization()
/src/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp247 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Val, Glue); in LowerReturn()
251 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
375 SDValue FR0 = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), in LowerCallResult()
389 RetVal = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), in LowerCallResult()
521 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
882 MRI.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
883 HFL.FirstVarArgSavedReg = NextSingleReg(*RC, VA.getLocReg()); in LowerFormalArguments()
/src/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.cpp425 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Glue); in LowerReturn()
429 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
470 MF.addLiveIn(VA.getLocReg(), getRegClassFor(VA.getLocVT())); in LowerFormalArguments()
722 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
802 Register Reg = VA.getLocReg(); in LowerCall()
/src/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp4337 Register RegLo = MF.addLiveIn(VA.getLocReg(), RC); in LowerFormalArguments_32SVR4()
4338 Register RegHi = MF.addLiveIn(ArgLocs[++i].getLocReg(), RC); in LowerFormalArguments_32SVR4()
4346 Register Reg = MF.addLiveIn(VA.getLocReg(), RC); in LowerFormalArguments_32SVR4()
5366 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, in LowerCallResult()
5371 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, in LowerCallResult()
5380 VA.getLocReg(), VA.getLocVT(), InGlue); in LowerCallResult()
6148 RegsToPass.push_back(std::make_pair(VA.getLocReg(), SVal.getValue(0))); in LowerCall_32SVR4()
6151 RegsToPass.push_back(std::make_pair(ArgLocs[++i].getLocReg(), in LowerCall_32SVR4()
6154 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall_32SVR4()
7276 MF.addLiveIn(VA.getLocReg(), in LowerFormalArguments_AIX()
[all …]
H A DPPCFastISel.cpp1514 unsigned SourcePhysReg = VA.getLocReg(); in finishCall()
1721 Register RetReg = VA.getLocReg(); in SelectRet()
1745 RetRegs.push_back(VA.getLocReg()); in SelectRet()

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