| /src/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600InstrInfo.h | 207 unsigned int getInstrLatency(const InstrItineraryData *ItinData,
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| H A D | AMDGPUSubtarget.cpp | 885 Lat = InstrInfo.getInstrLatency(getInstrItineraryData(), *I); in adjustSchedDependency()
895 unsigned Lat = InstrInfo.getInstrLatency(getInstrItineraryData(), *DefI); in adjustSchedDependency()
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| H A D | SIInstrInfo.h | 1423 unsigned getInstrLatency(const InstrItineraryData *ItinData,
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| H A D | R600InstrInfo.cpp | 981 unsigned int R600InstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() function in R600InstrInfo
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| H A D | SIInstrInfo.cpp | 9534 unsigned SIInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() function in SIInstrInfo
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| /src/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetSchedule.cpp | 263 return TII->getInstrLatency(&InstrItins, *MI); in computeInstrLatency()
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| H A D | TwoAddressInstructionPass.cpp | 954 if (TII->getInstrLatency(InstrItins, *MI) > 1) in rescheduleMIBelowKill()
1086 if (TII->getInstrLatency(InstrItins, DefMI) > (Dist - DefDist)) in isDefTooClose()
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| H A D | TargetInstrInfo.cpp | 1458 unsigned TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() function in TargetInstrInfo
1504 unsigned TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() function in TargetInstrInfo
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| /src/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.h | 462 unsigned getInstrLatency(const InstrItineraryData *ItinData,
466 unsigned getInstrLatency(const InstrItineraryData *ItinData,
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| H A D | ARMBaseInstrInfo.cpp | 4413 unsigned Latency = getInstrLatency(ItinData, DefMI); in getOperandLatencyImpl()
4735 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() function in ARMBaseInstrInfo
4750 Latency += getInstrLatency(ItinData, *I, PredCost); in getInstrLatency()
4786 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() function in ARMBaseInstrInfo
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| /src/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.h | 280 unsigned getInstrLatency(const InstrItineraryData *ItinData,
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| H A D | HexagonInstrInfo.cpp | 1970 unsigned HexagonInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() function in HexagonInstrInfo
4312 return getInstrLatency(ItinData, MI); in getInstrTimingClassLatency()
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| /src/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetInstrInfo.h | 1789 virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
1795 virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
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| /src/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.h | 333 unsigned getInstrLatency(const InstrItineraryData *ItinData,
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| H A D | PPCInstrInfo.cpp | 138 unsigned PPCInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() function in PPCInstrInfo
142 return PPCGenInstrInfo::getInstrLatency(ItinData, MI, PredCost); in getInstrLatency()
193 Latency = getInstrLatency(ItinData, DefMI); in getOperandLatency()
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| /src/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ScheduleDAGSDNodes.cpp | 647 SU->Latency += TII->getInstrLatency(InstrItins, N); in computeLatency()
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