| /src/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstr.h | 1509 return findRegisterDefOperandIdx(Reg, TRI, false, false) != -1;
1516 return findRegisterDefOperandIdx(Reg, TRI, false, true) != -1;
1523 return findRegisterDefOperandIdx(Reg, TRI, true, false) != -1;
1558 int findRegisterDefOperandIdx(Register Reg, const TargetRegisterInfo *TRI,
1568 int Idx = findRegisterDefOperandIdx(Reg, TRI, isDead, Overlap);
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| /src/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineCombiner.cpp | 233 DefInstr->findRegisterDefOperandIdx(MO.getReg(), /*TRI=*/nullptr); in getDepth()
247 DefInstr->findRegisterDefOperandIdx(MO.getReg(), in getDepth()
290 NewRoot->findRegisterDefOperandIdx(MO.getReg(), /*TRI=*/nullptr), in getLatency()
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| H A D | EarlyIfConversion.cpp | 602 int TIdx = TDef->findRegisterDefOperandIdx(TReg, /*TRI=*/nullptr); in hasSameValue()
603 int FIdx = FDef->findRegisterDefOperandIdx(FReg, /*TRI=*/nullptr); in hasSameValue()
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| H A D | AggressiveAntiDepBreaker.cpp | 682 int Idx = UseMI->findRegisterDefOperandIdx(NewReg, TRI, false, true); in FindSuitableFreeRegisters()
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| H A D | ModuloSchedule.cpp | 1683 assert(Def->findRegisterDefOperandIdx(MI.getOperand(1).getReg(), in moveStageBetweenBlocks()
1910 unsigned OpIdx = MI->findRegisterDefOperandIdx(Reg, /*TRI=*/nullptr); in getEquivalentRegisterIn()
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| H A D | TwoAddressInstructionPass.cpp | 1430 NewMIs[1]->findRegisterDefOperandIdx(regA, /*TRI=*/nullptr); in tryInstructionTransform()
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| H A D | MachineInstr.cpp | 1103 int MachineInstr::findRegisterDefOperandIdx(Register Reg, in findRegisterDefOperandIdx() function in MachineInstr
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| H A D | RegisterCoalescer.cpp | 852 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg(), /*TRI=*/nullptr); in removeCopyByCommutingDef()
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| /src/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostSelectOptimize.cpp | 272 II.findRegisterDefOperandIdx(AArch64::NZCV, /*TRI=*/nullptr); in optimizeNZCVDefs()
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| /src/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVOptWInstrs.cpp | 423 int OpNo = MI->findRegisterDefOperandIdx(Reg, /*TRI=*/nullptr); in isSignExtendedW()
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| /src/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchOptWInstrs.cpp | 504 int OpNo = MI->findRegisterDefOperandIdx(Reg, /*TRI=*/nullptr); in isSignExtendedW()
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| /src/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 648 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, /*TRI=*/nullptr, in canFoldIntoCSel()
677 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, /*TRI=*/nullptr, in canFoldIntoCSel()
1543 CmpInstr.findRegisterDefOperandIdx(AArch64::NZCV, /*TRI=*/nullptr, true); in optimizeCompareInstr()
1870 if (MI.findRegisterDefOperandIdx(AArch64::NZCV, /*TRI=*/nullptr, true) != -1) in canCmpInstrBeRemoved()
5948 MI->findRegisterDefOperandIdx(AArch64::NZCV, /*TRI=*/nullptr, true) == -1) in canCombine()
6087 Root.findRegisterDefOperandIdx(AArch64::NZCV, /*TRI=*/nullptr, true); in getMaddPatterns()
6582 Root.findRegisterDefOperandIdx(AArch64::NZCV, /*TRI=*/nullptr, true) == in getMiscPatterns()
8075 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, /*TRI=*/nullptr, in optimizeCondBranch()
9297 MI.findRegisterDefOperandIdx(MI.getOperand(0).getReg() - AArch64::W0 + in isCopyInstrImpl()
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| /src/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | LegalizationArtifactCombiner.h | 924 Unmerge->findRegisterDefOperandIdx(Def, /*TRI=*/nullptr); in findUnmergeThatDefinesReg()
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| /src/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600InstrInfo.cpp | 214 return MI.findRegisterDefOperandIdx(R600::AR_X, &RI, false, false) != -1; in definesAddressRegister()
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| H A D | SIInstrInfo.cpp | 7314 int SCCIdx = Inst.findRegisterDefOperandIdx(AMDGPU::SCC, /*TRI=*/nullptr); in moveToVALUImpl()
7580 if (CandI.findRegisterDefOperandIdx(AMDGPU::SCC, &RI, false, false) != in lowerSelect()
8412 if (MI.findRegisterDefOperandIdx(AMDGPU::SCC, &RI, false, false) != -1) in addSCCDefUsersToVALUWorklist()
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| /src/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMLowOverheadLoops.cpp | 94 return MI->findRegisterDefOperandIdx(ARM::VPR, /*TRI=*/nullptr) != -1; in isVectorPredicate()
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| H A D | ARMBaseInstrInfo.cpp | 1736 int ImpDefIdx = MI.findRegisterDefOperandIdx(DstRegD, /*TRI=*/nullptr); in expandPostRAPseudo()
4141 Idx = II->findRegisterDefOperandIdx(Reg, TRI, false, true); in getBundledDefMI()
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| /src/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 2870 return I1->findRegisterDefOperandIdx(InstAndDef1->Reg, /*TRI=*/nullptr) == in matchEqualDefs()
2871 I2->findRegisterDefOperandIdx(InstAndDef2->Reg, /*TRI=*/nullptr); in matchEqualDefs()
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| /src/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 4338 int Idx = DefMI.findRegisterDefOperandIdx(SR, &HRI, false, false); in getOperandLatency()
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| /src/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 5828 UseMI.findRegisterDefOperandIdx(X86::EFLAGS, /*TRI=*/nullptr)); in foldImmediateImpl()
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