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Searched refs:eop (Results 1 – 25 of 47) sorted by relevance

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/src/sys/dev/cxgbe/cudbg/
H A Dcudbg_wtp.c328 wtp->sge_pcie_cmd_req.eop[0] = sge_dbg_reg->debug_PC_Req_EOP0_cnt; in t5_wtp_data()
329 wtp->sge_pcie_cmd_req.eop[1] = sge_dbg_reg->debug_PC_Req_EOP1_cnt; in t5_wtp_data()
337 wtp->pcie_core_cmd_req.eop[0] = ((value >> 0) & 0xFF); /*bit 0:7*/ in t5_wtp_data()
338 wtp->pcie_core_cmd_req.eop[1] = ((value >> 8) & 0xFF); /*bit 8:15*/ in t5_wtp_data()
344 wtp->pcie_t5_dma_stat3.eop[i] = ((value >> 16) & 0xFF); in t5_wtp_data()
350 wtp->sge_debug_data_high_index_6.eop[0] = ((value >> 0) & 0x0F); in t5_wtp_data()
352 wtp->sge_debug_data_high_index_6.eop[1] = ((value >> 8) & 0x0F); in t5_wtp_data()
354 wtp->sge_debug_data_high_index_6.eop[2] = ((value >> 16) & 0x0F); in t5_wtp_data()
356 wtp->sge_debug_data_high_index_6.eop[3] = ((value >> 24) & 0x0F); in t5_wtp_data()
361 wtp->sge_debug_data_high_index_3.eop[0] = ((value >> 0) & 0x0F); in t5_wtp_data()
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H A Dcudbg_entity.h418 u32 eop; member
423 u32 eop[2]; member
428 u32 eop[4]; member
433 u32 eop[4]; member
547 u32 eop[8]; /* => undef,*/ member
/src/sys/dev/enic/
H A Dwq_enet_desc.h41 u8 offload_mode, u8 eop, u8 cq_entry, u8 fcoe_encap, in wq_enet_desc_enc() argument
51 (eop & 1) << WQ_ENET_FLAGS_EOP_SHIFT | in wq_enet_desc_enc()
60 u8 *offload_mode, u8 *eop, u8 *cq_entry, u8 *fcoe_encap, in wq_enet_desc_dec() argument
73 *eop = (u8)((le16_to_cpu(desc->header_length_flags) >> in wq_enet_desc_dec()
H A Dcq_enet_desc.h112 u8 ingress_port, u8 fcoe, u8 eop, u8 sop, u8 rss_type, u8 csum_not_calc, in cq_enet_rq_desc_enc() argument
124 (eop ? CQ_ENET_RQ_DESC_FLAGS_EOP : 0) | in cq_enet_rq_desc_enc()
165 u8 *ingress_port, u8 *fcoe, u8 *eop, u8 *sop, u8 *rss_type, in cq_enet_rq_desc_dec() argument
188 *eop = (completed_index_flags & CQ_ENET_RQ_DESC_FLAGS_EOP) ? in cq_enet_rq_desc_dec()
H A Denic_txrx.c96 uint8_t eop = 0, cq; in enic_isc_txd_encap() local
120 eop = 0; in enic_isc_txd_encap()
124 eop = 1; in enic_isc_txd_encap()
133 header_len, offload_mode, eop, cq, 0, in enic_isc_txd_encap()
393 u8 type, color, eop, sop, ingress_port, vlan_stripped; in vnic_rq_service() local
407 &ingress_port, &fcoe, &eop, &sop, &rss_type, in vnic_rq_service()
/src/sys/dev/aq/
H A Daq_dbg.c73 __field(uint8_t, eop) in trace_aq_tx_descr()
88 entry.eop = DESCR_FIELD(descr[1], 21, 21); in trace_aq_tx_descr()
98 entry.tx_cmd, entry.eop, entry.dd, entry.buf_len, in trace_aq_tx_descr()
108 uint8_t eop; in trace_aq_rx_descr() local
142 eop = DESCR_FIELD(descr[1], 1, 1); in trace_aq_rx_descr()
151 rx_estat, rx_stat, eop, dd); in trace_aq_rx_descr()
H A Daq_ring.h53 uint16_t eop:1; member
85 uint32_t eop:1; member
H A Daq_ring.c289 if (rx_desc[i].wb.eop) { in aq_isc_rxd_available()
370 if (!rx_desc->wb.eop) { in aq_isc_rxd_pkt_get()
387 } while (!rx_desc->wb.eop); in aq_isc_rxd_pkt_get()
548 txd->eop = 1U; in aq_isc_txd_encap()
/src/sys/dev/qcom_ess_edma/
H A Dqcom_ess_edma_tx.c234 uint32_t eop; in qcom_ess_edma_tx_ring_frame() local
368 eop = 0; in qcom_ess_edma_tx_ring_frame()
390 eop = EDMA_TPD_EOP; in qcom_ess_edma_tx_ring_frame()
407 ds->word1 = word1 | eop; in qcom_ess_edma_tx_ring_frame()
418 eop); in qcom_ess_edma_tx_ring_frame()
/src/stand/kboot/libkboot/
H A Ddfk.c173 char *eop = NULL; in symbol_addr() local
175 v = strtoul(val, &eop, 16); in symbol_addr()
176 if (*eop == '\0') in symbol_addr()
/src/sys/dev/sfxge/common/
H A Def10_tx.c453 boolean_t eop = ebp->eb_eop; in ef10_tx_qpost() local
467 size_t, size, boolean_t, eop); in ef10_tx_qpost()
471 ESF_DZ_TX_KER_CONT, (eop) ? 0 : 1, in ef10_tx_qpost()
594 __in boolean_t eop, in ef10_tx_qdesc_dma_create() argument
604 size_t, size, boolean_t, eop); in ef10_tx_qdesc_dma_create()
608 ESF_DZ_TX_KER_CONT, (eop) ? 0 : 1, in ef10_tx_qdesc_dma_create()
H A Defx_tx.c114 __in boolean_t eop,
611 __in boolean_t eop, in efx_tx_qdesc_dma_create() argument
620 etxop->etxo_qdesc_dma_create(etp, addr, size, eop, edp); in efx_tx_qdesc_dma_create()
1057 __in boolean_t eop, in siena_tx_qdesc_dma_create() argument
1069 size_t, size, boolean_t, eop); in siena_tx_qdesc_dma_create()
1072 FSF_AZ_TX_KER_CONT, eop ? 0 : 1, in siena_tx_qdesc_dma_create()
/src/crypto/openssl/ssl/quic/
H A Dquic_record_rx.c1017 const unsigned char *eop = NULL; in qrx_process_pkt() local
1056 eop = PACKET_data(pkt); in qrx_process_pkt()
1196 eop - sop - rxe->hdr.len, qrx->msg_callback_ssl, in qrx_process_pkt()
1213 eop = NULL; in qrx_process_pkt()
1304 assert(eop != NULL && eop >= PACKET_data(pkt)); in qrx_process_pkt()
1309 ignore_res(PACKET_forward(pkt, eop - PACKET_data(pkt))); in qrx_process_pkt()
1313 if (eop != NULL) { in qrx_process_pkt()
1322 assert(eop >= PACKET_data(pkt)); in qrx_process_pkt()
1325 ignore_res(PACKET_forward(pkt, eop - PACKET_data(pkt))); in qrx_process_pkt()
/src/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DEvergreenInstructions.td60 i32imm:$rat_id, InstFlag:$eop), (outs),
62 #!if(has_eop, ", $eop", ""),
72 let eop = 0;
77 let Constraints = "$rw_gpr = $out_gpr", eop = 0, mayStore = 1 in {
145 (ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
146 "STORE_RAW $rw_gpr, $index_gpr, $eop",
152 (ins R600_Reg64:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
153 "STORE_RAW $rw_gpr.XY, $index_gpr, $eop",
159 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
160 "STORE_RAW $rw_gpr.XYZW, $index_gpr, $eop",
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/src/sys/dev/ixgbe/
H A Dix_txrx.c408 bool eop; in ixgbe_isc_rxd_pkt_get() local
428 eop = ((staterr & IXGBE_RXD_STAT_EOP) != 0); in ixgbe_isc_rxd_pkt_get()
431 if (eop && (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) != 0) { in ixgbe_isc_rxd_pkt_get()
447 } while (!eop); in ixgbe_isc_rxd_pkt_get()
/src/sys/dev/e1000/
H A Dem_txrx.c666 bool eop; in lem_isc_rxd_pkt_get() local
684 eop = (status & E1000_RXD_STAT_EOP) != 0; in lem_isc_rxd_pkt_get()
702 } while (!eop); in lem_isc_rxd_pkt_get()
732 bool eop; in em_isc_rxd_pkt_get() local
750 eop = (staterr & E1000_RXD_STAT_EOP) != 0; in em_isc_rxd_pkt_get()
767 } while (!eop); in em_isc_rxd_pkt_get()
H A Digb_txrx.c444 bool eop; in igb_isc_rxd_pkt_get() local
464 eop = ((staterr & E1000_RXD_STAT_EOP) == E1000_RXD_STAT_EOP); in igb_isc_rxd_pkt_get()
467 if (eop && in igb_isc_rxd_pkt_get()
488 } while (!eop); in igb_isc_rxd_pkt_get()
/src/sys/dev/igc/
H A Digc_txrx.c472 bool eop; in igc_isc_rxd_pkt_get() local
492 eop = ((staterr & IGC_RXD_STAT_EOP) == IGC_RXD_STAT_EOP); in igc_isc_rxd_pkt_get()
495 if (eop && ((staterr & IGC_RXDEXT_STATERR_RXE) != 0)) { in igc_isc_rxd_pkt_get()
515 } while (!eop); in igc_isc_rxd_pkt_get()
/src/sys/dev/iavf/
H A Diavf_txrx_iflib.c675 bool eop; in iavf_isc_rxd_pkt_get() local
702 eop = (status & (1 << IAVF_RX_DESC_STATUS_EOF_SHIFT)); in iavf_isc_rxd_pkt_get()
709 if (eop && (error & (1 << IAVF_RX_DESC_ERROR_RXE_SHIFT))) { in iavf_isc_rxd_pkt_get()
719 } while (!eop); in iavf_isc_rxd_pkt_get()
/src/sys/dev/qat/qat_api/firmware/include/
H A Dicp_qat_fw_comp.h398 sop, eop, bfinal, cnv, cnvnr, cnvdfx, crc) \ argument
400 ((eop & ICP_QAT_FW_COMP_EOP_MASK) << ICP_QAT_FW_COMP_EOP_BITPOS) | \
/src/sys/dev/vmware/vmxnet3/
H A Dif_vmxreg.h101 uint32_t eop:1; /* End of packet */ member
144 uint32_t eop:1; /* End of packet */ member
/src/sys/sys/
H A Dqmath.h502 #define Q_QADDSUBQ(a, b, eop) \ argument
506 else if ((eop) == '+') { \
563 #define Q_QADDSUBI(q, i, eop) \ argument
568 else if ((eop) == '+') { \
/src/sys/dev/sfxge/
H A Dsfxge_rx.h187 extern void sfxge_rx_qcomplete(struct sfxge_rxq *rxq, boolean_t eop);
/src/sys/dev/ice/
H A Dice_iflib_txrx.c396 bool eop; in _ice_ift_rxd_pkt_get() local
417 eop = (status0 & BIT(ICE_RX_FLEX_DESC_STATUS0_EOF_S)); in _ice_ift_rxd_pkt_get()
425 } while (!eop); in _ice_ift_rxd_pkt_get()
/src/contrib/file/src/
H A Dfuncs.c573 char *eop; in file_getbuffer() local
578 eop = op + len; in file_getbuffer()
580 while (op < eop) { in file_getbuffer()
582 CAST(size_t, eop - op), &state); in file_getbuffer()

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