Home
last modified time | relevance | path

Searched refs:ena (Results 1 – 25 of 49) sorted by relevance

12

/src/sys/contrib/openzfs/module/zfs/
H A Dfm.c762 uint64_t ena, const nvlist_t *detector, ...) in fm_ereport_set() argument
781 if (nvlist_add_uint64(ereport, FM_EREPORT_ENA, ena)) { in fm_ereport_set()
1177 fm_ena_increment(uint64_t ena) in fm_ena_increment() argument
1181 switch (ENA_FORMAT(ena)) { in fm_ena_increment()
1183 new_ena = ena + (1 << ENA_FMT1_GEN_SHFT); in fm_ena_increment()
1186 new_ena = ena + (1 << ENA_FMT2_GEN_SHFT); in fm_ena_increment()
1198 uint64_t ena = 0; in fm_ena_generate_cpu() local
1203 ena = (uint64_t)((format & ENA_FORMAT_MASK) | in fm_ena_generate_cpu()
1209 ena = (uint64_t)((format & ENA_FORMAT_MASK) | in fm_ena_generate_cpu()
1217 ena = (uint64_t)((format & ENA_FORMAT_MASK) | in fm_ena_generate_cpu()
[all …]
H A Dzfs_fm.c480 uint64_t ena; in zfs_ereport_start() local
504 ena = spa->spa_ena; in zfs_ereport_start()
509 ena = zio->io_logical->io_ena; in zfs_ereport_start()
511 ena = fm_ena_generate(0, FM_ENA_FMT1); in zfs_ereport_start()
523 fm_ereport_set(ereport, FM_EREPORT_VERSION, class, ena, detector, NULL); in zfs_ereport_start()
/src/sys/arm/arm/
H A Dpl310.c127 const char *ena = "enabled"; in pl310_print_config() local
133 (aux & AUX_CTRL_EARLY_BRESP) ? ena : dis); in pl310_print_config()
135 (aux & AUX_CTRL_INSTR_PREFETCH) ? ena : dis); in pl310_print_config()
137 (aux & AUX_CTRL_DATA_PREFETCH) ? ena : dis); in pl310_print_config()
139 (aux & AUX_CTRL_NS_INT_CTRL) ? ena : dis); in pl310_print_config()
141 (aux & AUX_CTRL_NS_LOCKDOWN) ? ena : dis); in pl310_print_config()
143 (aux & AUX_CTRL_SHARE_OVERRIDE) ? ena : dis); in pl310_print_config()
146 (prefetch & PREFETCH_CTRL_DL) ? ena : dis); in pl310_print_config()
148 (prefetch & PREFETCH_CTRL_INSTR_PREFETCH) ? ena : dis); in pl310_print_config()
150 (prefetch & PREFETCH_CTRL_DATA_PREFETCH) ? ena : dis); in pl310_print_config()
[all …]
/src/sys/modules/ena/
H A DMakefile32 .PATH: ${SRCTOP}/sys/dev/ena \
33 ${SRCTOP}/sys/contrib/ena-com
37 SRCS += ena.c ena_sysctl.c ena_datapath.c ena_netmap.c ena_rss.c
/src/sys/dev/vnic/
H A Dq_struct.h610 uint64_t ena:1; member
614 uint64_t ena:1;
622 uint64_t ena:1; member
638 uint64_t ena:1;
646 uint64_t ena:1; member
662 uint64_t ena:1;
670 uint64_t ena:1; member
688 uint64_t ena: 1;
696 uint64_t ena:1; member
716 uint64_t ena:1;
/src/tools/kerneldoc/subsys/
H A DDoxyfile-dev_ena6 PROJECT_NAME = "FreeBSD kernel ena device code"
12 INPUT = $(DOXYGEN_SRC_PATH)/dev/ena/ \
/src/sys/dev/mwl/
H A Dmwlhal.h483 int mwl_hal_setpowersave_sta(struct mwl_hal_vap *, uint16_t aid, int ena);
662 int mwl_hal_setpromisc(struct mwl_hal *, int ena);
668 int mwl_hal_setcfend(struct mwl_hal *, int ena);
673 int mwl_hal_setdwds(struct mwl_hal *, int ena);
H A Dmwlhal.c1317 mwl_hal_setpowersave_sta(struct mwl_hal_vap *vap, uint16_t aid, int ena) in mwl_hal_setpowersave_sta() argument
1326 pCmd->Set = htole32(ena); in mwl_hal_setpowersave_sta()
1636 mwl_hal_setcfend(struct mwl_hal *mh0, int ena) in mwl_hal_setcfend() argument
1645 pCmd->Enable = htole32(ena); in mwl_hal_setcfend()
1653 mwl_hal_setdwds(struct mwl_hal *mh0, int ena) in mwl_hal_setdwds() argument
1661 pCmd->Enable = htole32(ena); in mwl_hal_setdwds()
2167 mwl_hal_setpromisc(struct mwl_hal *mh0, int ena) in mwl_hal_setpromisc() argument
2174 WR4(mh, MACREG_REG_PROMISCUOUS, ena ? v | 1 : v &~ 1); in mwl_hal_setpromisc()
/src/sys/contrib/device-tree/Bindings/regulator/
H A Dmax77686.txt37 - maxim,ena-gpios : one GPIO specifier enable control (the gpio
69 maxim,ena-gpios = <&gpm0 3 GPIO_ACTIVE_HIGH>;
/src/sys/contrib/openzfs/include/sys/fm/
H A Dprotocol.h152 #define ENA_FORMAT(ena) ((ena) & ENA_FORMAT_MASK) argument
/src/sys/arm64/conf/
H A Dstd.ec29 #device ena
/src/sys/net/
H A Dif_vlan.c2089 int cap = 0, ena = 0, mena, cap2 = 0, ena2 = 0; in vlan_capabilities() local
2113 ena |= mena & (IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6); in vlan_capabilities()
2114 if (ena & IFCAP_TXCSUM) in vlan_capabilities()
2117 if (ena & IFCAP_TXCSUM_IPV6) in vlan_capabilities()
2133 ena |= mena & IFCAP_TSO; in vlan_capabilities()
2134 if (ena & IFCAP_TSO) in vlan_capabilities()
2146 ena |= mena & IFCAP_LRO; in vlan_capabilities()
2161 ena |= mena & IFCAP_TOE; in vlan_capabilities()
2169 ena |= (mena & IFCAP_LINKSTATE); in vlan_capabilities()
2177 ena |= (mena & IFCAP_TXRTLMT); in vlan_capabilities()
[all …]
H A Dif_lagg.c668 int cap, cap2, ena, ena2, pena, pena2; in lagg_capabilities() local
675 ena = ena2 = ~0; in lagg_capabilities()
677 ena &= lp->lp_ifp->if_capenable; in lagg_capabilities()
681 ena = ena2 = 0; in lagg_capabilities()
688 pena = ena; in lagg_capabilities()
691 lagg_setcaps(lp, ena, ena2); in lagg_capabilities()
692 ena &= lp->lp_ifp->if_capenable; in lagg_capabilities()
695 } while (pena != ena || pena2 != ena2); in lagg_capabilities()
713 sc->sc_ifp->if_capenable != ena || in lagg_capabilities()
719 sc->sc_ifp->if_capenable = ena; in lagg_capabilities()
[all …]
/src/sys/arm/nvidia/tegra124/
H A Dtegra124_pmc.c184 enum tegra_powergate_id id, int ena) in tegra124_pmc_set_powergate() argument
192 if (((reg != 0) && ena) || ((reg == 0) && !ena)) { in tegra124_pmc_set_powergate()
/src/sys/contrib/device-tree/src/arm/ti/omap/
H A Dam335x-sbc-t335.dts158 dvi-ena-hog {
164 lcd-ena-hog {
/src/sys/contrib/device-tree/Bindings/scsi/
H A Dhisilicon-sas.txt18 - ctrl-clock-ena-reg : offset to controller clock enable register in ctrl reg
72 ctrl-clock-ena-reg = <0x338>;
/src/sys/arm64/nvidia/tegra210/
H A Dtegra210_pmc.c220 enum tegra_powergate_id id, int ena) in tegra210_pmc_set_powergate() argument
228 if (((reg != 0) && ena) || ((reg == 0) && !ena)) { in tegra210_pmc_set_powergate()
/src/sys/contrib/openzfs/cmd/zed/agents/
H A Dzfs_diagnosis.c561 uint64_t ena, pool_guid, vdev_guid, parent_guid; in zfs_fm_recv() local
654 if (nvlist_lookup_uint64(nvl, FM_EREPORT_ENA, &ena) != 0) in zfs_fm_recv()
655 ena = 0; in zfs_fm_recv()
761 data.zc_ena = ena; in zfs_fm_recv()
/src/sys/contrib/device-tree/src/arm/samsung/
H A Dexynos4412-n710x.dts28 maxim,ena-gpios = <&gpm1 0 GPIO_ACTIVE_HIGH>;
H A Dexynos4412-galaxy-s3.dtsi90 maxim,ena-gpios = <&gpm0 3 GPIO_ACTIVE_HIGH>;
H A Ds5pv210-fascinate4g.dts141 headset_micbias_ena: headset-micbias-ena-pins {
153 main_micbias_ena: main-micbias-ena-pins {
/src/release/
H A DMakefile.ec291 ${BOOTMODEOPT} --sriov --ena \
/src/sys/contrib/device-tree/src/arm64/hisilicon/
H A Dhip06.dtsi616 ctrl-clock-ena-reg = <0x338>;
659 ctrl-clock-ena-reg = <0x318>;
701 ctrl-clock-ena-reg = <0x3a8>;
/src/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mm-iot-gateway.dts11 regulator-usbhub-ena {
/src/sys/arm/mv/
H A Dmv_common.c403 int i, ena, compat; in mv_fdt_pm() local
405 ena = 1; in mv_fdt_pm()
415 ena = 0; in mv_fdt_pm()
423 return (ena); in mv_fdt_pm()

12