| /src/sys/amd64/vmm/io/ |
| H A D | vlapic.c | 813 vlapic_calcdest(struct vm *vm, cpuset_t *dmask, uint32_t dest, bool phys, in vlapic_calcdest() argument
827 *dmask = vm_active_cpus(vm); in vlapic_calcdest()
835 CPU_ZERO(dmask); in vlapic_calcdest()
839 CPU_SET(vcpuid, dmask); in vlapic_calcdest()
863 CPU_ZERO(dmask); in vlapic_calcdest()
897 CPU_SET(vcpuid, dmask); in vlapic_calcdest()
1037 cpuset_t dmask, ipimask; in vlapic_icrlo_write_handler() local
1061 vlapic_calcdest(vlapic->vm, &dmask, dest, phys, false, x2apic(vlapic)); in vlapic_icrlo_write_handler()
1064 CPU_SETOF(vlapic->vcpuid, &dmask); in vlapic_icrlo_write_handler()
1067 dmask = vm_active_cpus(vlapic->vm); in vlapic_icrlo_write_handler()
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| /src/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | MIMGInstructions.td | 426 DMask:$dmask, UNorm:$unorm, CPol:$cpol,
429 let AsmString = asm#" $vdata, $vaddr, $srsrc$dmask$unorm$cpol$r128$tfe$lwe$da"
439 DMask:$dmask, UNorm:$unorm, CPol:$cpol,
442 let AsmString = asm#" $vdata, $vaddr, $srsrc$dmask$unorm$cpol$r128$lwe$da"
450 let InOperandList = !con((ins AddrRC:$vaddr0, SReg_256:$srsrc, DMask:$dmask,
454 let AsmString = opcode#" $vdata, $vaddr0, $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe"
463 (ins SReg_256:$srsrc, DMask:$dmask,
467 let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe"
475 let InOperandList = !con((ins AddrRC:$vaddr0, SReg_256:$srsrc, DMask:$dmask,
479 let AsmString = opcode#" $vdata, $vaddr0, $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe"
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| H A D | SIInstrFormats.td | 340 bits<4> dmask;
350 let Inst{11-8} = dmask;
405 bits<4> dmask;
422 let Inst{11-8} = dmask;
445 bits<4> dmask;
459 let Inst{25-22} = dmask;
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| H A D | SILoadStoreOptimizer.cpp | 335 TII.getNamedOperand(MI, AMDGPU::OpName::dmask)->getImm(); in getOpcodeWidth()
798 DMask = LSO.TII->getNamedOperand(*I, AMDGPU::OpName::dmask)->getImm(); in setMI()
1442 AMDGPU::getNamedOperandIdx(CI.I->getOpcode(), AMDGPU::OpName::dmask); in mergeImagePair()
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| H A D | SIISelLowering.cpp | 14828 unsigned DmaskIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::dmask) - 1; in adjustWritemask()
15048 AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::dmask)) { in PostISelFolding()
15149 MachineOperand *MO_Dmask = TII->getNamedOperand(MI, AMDGPU::OpName::dmask); in AddMemOpInit()
15154 unsigned dmask = MO_Dmask->getImm(); in AddMemOpInit() local
15157 unsigned ActiveLanes = TII->isGather4(MI) ? 4 : llvm::popcount(dmask); in AddMemOpInit()
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| H A D | SIInstrInfo.td | 1106 def DMask : NamedIntOperand<i16, "dmask">;
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| H A D | SIInstrInfo.cpp | 4874 const MachineOperand *DMask = getNamedOperand(MI, AMDGPU::OpName::dmask); in verifyInstruction()
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| /src/sys/amd64/vmm/ |
| H A D | vmm_lapic.c | 73 cpuset_t dmask; in lapic_set_local_intr() local
78 dmask = vm_active_cpus(vm); in lapic_set_local_intr()
79 CPU_FOREACH_ISSET(cpu, &dmask) { in lapic_set_local_intr()
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| H A D | vmm_dev_machdep.c | 89 __BITSET_DEFINE(, 256) dmask;
237 cpuset_t *dmask; in vmmdev_machdep_ioctl() local
240 dmask = vm_exitinfo_cpuset(vcpu); in vmmdev_machdep_ioctl()
242 BIT_ZERO(256, &ipi->dmask); in vmmdev_machdep_ioctl()
243 CPU_FOREACH_ISSET(cpu, dmask) { in vmmdev_machdep_ioctl()
246 BIT_SET(256, cpu, &ipi->dmask); in vmmdev_machdep_ioctl()
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| /src/sys/contrib/zlib/ |
| H A D | inffast.c | 69 unsigned dmask; /* mask for first level of distance codes */ in inflate_fast() local
96 dmask = (1U << state->distbits) - 1; in inflate_fast()
138 here = dcode + (hold & dmask); in inflate_fast()
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| /src/usr.sbin/bhyve/amd64/ |
| H A D | vmexit.c | 477 cpuset_t *dmask; in vmexit_ipi() local
481 dmask = vmrun->cpuset; in vmexit_ipi()
486 CPU_FOREACH_ISSET(i, dmask) { in vmexit_ipi()
495 CPU_FOREACH_ISSET(i, dmask) { in vmexit_ipi()
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| /src/sys/fs/cd9660/ |
| H A D | cd9660_mount.h | 46 mode_t dmask; /* file mask to be applied for directories */ member
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| H A D | cd9660_vfsops.c | 112 ma = mount_argf(ma, "dirmask", "%d", args.dmask); in cd9660_cmount()
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| /src/usr.sbin/bhyve/ |
| H A D | bhyverun.c | 631 cpuset_t active_cpus, dmask; in vm_loop() local
637 vmrun.cpuset = &dmask; in vm_loop()
638 vmrun.cpusetsize = sizeof(dmask); in vm_loop()
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| /src/sbin/routed/rtquery/ |
| H A D | rtquery.c | 590 u_int mask, dmask; in rip_input() local
640 dmask = mask & -mask; in rip_input()
646 } else if (mask + dmask == 0) { in rip_input()
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| /src/sbin/routed/ |
| H A D | trace.c | 425 naddr dmask; in addrname() local
437 dmask = mask & -mask; in addrname()
438 if (mask + dmask == 0) { in addrname()
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| /src/sys/net/ |
| H A D | route.h | 435 const struct sockaddr *smask, struct sockaddr_storage *dmask);
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| H A D | rtsock.c | 1693 struct sockaddr_storage *dmask) in rtsock_fix_netmask() argument
1698 memset(dmask, 0, dst->sa_len); in rtsock_fix_netmask()
1699 memcpy(dmask, smask, smask->sa_len); in rtsock_fix_netmask()
1700 dmask->ss_len = dst->sa_len; in rtsock_fix_netmask()
1701 dmask->ss_family = dst->sa_family; in rtsock_fix_netmask()
1703 return ((struct sockaddr *)dmask); in rtsock_fix_netmask()
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| /src/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/ |
| H A D | AMDGPUDisassembler.cpp | 959 AMDGPU::OpName::dmask); in convertMIMGInst()
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| /src/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 3868 int DMaskIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dmask); in validateMIMGDataSize()
3985 int DMaskIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dmask); in validateMIMGAtomicDMask()
4003 int DMaskIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dmask); in validateMIMGGatherDMask()
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| /src/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | IntrinsicsAMDGPU.td | 858 !if(P_.IsAtomic, [], [llvm_i32_ty]), // dmask(imm)
|